CN108880567B - Error checking and correcting decoder - Google Patents

Error checking and correcting decoder Download PDF

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CN108880567B
CN108880567B CN201810282788.8A CN201810282788A CN108880567B CN 108880567 B CN108880567 B CN 108880567B CN 201810282788 A CN201810282788 A CN 201810282788A CN 108880567 B CN108880567 B CN 108880567B
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circuit
finite field
value
syndrome
error
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CN108880567A (en
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连存德
张雅廸
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/07—Arithmetic codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/157—Polynomial evaluation, i.e. determination of a polynomial sum at a given value
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/617—Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials

Abstract

An Error Checking and Correcting (ECC) decoder is provided for BCH decoding to decode a codeword into decoded data. The ECC decoder includes a syndrome generating circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generating circuit may generate a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit may perform an arithmetic operation by using the syndromes to generate coefficients of the error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit may solve at least one solution of an error locator polynomial having the coefficients and correct the codeword according to the solution of the error locator polynomial to generate the decoded data.

Description

Error checking and correcting decoder
Technical Field
The present invention relates to a decoding circuit, and more particularly, to an error checking and correcting decoder.
Background
Reliability of data is an important issue during data transmission and/or data storage. For example, a Non-volatile memory (Non-volatile memory) has characteristics such as data Non-volatility, power saving, and small size, and is therefore applicable to various electronic devices. Generally, data to be written into a non-volatile memory is encoded by an Error Checking and Correcting (ECC) encoder to generate a corresponding ECC code, and then a codeword (codeword) containing the data and the ECC code is stored in the non-volatile memory. Conversely, the ECC decoder may obtain a codeword (encoded data) from the non-volatile memory and then perform an ECC decoding procedure to decode the codeword into decoded data. That is, the ECC decoder can correct the error bits in the read data by using the corresponding error checking and correcting codes.
The ECC decoding procedure used in the non-volatile memory may be a Bose-Chaudhuri-Hocquenghem (BCH) decoding procedure. However, as the memory capacity increases, the time taken to perform BCH decoding also increases. Accordingly, how to reduce the time required for BCH decoding (to improve decoding efficiency) and how to reduce the power consumption required for BCH decoding are issues of concern to those skilled in the art.
Disclosure of Invention
The present invention provides an Error Checking and Correcting (ECC) decoder for BCH decoding.
An embodiment of the present invention provides an ECC decoder for performing a BCH decoding method to decode a codeword (codeword) into decoded data. The ECC decoder includes a syndrome generating circuit, an error locator polynomial (error locator polynomial) circuit, and a decoding circuit. The syndrome generating circuit may receive the codeword. The syndrome generating circuit may generate a plurality of syndromes corresponding to the codeword. At least one input terminal of the error locator polynomial circuit is coupled to at least one output terminal of the syndrome generating circuit for receiving the plurality of syndromes. The error locator polynomial circuit may perform an arithmetic operation by using the syndromes to generate coefficients of the error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit is coupled to at least one output terminal of the error locator polynomial circuit to receive the coefficients. The decoding circuit may correct the codeword according to at least one solution of the error locator polynomial having the coefficients to generate the decoded data.
Based on the above, the ECC decoder according to the embodiments of the present invention can perform BCH decoding. The lookup table circuit is used to implement part of operators in the BCH decoding process to increase the speed and reduce the power consumption.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of an error checking and correcting decoder according to an embodiment of the present invention;
FIG. 2 is a block diagram illustrating the error locator polynomial circuit of FIG. 1 according to one embodiment of the present invention;
FIG. 3 is a block diagram of an error locator polynomial circuit of FIG. 1 according to another embodiment of the present invention;
FIG. 4 is a block diagram illustrating the error locator polynomial circuit of FIG. 1 according to yet another embodiment of the present invention;
FIG. 5 is a block diagram illustrating an error locator polynomial circuit of FIG. 1 according to yet another embodiment of the present invention.
The reference numbers illustrate:
10: non-volatile memory device
11: nonvolatile memory
12: code word
13: decoded data
20: main unit
100: ECC decoder
110: syndrome generating circuit
120: error locating polynomial circuit
121: first arithmetic circuit
121 a: limited field squaring circuit
121 b: finite field multiplication circuit
121 c: finite field addition circuit
121 d: look-up table circuit
122: second arithmetic circuit
122 a: limited field squaring circuit
122 b: finite field multiplication circuit
122 c: finite field addition circuit
123: look-up table circuit
124: finite field addition circuit
125: finite field multiplication circuit
126: error flag circuit
127: error flag circuit
128: error flag circuit
129: multiplexer
130: decoding circuit
201: square value of finite field
202: finite field product value
203: finite field product value
211: cubic value of finite field
212: square value of finite field
310: look-up table circuit
400: arithmetic circuit
410: arithmetic circuit
410': arithmetic circuit
411: look-up table circuit
411 a: cubic value of finite field
412: finite field addition circuit
412 a: finite field addition value
413: look-up table circuit
413 a: first order square value of finite field
414: look-up table circuit
414 a: limited field quintic value
415: finite field addition circuit
415 a: finite field addition value
416: finite field multiplication circuit
417: look-up table circuit
417 a: first finite field arithmetic value
418: look-up table circuit
418 a: second finite field arithmetic value
420: arithmetic circuit
421: finite field multiplication circuit
422: finite field addition circuit
421 a: finite field product value
430: arithmetic circuit
431: limited field squaring circuit
431 a: square value of finite field
432: finite field addition circuit
a0': value of constant term
a1': first order square term value
a2': value of quadratic term
a3': value of the third power
b0: coefficient of constant term
b1: coefficient of first order square term
C: coefficient of performance
d: internal value
E1F: flag signal for error bit number
E2F: flag signal for error bit number
EF: error flag signal
S, S1, S3, S5: check-up sub
Detailed Description
Referring to fig. 1, a nonvolatile memory device 10 includes a nonvolatile memory 11 and an ECC decoder 100. The non-volatile memory 11 outputs a codeword 12 to an input of the ECC decoder 100. The ECC decoder 100 may perform a BCH decoding method. Thus, ECC decoder 100 may decode codeword 12 into decoded data 13 and then provide decoded data 13 to host 20.
In the embodiment shown in fig. 1, the ECC decoder 100 includes a syndrome generating circuit 110, an error locator polynomial (error locator polynomial) circuit 120, and a decoding circuit 130. Syndrome generating circuit 110 may receive codeword 12 from non-volatile memory 11. The syndrome generating circuit 110 can generate a plurality of syndromes S corresponding to the codeword 12 by using the BCH decoding method.
Assume that the codeword 12 has N bits, and the ECC decoder 100 can correct at most m error bits in the codeword 12, where N and m are integers. The N and m may be determined according to design requirements. For example, the codeword 12 has 64 bits (N ═ 64), and the ECC decoder 100 can correct at most 3 error bits (m ═ 3) in the codeword 12. In the application scenario where m is 3, the syndrome generating circuit 110 can calculate 3 syndromes S, such as syndrome S1, syndrome S3, and syndrome S5.
The input terminal of the error locator polynomial circuit 120 is coupled to the output terminal of the syndrome generating circuit 110 to receive the syndromes S. The error locator polynomial circuit 120 may perform an arithmetic operation by using the syndromes S to generate coefficients C in the error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table (LUT) circuit. The lookup table circuit may include a Read Only Memory (ROM) or other memory to store the lookup table.
In some embodiments, the error locator polynomial may be
Figure BDA0001615107120000041
And wherein the coefficient C may be a coefficient ai. In the application scenario where m is 3, the error locator polynomial circuit 120 may generate the error locator polynomial a by performing an arithmetic operation using the syndrome S1, the syndrome S3, and the syndrome S53X3+a2X2+a1X+a0Coefficient of cubic power a in 03Coefficient of quadratic term a2First order square term coefficient a1Coefficient of constant term a0。
In other embodiments, the error locator polynomial may be
Figure BDA0001615107120000042
And wherein the coefficient C may be the coefficient bi. In the application scenario where m is 3, the error locator polynomial circuit 120 may generate the error locator polynomial X by performing an arithmetic operation using the syndrome S1, the syndrome S3, and the syndrome S53+S1X2+b1X+b0Coefficient of first power term b in 01Coefficient of constant term b0。
The decoding circuit 130 is coupled to the output of the error locator polynomial circuit 120 to receive the coefficients C. By using the BCH decoding method, the decoding circuit 130 can find at least one solution (or at least one root) of the error locator polynomial with these coefficients C and correct the code word 12 in dependence on the solution (root) of the error locator polynomial to produce the decoded data 13.
In the application scenario where m is 3, the decoding circuit 130 may obtain the error locator polynomial a3X3+a2X2+a1X+a0At least one solution of 0, where the solution (root) of X may indicate the location of the error bit in codeword 12. By inverting the bit value of the error bit, the decoding circuit 130 can correct the error bit. Thus, the decoding circuit 130 can obtain the corrected decoded data 13. For example, assume that the codeword 12 has a four-bit value of "1111" and assume that the solution of X is "0001" (representing the first bit in the codeword 12 as an error bit), so the decoding circuit 130 can invert the first bit of the codeword 12, so that the decoded data 13 is "1110".
FIG. 2 is a block diagram illustrating the error locator polynomial 120 of FIG. 1 according to one embodiment of the present invention. In the embodiment shown in fig. 2, the ECC decoder 100 is assumed to correct at most 3 error bits (m equals to 3) in the codeword 12. In the application scenario where m is 3, the 3 syndromes S outputted by the syndrome generating circuit 110 to the error locator polynomial circuit 120 include syndrome S1, syndrome S3, and syndrome S5. The number of bits of the syndrome S1, the syndrome S3, and the syndrome S5 can be determined according to design requirements. For example, any of syndrome S1, syndrome S3, and syndrome S5 may be a 6-bit value.
The error locator polynomial circuit 120 includes a first arithmetic circuit 121 and a second arithmetic circuit 122. By using some or all of these syndromes S, the first arithmetic circuit 121 can perform a first finite field (finite field) arithmetic operation to generate a first-order term value a1'. The second arithmetic circuit 122 is coupled to the first arithmetic circuit 121 for receiving the first power term a1'. By using some or all of these syndromes S, and by using the one-time term value a1' and the second arithmetic circuit 122 may perform a second finite field arithmetic operation,to generate a constant term value a0'. The finite field arithmetic operations are also referred to as Galois Field (GF) arithmetic operations. For example, in the application scenario where syndrome S1, syndrome S3, and syndrome S5 are all 6-bit syndromes, the order of finite field arithmetic is 64 (i.e., 2)6Generally indicated by GF (64).
In the embodiment shown in fig. 2, the first arithmetic circuit 121 includes a finite field squaring circuit 121a, a finite field multiplying circuit 121b and a finite field adding circuit 121 c. The finite field squaring circuit 121a receives and uses the syndrome S1 of the syndromes S to perform a finite field squaring operation to generate a finite field squared value 201 of the syndrome S1, i.e., (S1)2Finite field arithmetic value of. In some embodiments, a first order exclusive or gate (1-stage XOR gate) may be used to implement the field-limited squaring circuit 121 a. The finite field multiplying circuit 121b is coupled to the finite field squaring circuit 121a to receive the finite field squared value 201. Finite field multiplication circuit 121b performs a finite field multiplication operation using finite field squared value 201 and syndrome S3 of syndromes S to produce finite field product value 202, i.e. (S1)2Finite field arithmetic values of S3. In some embodiments, a first-order AND gate (1-stage AND gate) AND a 4-order exclusive OR gate (4-stage XOR gate) may be used to implement the finite field multiplication circuit 121 b. The finite field adder circuit 121c is coupled to the finite field multiplier circuit 121b to receive the finite field product value 202. The finite field addition circuit 121c performs a finite field addition operation using the finite field product value 202 and the syndrome S5 among the syndromes S to generate a first-order term value a1', i.e. (S1)2Finite field arithmetic values of S3+ S5. In some embodiments, a first order exclusive or gate (1-stage XOR gate) may be used to implement the limited field addition circuit 121 c.
In the embodiment shown in FIG. 2, the error locator polynomial 120 further includes a look-up table circuit 123 and a finite field addition circuit 124. The lookup table circuit 123 receives and uses the syndrome S1 of these syndromes S to lookup a lookup table to obtain the finite field cube value 211 of the syndrome S1, i.e., (S1)3Finite field arithmetic value of. In case of "syndrome S1 is a 6-bit value" and "finite field cubic value 211 isIn the application context of 6-bit value, the lookup table circuit 123 has a storage space of 63 × 6 bits for storing the "S1 transform (S1)3"look-up table.
The finite field addition circuit 124 is coupled to the look-up table circuit 123 to receive the finite field cube 211. The finite field addition circuit 124 performs a finite field addition operation using the finite field cube 211 and a syndrome S3 of the syndromes S to generate a cubic term value a3', i.e. (S1)3A finite field arithmetic value of + S3. In some embodiments, a first order exclusive OR gate (1-stage XOR gate) may be used to implement the finite field addition circuit 124.
The second arithmetic circuit 122 is further coupled to the finite field addition circuit 124 for receiving the cubic term a3'. By using some or all of these syndromes S and by using the one-time term value a1' with the value of the cubic term a3', the second arithmetic circuit 122 may perform the second finite field arithmetic operation to generate the constant term value a0'. In the embodiment shown in fig. 2, the second arithmetic circuit 122 includes a finite field squaring circuit 122a, a finite field multiplying circuit 122b, and a finite field adding circuit 122 c. The finite field squaring circuit 122a is coupled to the finite field adding circuit 124 to receive the cubic term a3'. The finite field squaring circuit 122a uses a cubic term a3To perform a finite field squaring operation to generate a cubic term a3The finite field squared value of 212, i.e. (a)3’)2Finite field arithmetic value of. In the embodiment shown in FIG. 2, the value of the cubic term a3' is (S1)3+ S3. In some embodiments, a first order exclusive OR gate (1-stage XOR gate) may be used to implement the field-limited squaring circuit 122 a.
The finite field multiplication circuit 122b is coupled to the first arithmetic circuit 121 for receiving the first power term value a1'. The finite field multiplying circuit 122b uses the first power term value a1' carry out finite field multiplication with syndrome S1 to generate finite field product value 203, i.e. a1' S1. In the embodiment shown in FIG. 2, the first power term value a1' is (S1)2S3+ S5. In some casesIn one embodiment, a first-order AND gate (1-stage AND gate) AND a 4-order XOR gate (4-stage XOR gate) may be used to implement the finite field multiplier circuit 122 b. The finite field adder 122c is coupled to the finite field multiplier 122b and the finite field squarer 122a for receiving the finite field product value 203 and the finite field square value 212, respectively. The finite field addition circuit 122c performs a finite field addition operation using the finite field product value 203 and the finite field square value 212 to generate a constant term value a0', i.e. a1’*S1+(a3’)2Finite field arithmetic value of. In some embodiments, a first order exclusive or gate (1-stage XOR gate) may be used to implement the limited field addition circuit 122 c.
In the embodiment shown in FIG. 2, the error locator polynomial circuit 120 further includes a finite field multiplier circuit 125. The finite field multiplying circuit 125 is coupled to the finite field adding circuit 124 to receive the third power term a3'. Finite field multiplication circuit 125 uses a value of the third power term a3' carry out finite field multiplication with syndrome S1 to generate a quadratic term value a2', i.e. a3' S1. In some embodiments, a first order AND gate (1-stage AND gate) AND a 4-stage XOR gate (4-stage XOR gate) may be used to implement the finite field multiplication circuit 125.
In the embodiment shown in FIG. 2, the error locator polynomial 120 further includes an error flag circuit 126. The error flag circuit 126 receives the syndrome S1 and the syndrome S3 of the syndromes S, and checks bits of the syndrome S1 and bits of the syndrome S3. Based on the checking result, the error flag circuit 126 generates the error flag signal EF to the decoding circuit 130. The error flag signal EF is used to indicate whether there are error bits in the codeword 12. For example, the error flag signal EF may be a logic "1" when the codeword 12 has an error bit. Conversely, the error flag signal EF may be a logic "0" when the codeword 12 has no error bits. In some embodiments, the error flag circuit 126 determines that all bits of the syndrome S1 are 0 and that all bits of the syndrome S3 are 0. When both of these two determination conditions are satisfied (both are true), the error flag circuit 126 sets the error flag signal EF to logic "0", otherwise sets the error flag signal EF to logic "1".
In the embodiment shown in FIG. 2, the error locator polynomial 120 further includes an error flag circuit 127. The error flag circuit 127 is coupled to the error flag circuit 126 and the finite field addition circuit 124 for receiving the error flag signal EF and the cubic term a3'. The error flag circuit 127 can check the error flag signal EF and the cubic term a3A plurality of bits of. Based on the checking result, the error flag circuit 127 can generate the error number of bits flag signal E1F to the decoding circuit 130. The error bit number flag signal E1F is used to indicate whether the number of error bits in the codeword 12 is 1. For example, when the codeword 12 has 1 error bit, the error bit quantity flag signal E1F can be a logic "1". In addition, the error bit number flag signal E1F is logic "0". In some embodiments, the error flag circuit 127 has the determination conditions of "error flag signal EF is 1" and "cubic term a3All bits of 'are 0'. When both of these two determination conditions are satisfied (both are true), the error flag circuit 127 sets the error number of bits flag signal E1F to logic "1", otherwise sets the error number of bits flag signal E1F to logic "0".
In the embodiment shown in FIG. 2, the error locator polynomial 120 further includes an error flag circuit 128. The error flag circuit 128 is coupled to the error flag circuit 126, the second arithmetic circuit 122 and the finite field addition circuit 124 for receiving the error flag signal EF and the constant term a0' with the value of the cubic term a3'. The error flag circuit 128 can check the error flag signal EF and the constant term value a0' the multiple bits and the cubic term a3A plurality of bits of. Based on the checking result, the error flag circuit 128 generates an error bit number flag signal E2F to the decoding circuit 130. The error bit number flag signal E2F is used to indicate whether the number of error bits in the codeword 12 is 2. For example, when the codeword 12 has 2 error bits, the error bit quantity flag signal E2F can be a logic "1". In addition to this, errorsThe bit number flag signal E2F is logic "0". In some embodiments, the error flag circuit 128 determines the conditions as "error flag signal EF is 1" and "cubic term a3' any one bit of the constant is not 00All bits of 'are 0'. When all of the three determination conditions are satisfied (all are true), the error flag circuit 128 sets the error number of bits flag signal E2F to logic "1", otherwise sets the error number of bits flag signal E2F to logic "0".
In the embodiment shown in FIG. 2, the error locator polynomial circuit 120 further includes a multiplexer 129. In the first mode (i.e. when the error bit number flag signal E1F is 0), the multiplexer 129 applies the value of the third power a3', quadratic term value a2', first order square term value a1' and constant term a0' output to the decoding circuit 130 as a cubic term coefficient, a quadratic term coefficient, a first order term coefficient, and a constant term coefficient among the plurality of coefficients C of the error locator polynomial. For example, assume that the error locator polynomial is a3X3+a2X2+a1X+a00, then in the first mode, the value of the cubic term a3' as coefficient of cubic term a3Value of the quadratic term a2' as a coefficient of quadratic term a2First order square term value a1' as a first-order term coefficient a1And constant term a0' coefficient a as constant term0。
In the second mode (i.e., when the error bit number flag signal E1F is 1), the multiplexer 129 outputs "0", "1", and "syndrome S1" to the decoding circuit 130 as the coefficient of the error locator polynomial, such as the coefficient of the cubic term, the coefficient of the quadratic term, the coefficient of the first order term, and the coefficient of the constant term among the coefficients C. For example, assume that the error locator polynomial is a3X3+a2X2+a1X+a0In the second mode, the error locator polynomial is X + S1 equal to 0.
In any case, the implementation of the error locator polynomial circuit 120 shown in fig. 1 should not be limited to the implementation example shown in fig. 2. For example, FIG. 3 is a block diagram illustrating the error locator polynomial 120 of FIG. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 3, the ECC decoder 100 is assumed to correct at most 3 error bits (m equals to 3) in the codeword 12. In the application scenario where m is 3, the 3 syndromes S outputted by the syndrome generating circuit 110 to the error locator polynomial circuit 120 include syndrome S1, syndrome S3, and syndrome S5.
The error locator polynomial circuit 120 includes a first arithmetic circuit 121 and a second arithmetic circuit 122. By using some or all of the syndromes S, the first arithmetic circuit 121 can perform a first finite field arithmetic operation to generate a first-order term value a1'. The second arithmetic circuit 122 is coupled to the first arithmetic circuit 121 for receiving the first power term a1'. By using some or all of these syndromes S, and by using the one-time term value a1', the second arithmetic circuit 122 may perform a second finite field arithmetic operation to generate the constant term value a0’。
In the embodiment shown in fig. 3, the first arithmetic circuit 121 includes a look-up table circuit 121d and a finite field addition circuit 121 c. The lookup table circuit 121d receives and uses the syndrome S1 and the syndrome S3 of the syndromes S to lookup a lookup table to obtain the finite field squared value of the syndrome S1 and the finite field product value 202 of the syndrome S3, i.e., (S1)2Finite field arithmetic values of S3. For example, in the application scenario of "syndrome S1 is a 6-bit value" and "syndrome S3 is a 6-bit value", the lookup table circuit 121d has 63 × 64 × 6-bit storage space for storing "convert S1 and S3 into (S1)2S3 "look-up table. The finite field adder circuit 121c is coupled to the look-up table circuit 121d to receive the finite field product value 202. The finite field addition circuit 121c may perform a finite field addition operation using the finite field product value 202 and a syndrome S5 of the syndromes S to produce a first power term value a1', i.e. (S1)2Finite field arithmetic values of S3+ S5.
In the embodiment shown in FIG. 3, the error locator polynomial 120 further includes a look-up table circuit 310. The look-up table circuit 310 receives andusing syndrome S1 and syndrome S3 of these syndromes S, a lookup table is looked up to obtain a finite field cube value of syndrome S1 and a finite field sum value of syndrome S3, i.e., (S1)3A finite field arithmetic value of + S3. The finite field addition value (i.e., (S1)3+ S3) as the value of the cubic term a3'. For example, in the application scenario of "syndrome S1 is a 6-bit value" and "syndrome S3 is a 6-bit value", the lookup table circuit 310 has 63 × 64 × 6-bit storage space for storing "convert S1 and S3 (S1)3+ S3 "look-up table.
In the embodiment shown in FIG. 3, the second arithmetic circuit 122 is further coupled to the lookup table circuit 310 for receiving the cubic term a3'. By using some or all of these syndromes S and by using the one-time term value a1' with the value of the cubic term a3', the second arithmetic circuit 122 may perform the second finite field arithmetic operation to generate the constant term value a0'. The second arithmetic circuit 122 shown in fig. 3 can be analogized with the related description of the second arithmetic circuit 122 shown in fig. 2, and therefore, the description thereof is omitted.
In the embodiment shown in FIG. 3, the error locator polynomial circuit 120 further includes a finite field multiplier circuit 125, an error flag circuit 126, an error flag circuit 127, an error flag circuit 128, and a multiplexer 129. The finite field multiplication circuit 125, the error flag circuit 126, the error flag circuit 127, the error flag circuit 128, and the multiplexer 129 shown in FIG. 3 can be analogized with reference to the related description of FIG. 2, and therefore, they are not described again.
In other embodiments, the coefficients of the third power in the error locator polynomial may be set to 1 and the coefficients of the second power in the error locator polynomial may be set to syndrome S1 in these syndromes S. For example, in the application scenario of "the ECC decoder 100 can correct at most 3 error bits (m is 3)" in the codeword 12, the error locator polynomial a3X3+a2X2+a1X+a0＝X3+(a2/a3)X2+(a1/a3)X+(a0/a3)＝X3+S1X2+b1X+b00, wherein b1＝(S1)2+d，b0D ═ S1 × d + S3, and d ═ S15+S5]*[(S1)3+S3]-1. Thus, the error locator polynomial circuit 120 may output the syndrome S1, the first-order coefficient b1Coefficient of constant term b0To the decoding circuit 130 as coefficient C.
FIG. 4 is a block diagram illustrating the error locator polynomial circuit 120 of FIG. 1 according to yet another embodiment of the present invention. In the embodiment shown in fig. 4, the ECC decoder 100 is assumed to correct at most 3 error bits (m equals to 3) in the codeword 12. In the application scenario where m is 3, the 3 syndromes S outputted by the syndrome generating circuit 110 to the error locator polynomial circuit 120 include syndrome S1, syndrome S3, and syndrome S5. The error locator polynomial circuit 120 may generate the error locator polynomial X by performing an arithmetic operation using the syndrome S1, the syndrome S3, and the syndrome S53+S1X2+b1X+b0Coefficient of first power term b in 01Coefficient of constant term b0To the decoding circuit 130.
The decoding circuit 130 is coupled to the output of the error locator polynomial circuit 120 to receive the syndrome S1 and the first-order coefficient b1Coefficient of constant term b0As coefficient C. By using the BCH decoding method, the decoding circuit 130 can find the error positioning polynomial X in the application scenario where m is 33+S1X2+b1X+b0At least one solution of 0, where the solution (root) of X may indicate the location of the error bit in codeword 12. By inverting the bit value of the error bit, the decoding circuit 130 can correct the error bit.
In the embodiment shown in FIG. 4, the error locator polynomial circuit 120 includes an arithmetic circuit 400. The arithmetic circuit 400 performs a finite field arithmetic operation using some or all of the syndromes S to generate a first-order coefficient b of the coefficients C of the error locator polynomial1And constant term coefficient b0To the decoding circuit 130. The arithmetic circuit 400 includes an arithmetic circuit 410, an arithmetic circuit 420, and an arithmetic circuit 430. Arithmetic circuit410 perform a first finite field arithmetic operation using some or all of the syndromes S to generate an internal value d. The arithmetic circuit 420 is coupled to the arithmetic circuit 410 to receive the internal value d. By using some or all of the syndromes S and by using the internal value d, the arithmetic circuit 420 can perform a second finite field arithmetic operation to generate the constant term coefficient b of the coefficients C of the error locator polynomial0To the decoding circuit 130. The arithmetic circuit 430 is coupled to the arithmetic circuit 410 to receive the internal value d. By using some or all of the syndromes S and by using the internal value d, the arithmetic circuit 430 can perform a third finite field arithmetic operation to generate a first-order coefficient b of the coefficients C of the error locator polynomial1To the decoding circuit 130.
In the embodiment shown in fig. 4, the arithmetic circuit 410 includes a lookup table circuit 411, a finite field addition circuit 412, a lookup table circuit 413, a lookup table circuit 414, a finite field addition circuit 415, and a finite field multiplication circuit 416. The lookup table circuit 411 receives and uses the syndrome S1 to lookup the first lookup table to obtain the finite field cube value 411a of the syndrome S1, i.e. (S1)3Finite field arithmetic value of. For example, in the application scenario of "syndrome S1 is a 6-bit value" and "finite field cube value 411a is a 6-bit value", the lookup table circuit 411 has 63 × 6-bit storage space for storing "S1 transform (S1)3"look-up table.
The finite field addition circuit 412 is coupled to the look-up table circuit 411 to receive the finite field cube 411 a. The finite field addition circuit 412 may perform a finite field addition operation using the finite field cube value 411a and a syndrome S3 among the syndromes S to generate a finite field addition value 412a, i.e., (S1)3A finite field arithmetic value of + S3. In some embodiments, a first order exclusive OR gate (1-stage XOR gate) may be used to implement the limited field addition circuit 412. The look-up table circuit 413 is coupled to the finite field addition circuit 412 to receive the finite field addition value 412 a. The lookup table circuit 413 may use the finite field addition value 412a to lookup the second lookup table to obtain the finite field negative first power value 413a of the finite field addition value 412a, i.e., [ (S1)3+S3]-1Is provided withField limited arithmetic values. For example, in the application scenario of "the finite field addition value 412a is a 6-bit value" and "the finite field negative first square value 413a is a 6-bit value", the lookup table circuit 413 has a storage space of 63 × 6 bits to store "will (S1)3+ S3 conversion to [ (S1)3+S3]-1"look-up table.
The lookup table circuit 414 receives and uses the syndrome S1 to lookup a third lookup table to obtain the field-limited quintic-square value 414a of the syndrome S1, i.e., (S1)5Finite field arithmetic value of. For example, in the application scenario of "syndrome S1 is a 6-bit value" and "limited field quintic value 414a is a 6-bit value", the lookup table circuit 414 has 63 × 6-bit storage space for storing "S1 transform (S1)5"look-up table. The finite field addition circuit 415 is coupled to the lookup table circuit 414 to receive the finite field quintic valued 414 a. The finite field addition circuit 415 may perform a finite field addition operation using the finite field quintic values 414a and the syndromes S5 among the syndromes S to generate finite field addition values 415a, i.e., (S1)5A finite field arithmetic value of + S5. In some embodiments, a first order exclusive OR gate (1-stage XOR gate) may be used to implement the limited field addition circuit 415.
The finite field multiplication circuit 416 is coupled to the lookup table circuit 413 and the finite field addition circuit 415 to receive the finite field negative first square 413a and the finite field addition value 415a, respectively. The finite field multiplication circuit 416 may perform a finite field multiplication operation using the finite field negative first square 413a and the finite field addition value 415a to generate an internal value d, [ (S1)5+S5]*[(S1)3+S3]-1Finite field arithmetic value of. In some embodiments, a first order AND gate (1-stage AND gate) AND a 4-stage XOR gate (4-stage XOR gate) may be used to implement the finite field multiplication circuit 416.
In the embodiment shown in fig. 4, the arithmetic circuit 420 includes a finite field multiplication circuit 421 and a finite field addition circuit 422. The finite field multiplication circuit 421 is coupled to the arithmetic circuit 410 to receive the internal value d. The finite field multiplication circuit 421 can perform a finite field multiplication operation using the internal value d and the syndrome S1 to generate a finite field product value 421a, i.e., dFinite field arithmetic values of S1. In some embodiments, a first order AND gate (1-stage AND gate) AND a 4-stage XOR gate (4-stage XOR gate) may be used to implement the finite field multiplication circuit 421. The finite field adder circuit 422 is coupled to the finite field multiplier circuit 421 to receive the finite field product value 421 a. The finite field addition circuit 422 may perform a finite field addition operation using the finite field product value 421a and a syndrome S3 of the syndromes S to produce a constant term coefficient b0To a decoding circuit 130 in which a constant term coefficient b0Is a finite field arithmetic value of d × S1+ S3. In some embodiments, a first order exclusive OR gate (1-stage XOR gate) may be used to implement the limited field addition circuit 422.
In the embodiment shown in fig. 4, the arithmetic circuit 430 includes a finite field squaring circuit 431 and a finite field adding circuit 432. The finite field squaring circuit 431 receives and uses the syndrome S1 to perform a finite field squaring operation to generate a finite field squared value 431a of the syndrome S1, i.e., (S1)2Finite field arithmetic value of. In some embodiments, a first order exclusive OR gate (1-stage XOR gate) may be used to implement the finite field squaring circuit 431. The finite field adder 432 is coupled to the finite field squaring circuit 431 and the arithmetic circuit 410 for receiving the finite field squared value 431a and the internal value d, respectively. The finite field addition circuit 432 performs a finite field addition operation using the finite field squared value 431a and the internal value d to generate a first order coefficient b1To the decoding circuit 130, in which the coefficient of the first power term b1Is (S1)2A finite field arithmetic value of + d.
FIG. 5 is a block diagram illustrating the error locator polynomial circuit 120 of FIG. 1 according to yet another embodiment of the present invention. In the embodiment shown in fig. 5, the ECC decoder 100 is assumed to correct at most 3 error bits (m equals to 3) in the codeword 12. In the application scenario where m is 3, the syndrome S output by the syndrome generating circuit 110 to the error locator polynomial circuit 120 includes syndrome S1, syndrome S3 and syndrome S5. The error locator polynomial circuit 120 may generate the error locator polynomial X by performing an arithmetic operation using the syndrome S1, the syndrome S3, and the syndrome S53+S1X2+b1X+b 01 in 0Coefficient of square b1Coefficient of constant term b0To the decoding circuit 130.
The error locator polynomial circuit 120, the arithmetic circuit 410', the arithmetic circuit 420 and the arithmetic circuit 430 shown in fig. 5 can be analogized by referring to the related descriptions of the error locator polynomial circuit 120, the arithmetic circuit 410, the arithmetic circuit 420 and the arithmetic circuit 430 shown in fig. 4, and thus are not described again.
In the embodiment shown in FIG. 5, the arithmetic circuit 410' includes a finite field multiplication circuit 416, a lookup table circuit 417, and a lookup table circuit 418. The lookup table circuit 417 receives and uses the syndrome S1 and the syndrome S3 to lookup the first lookup table to obtain a first finite field arithmetic value 417a, i.e., [ (S1)3+S3]-1Finite field arithmetic value of. For example, in the application scenario of "syndrome S1 is a 6-bit value" and "syndrome S3 is a 6-bit value", the lookup table circuit 417 has 63 × 64 × 6-bit storage space for storing "convert S1 and S3 into [ (S1)3+S3]-1"look-up table. The lookup table circuit 418 receives and uses the syndrome S1 and the syndrome S5 to lookup a second lookup table to obtain a second finite field arithmetic value 418 a. For example, the lookup table circuit 418 looks up the second lookup table to obtain the limited field quintic value of the syndrome S1 and the limited field addition value of the syndrome S5, i.e. (S1)5A finite field arithmetic value of + S5. For example, in the application scenario of "syndrome S1 is a 6-bit value" and "syndrome S5 is a 6-bit value", the lookup table circuit 418 has 63 × 64 × 6-bit storage space for storing "convert S1 and S5 to (S1)5+ S5 "look-up table. The finite field multiplication circuit 416 is coupled to the lookup table circuit 417 and the lookup table circuit 418 to receive the first finite field arithmetic value 417a and the second finite field arithmetic value 418a, respectively, and performs a finite field multiplication operation using the first finite field arithmetic value 417a and the second finite field arithmetic value 418a to generate an internal value d for the arithmetic circuit 420 and the arithmetic circuit 430.
It is noted that, in various application scenarios, the related functions of the syndrome generating circuit 110, the error locator polynomial circuit 120 and/or the decoding circuit 130 may be implemented as software, firmware or hardware by using a general programming language (e.g. C), a hardware description language (e.g. Verilog HDL) or other suitable programming languages. The programming language that can perform the related functions may be arranged as any known computer-accessible media such as magnetic tape (magnetic tapes), semiconductor (semiconductors) memory, magnetic disk (magnetic disks) or optical disk (compact disks such as CD-ROM), or may be transmitted through the Internet (Internet), wired communication (wired communication), wireless communication (wireless communication), or other communication media. The programming language may be stored in a computer accessible medium for facilitating access/execution of programming codes of the programming language by a processor of the computer. In addition, the apparatus and method of the present invention may be implemented by a combination of hardware and software.
In summary, the ECC decoder 100 according to the embodiments of the present invention can perform BCH decoding. In the BCH decoding process, the lookup table circuit is used to implement one or more operators of the error locator polynomial circuit 120, so as to increase the BCH decoding speed and reduce the power consumption of the error locator polynomial circuit 120.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (19)

1. An error checking and correction decoder for performing a bose-chaudhuri-hocquenghem decoding method for decoding a codeword into decoded data, the error checking and correction decoder comprising:
a syndrome generating circuit for receiving the codeword and generating a plurality of syndromes corresponding to the codeword;
an error locator polynomial circuit having at least one input coupled to the at least one output of the syndrome generating circuit to receive the plurality of syndromes for performing an arithmetic operation using the plurality of syndromes to generate a plurality of coefficients of an error locator polynomial, wherein the arithmetic operation includes a plurality of operators and at least one of the plurality of operators is a lookup table circuit; and
decoding circuitry coupled to at least one output of the error locator polynomial circuitry to receive the plurality of coefficients for correcting the codeword according to at least one solution of the error locator polynomial having the plurality of coefficients to produce the decoded data,
wherein the error locator polynomial circuit comprises:
a first arithmetic circuit for performing a first finite field arithmetic operation by using a part or all of the plurality of syndromes to generate a first power term value; and
a second arithmetic circuit coupled to the first arithmetic circuit to receive the first-order term value, wherein the second arithmetic circuit performs a second finite-field arithmetic operation using part or all of the plurality of syndromes and using the first-order term value to generate a constant term value;
wherein in a first mode, the first-order-term value is a first-order-term coefficient of the plurality of coefficients of the error locator polynomial, and the constant-term value is a constant-term coefficient of the plurality of coefficients of the error locator polynomial.
2. The error checking and correcting decoder of claim 1, wherein in the second mode, 1 is used as the first power term coefficient and a first syndrome of the plurality of syndromes is used as the constant term coefficient.
3. The error checking and correcting decoder of claim 1, wherein the first arithmetic circuit comprises:
a finite field squaring circuit that receives and uses a first syndrome of the plurality of syndromes to perform a finite field squaring operation to produce a finite field squared value of the first syndrome;
finite field multiplication circuitry coupled to the finite field squaring circuitry to receive the finite field squared value and to perform a finite field multiplication operation using the finite field squared value and a second syndrome of the plurality of syndromes to produce a finite field product value; and
a finite field addition circuit coupled to the finite field multiplication circuit to receive the finite field product value and perform a finite field addition operation using the finite field product value and a third syndrome of the plurality of syndromes to generate the one-time term value.
4. The error checking and correcting decoder of claim 1, wherein the error locator polynomial circuit further comprises:
a lookup table circuit that receives and uses a first syndrome of the plurality of syndromes to lookup a lookup table to obtain a finite field cubic value of the first syndrome; and
a first finite field addition circuit coupled to the lookup table circuit to receive the finite field cube value and perform a finite field addition operation using the finite field cube value and a second syndrome of the plurality of syndromes to generate a cubic term value;
wherein the second arithmetic circuit is further coupled to the first finite field addition circuit to receive the cubic term value, the second arithmetic circuit performing the second finite field arithmetic operation using part or all of the plurality of syndromes and using the first term value and the cubic term value to generate the constant term value; and
in the first mode, the cubic term value is taken as a cubic term coefficient of the plurality of coefficients of the error locator polynomial.
5. The error checking and correcting decoder of claim 4,
the second arithmetic circuit includes:
a finite field squaring circuit coupled to the first finite field adding circuit for receiving the cubic term values to perform a finite field squaring operation to generate a finite field squared value of the cubic term values;
a finite field multiplication circuit coupled to the first arithmetic circuit to receive the first-order term value and perform a finite field multiplication operation using the first-order term value and the first syndrome to generate a finite field product value; and
a second finite field addition circuit coupled to the finite field multiplication circuit and the finite field squaring circuit to receive the finite field product value and the finite field squared value, respectively, and to perform the finite field addition operation using the finite field product value and the finite field squared value to generate the constant term value;
the error locator polynomial circuit further comprises:
a finite field multiplication circuit coupled to the first finite field addition circuit to receive the cubic term value and perform a finite field multiplication operation using the cubic term value and the first syndrome to generate a quadratic term value;
wherein in the first mode, the quadratic term value is as a quadratic term coefficient of the plurality of coefficients of the error locator polynomial.
6. The error checking and correcting decoder of claim 4, wherein the error locator polynomial circuit further comprises:
a first error flag circuit for receiving the first syndrome and the second syndrome of the plurality of syndromes and checking a plurality of bits of the first syndrome and a plurality of bits of the second syndrome to generate an error flag signal corresponding thereto to the decoding circuit.
7. The error checking and correcting decoder of claim 6, wherein the error locator polynomial circuit further comprises:
a second error flag circuit coupled to the first error flag circuit and the first finite field addition circuit for receiving the error flag signal and the cubic term value, respectively, for checking a plurality of bits of the error flag signal and the cubic term value to generate an error bit number flag signal corresponding to the error bit number flag signal to the decoding circuit.
8. The error checking and correcting decoder of claim 6, wherein the error locator polynomial circuit further comprises:
a second error flag circuit coupled to the first error flag circuit, the second arithmetic circuit and the first finite field addition circuit for receiving the error flag signal, the constant term value and the cubic term value, respectively, and checking the error flag signal, the bits of the constant term value and the bits of the cubic term value to generate an error bit number flag signal corresponding to the error bit number flag signal to the decoding circuit.
9. The error checking and correcting decoder of claim 1, wherein the first arithmetic circuit comprises:
a lookup table circuit that receives and uses a first syndrome and a second syndrome of the plurality of syndromes to lookup a lookup table to obtain a finite field squared value of the first syndrome and a finite field product value of the second syndrome; and
a finite field addition circuit coupled to the lookup table circuit to receive the finite field product value and to perform a finite field addition operation using the finite field product value and a third syndrome of the plurality of syndromes to generate the first-order term value.
10. The error checking and correcting decoder of claim 1, wherein the error locator polynomial circuit further comprises:
a lookup table circuit that receives and looks up a lookup table using a first syndrome and a second syndrome of the plurality of syndromes to obtain a finite field cubic value of the first syndrome and a finite field addition value of the second syndrome, and takes the finite field addition value as a cubic term value;
wherein the second arithmetic circuit is further coupled to the lookup table circuit to receive the cubic term value, and the second arithmetic circuit performs the second finite field arithmetic operation using part or all of the plurality of syndromes and using the first term value and the cubic term value to generate the constant term value; and
in the first mode, the cubic term value is taken as a cubic term coefficient of the plurality of coefficients of the error locator polynomial.
11. The error checking and correcting decoder of claim 10, wherein the error locator polynomial circuit further comprises:
a finite field multiplication circuit coupled to the lookup table circuit to receive the cubic term value and perform a finite field multiplication operation using the cubic term value and the first syndrome to generate a quadratic term value;
wherein in the first mode, the quadratic term value is as a quadratic term coefficient of the plurality of coefficients of the error locator polynomial.
12. The error checking and correcting decoder of claim 10, wherein the error locator polynomial circuit further comprises:
a first error flag circuit for receiving the first syndrome and the second syndrome from the plurality of syndromes and checking a plurality of bits of the first syndrome and a plurality of bits of the second syndrome to generate an error flag signal corresponding thereto to the decoding circuit; and
a second error flag circuit coupled to the first error flag circuit and the lookup table circuit for receiving the error flag signal and the cubic term value, respectively, for checking a plurality of bits of the error flag signal and the cubic term value to generate an error bit number flag signal corresponding to the error bit number flag signal to the decoding circuit.
13. The error checking and correcting decoder of claim 10, wherein the error locator polynomial circuit further comprises:
a first error flag circuit for receiving the first syndrome and the second syndrome from the plurality of syndromes and checking a plurality of bits of the first syndrome and a plurality of bits of the second syndrome to generate an error flag signal corresponding thereto to the decoding circuit; and
a second error flag circuit coupled to the first error flag circuit, the second arithmetic circuit and the lookup table circuit for receiving the error flag signal, the constant term value and the cubic term value respectively, and checking the error flag signal, the bits of the constant term value and the bits of the cubic term value to generate an error bit quantity flag signal corresponding to the error bit quantity flag signal to the decoding circuit.
14. An error checking and correction decoder for performing a bose-chaudhuri-hocquenghem decoding method for decoding a codeword into decoded data, the error checking and correction decoder comprising:
a syndrome generating circuit for receiving the codeword and generating a plurality of syndromes corresponding to the codeword;
an error locator polynomial circuit having at least one input coupled to the at least one output of the syndrome generating circuit to receive the plurality of syndromes for performing an arithmetic operation using the plurality of syndromes to generate a plurality of coefficients of an error locator polynomial, wherein the arithmetic operation includes a plurality of operators and at least one of the plurality of operators is a lookup table circuit; and
decoding circuitry coupled to at least one output of the error locator polynomial circuitry to receive the plurality of coefficients for correcting the codeword according to at least one solution of the error locator polynomial having the plurality of coefficients to produce the decoded data,
wherein a coefficient of a cubic term in the error locator polynomial is 1, a coefficient of a quadratic term in the error locator polynomial is a first syndrome in the plurality of syndromes, and the error locator polynomial circuit comprises:
an arithmetic circuit for performing a finite field arithmetic operation using part or all of the plurality of syndromes to generate a first order term coefficient and a constant term coefficient of the plurality of coefficients of the error locator polynomial.
15. The error checking and correcting decoder of claim 14, wherein the arithmetic circuit comprises:
a first arithmetic circuit that performs a first finite field arithmetic operation by using part or all of the plurality of syndromes to generate an internal value;
a second arithmetic circuit coupled to the first arithmetic circuit to receive the internal value for performing a second finite field arithmetic operation using part or all of the plurality of syndromes and the internal value to generate the constant term coefficient; and
a third arithmetic circuit, coupled to the first arithmetic circuit to receive the internal value, for performing a third finite field arithmetic operation using part or all of the plurality of syndromes and the internal value to generate the first-order coefficient.
16. The error checking and correcting decoder of claim 15, wherein the first arithmetic circuit comprises:
a first lookup table circuit that receives and uses the first syndrome to lookup a first lookup table to obtain a finite field cubic value of the first syndrome;
a first finite field addition circuit coupled to the first lookup table circuit to receive the finite field cube value and to perform a finite field addition operation using the finite field cube value and a second syndrome of the plurality of syndromes to generate a first finite field addition value;
a second lookup table circuit coupled to the first finite field addition circuit to receive the first finite field addition value and lookup a second lookup table using the first finite field addition value to obtain a finite field negative first power value of the first finite field addition value;
a third lookup table circuit receiving and using the first syndrome to lookup a third lookup table to obtain a limited field quintic value of the first syndrome;
a second finite field addition circuit coupled to the third lookup table circuit to receive the finite field quintic values and perform the finite field addition operation using the finite field quintic values and a third syndrome of the plurality of syndromes to generate a second finite field addition value; and
a finite field multiplication circuit coupled to the second lookup table circuit and the second finite field addition circuit for receiving the finite field negative first square value and the second finite field addition value, respectively, and performing finite field multiplication operation using the finite field negative first square value and the second finite field addition value to generate the internal value.
17. The error checking and correcting decoder of claim 15, wherein the first arithmetic circuit comprises:
a first lookup table circuit receiving and using the first syndrome and the second syndrome to lookup a first lookup table to obtain a first finite field arithmetic value;
a second lookup table circuit receiving and using the first syndrome and the third syndrome to lookup a second lookup table to obtain a second finite field arithmetic value; and
a finite field multiplication circuit coupled to the first lookup table circuit and the second lookup table circuit to receive the first finite field arithmetic value and the second finite field arithmetic value, respectively, and to perform a finite field multiplication operation using the first finite field arithmetic value and the second finite field arithmetic value to generate the internal value.
18. The error checking and correcting decoder of claim 15, wherein the second arithmetic circuit comprises:
a finite field multiplication circuit coupled to the first arithmetic circuit to receive the internal value and to perform a finite field multiplication operation using the internal value and the first syndrome to produce a finite field product value; and
finite field addition circuitry coupled to the finite field multiplication circuitry to receive the finite field product values and to perform finite field addition operations using the finite field product values and a second syndrome of the plurality of syndromes to produce the constant term coefficients.
19. The error checking and correcting decoder of claim 15, wherein the third arithmetic circuit comprises:
a finite field squaring circuit that receives and uses the first syndrome to perform a finite field squaring operation to produce a finite field squared value of the first syndrome; and
a finite field addition circuit coupled to the finite field squaring circuit and the first arithmetic circuit for receiving the finite field squared value and the internal value, respectively, and performing a finite field addition operation using the finite field squared value and the internal value to generate the first-order term coefficient.
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