CN108880238B - JFET type self-excited staggered parallel Sepic converter - Google Patents
JFET type self-excited staggered parallel Sepic converter Download PDFInfo
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- CN108880238B CN108880238B CN201810839004.7A CN201810839004A CN108880238B CN 108880238 B CN108880238 B CN 108880238B CN 201810839004 A CN201810839004 A CN 201810839004A CN 108880238 B CN108880238 B CN 108880238B
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- 239000003990 capacitor Substances 0.000 claims abstract description 110
- 230000000087 stabilizing effect Effects 0.000 claims description 34
- 238000010586 diagram Methods 0.000 description 11
- 238000004088 simulation Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/1557—Single ended primary inductor converters [SEPIC]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The self-excited staggered parallel Sepic converter comprises an inductor L1, an inductor L2, an N-type JFET tube J1 which can be conducted when the gate-source voltage is 0, an N-type JFET tube J2 which can be conducted when the gate-source voltage is 0, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an inductor L3, an inductor L4, a diode D3, a diode D4, a capacitor Co, a driving branch 1 and a driving branch 2, wherein in the driving branch 1, when the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 is conducted, a port a1 of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0 is generated by negative voltage to turn off the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0; in the driving branch 2, when the N-type JFET J1, which is turned on when the gate-source voltage is 0, is turned on, the port a2 thereof generates a negative voltage to turn off the N-type JFET J2, which is turned on when the gate-source voltage is 0. The invention has the characteristics of low input voltage starting, wide input voltage range working and high efficiency.
Description
Technical Field
The invention relates to an interleaved parallel Sepic converter, in particular to an interleaved parallel Sepic converter suitable for low-voltage input, which can be applied to occasions such as LED driving, energy collection, auxiliary power supply and the like.
Background
Compared with the separate excitation type Sepic converter, the self-excitation type staggered parallel Sepic converter has the advantages of small input/output current ripple, easy starting, easy capacity expansion, low cost and the like. Enhancement MOSFETs and BJTs are common semiconductor devices that can be used to construct self-excited interleaved parallel Sepic converters. When applied to low voltage input applications, the enhancement MOSFET is not suitable because of its high gate-source threshold voltage. Although a BJT with a lower base-emitter turn-on voltage is suitable, its drive and turn-on losses are both greater.
Disclosure of Invention
In order to overcome the defect of larger loss when the existing BJT constructs a low-voltage input staggered parallel Sepic converter, the invention provides a JFET type self-excited staggered parallel Sepic converter, and aims to realize low-input voltage starting, wide input voltage range operation and high efficiency at the same time.
The technical scheme adopted for solving the technical problems is as follows:
a self-excited parallel-connection type Sepic converter of JFET type comprises an inductor L1, an inductor L2, an N-type JFET tube J1 which can be conducted when the voltage of a gate source electrode is 0, an N-type JFET tube J2 which can be conducted when the voltage of the gate source electrode is 0, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an inductor L3, an inductor L4, a diode D3, a diode D4, a capacitor Co, a driving branch 1 and a driving branch 2, wherein the driving branch J is provided with a port aj, a port bj, a port cj and a port dj, the value range of J is 1 to 2, the positive end of a direct current power supply Vi is simultaneously connected with one end of the inductor L1 and one end of the inductor L2, the other end of the inductor L1 is simultaneously connected with the drain electrode of the N-type JFET tube J1 which can be conducted when the voltage of the gate source electrode is 0, the port C2 of the driving branch 2 and one end of the capacitor C1, the other end of the capacitor C1 is simultaneously connected with the port D2 of the driving branch 2, the anode of the diode D1 and one end of the inductor L3, the other end of the inductor L3 is connected with the cathode of the diode D3, the cathode of the diode D1 is simultaneously connected with the cathode of the diode D2, one end of the capacitor Co and one end of the load, the other end of the capacitor Co is simultaneously connected with the other end of the load, the anode of the diode D3, the anode of the diode D4, the port b1 of the driving branch 1, the port b2 of the driving branch 2, the source of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0, the source of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and the negative end of the direct current power supply Vi, the other end of the inductor L2 is simultaneously connected with the drain of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0, the port C1 of the driving branch 1 and one end of the capacitor C2, the other end of the capacitor C2 is simultaneously connected with the port D1 of the driving branch 1, the anode of the diode D2 and one end of the inductor L4, the other end of the inductor L4 is connected to the cathode of the diode D4, and the gate of the N-type JFET J1, which is turned on when the gate-source voltage is 0, is connected to the port a1 of the driving branch 1, and the gate of the N-type JFET J2, which is turned on when the gate-source voltage is 0, is connected to the port a2 of the driving branch 2.
Further, in the driving branch 1, when the N-type JFET J2, which is turned on when the gate-source voltage is 0, is turned on, the port a1 thereof generates a negative voltage to turn off the N-type JFET J1, which is turned on when the gate-source voltage is 0; in the driving branch 2, when the N-type JFET J1, which is turned on when the gate-source voltage is 0, is turned on, the port a2 thereof generates a negative voltage to turn off the N-type JFET J2, which is turned on when the gate-source voltage is 0.
The N-type JFET J1 that can be turned on when the gate-source voltage is 0 and the N-type JFET J2 that can be turned on when the gate-source voltage is 0 can be replaced with depletion type MOSFET transistors.
As a preferred scheme of the driving branch j, the driving branch j includes a voltage stabilizing tube Zaj, a resistor Raj and a capacitor Caj, the port aj of the driving branch j is connected with the anode of the voltage stabilizing tube Zaj and one end of the resistor Raj at the same time, the other end of the resistor Raj is connected with one end of the capacitor Caj, the other end of the capacitor Caj is connected with the port cj of the driving branch j, the cathode of the voltage stabilizing tube Zaj is connected with the port bj of the driving branch j, and the value range of j is 1 to 2.
Further, the driving branch j further includes a resistor Rbj and a diode Dbj, one end of the resistor Rbj is connected to the port aj of the driving branch j, the other end of the resistor Rbj is connected to the cathode of the diode Dbj, and the anode of the diode Dbj is connected to one end of the capacitor Caj.
Further, the driving branch j further includes a resistor Rcj and a diode Dcj, an anode of the diode Dcj is connected to the port aj of the driving branch j, a cathode of the diode Dcj is connected to one end of the resistor Rcj, and the other end of the resistor Rcj is connected to one end of the capacitor Caj.
As another preferred scheme of the driving branch j, the driving branch j comprises a voltage stabilizing tube Zdj, a resistor Rdj and a capacitor Cdj, the port aj of the driving branch j is connected with the anode of the voltage stabilizing tube Zdj and one end of the resistor Rdj at the same time, the other end of the resistor Rdj is connected with one end of the capacitor Cdj, the other end of the capacitor Cdj is connected with the port dj of the driving branch j, the cathode of the voltage stabilizing tube Zdj is connected with the port bj of the driving branch j, and the value range of j is 1-2.
Further, the driving branch j further includes a resistor Rej and a diode Dej, one end of the resistor Rej is connected to the port aj of the driving branch j, the other end of the resistor Rej is connected to the cathode of the diode Dej, and the anode of the diode Dej is connected to one end of the capacitor Cdj.
Further, the driving branch j further includes a resistor Rfj and a diode Dfj, an anode of the diode Dfj is connected to the port aj of the driving branch j, a cathode of the diode Dfj is connected to one end of the resistor Rfj, and the other end of the resistor Rfj is connected to one end of the capacitor Cdj.
The technical conception of the invention is as follows: in contrast to enhancement MOSFETs, JFETs can turn on when the gate-source voltage is 0. The voltage-driven JFET has lower drive and turn-on losses than BJTs, and is also easier to integrate. In summary, the JFET has the advantages of both the enhancement type MOSFET and the BJT, and is suitable for constructing a staggered parallel Sepic converter with low voltage input.
The self-excited staggered parallel Sepic converter is constructed by adopting JFET (junction field effect transistor) tubes which can be conducted when the gate-source voltage is 0, and a driving branch which can be matched with the working performance of the JFET tubes which can be conducted when the gate-source voltage is 0 and can generate negative voltage is mainly constructed, wherein the driving branch comprises basic components such as a voltage stabilizing tube, a resistor, a capacitor and the like.
The beneficial effects of the invention are mainly shown in the following steps: the JFET type self-excited staggered parallel Sepic converter has the characteristics of low input voltage starting, wide input voltage range working and high efficiency.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Fig. 2 is a circuit diagram of a first drive leg scheme suitable for use with the present invention.
Fig. 3 is a simulation waveform diagram of embodiment 1.
Fig. 4 is a circuit diagram of a second drive leg scheme suitable for use with the present invention.
Fig. 5 is a circuit diagram of a third drive leg scheme suitable for use with the present invention.
Fig. 6 is a circuit diagram of a fourth drive leg scheme suitable for use with the present invention.
Fig. 7 is a simulation waveform diagram of example 4.
Fig. 8 is a circuit diagram of a fifth drive leg scheme suitable for use with the present invention.
Fig. 9 is a circuit diagram of a sixth drive leg scheme suitable for use with the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Example 1
Referring to fig. 1 and 2, a JFET-type self-excited interleaved Sepic converter includes an inductor L1, an inductor L2, an N-type JFET tube J1 that can be turned on when a gate-source voltage is 0, an N-type JFET tube J2 that can be turned on when a gate-source voltage is 0, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an inductor L3, an inductor L4, a diode D3, a diode D4, a capacitor Co, a driving branch 1, and a driving branch 2, the driving branch J having a port aj, a port bj, a port cj, and a port dj, the value of J ranging from 1 to 2, the positive terminal of a dc power supply Vi being connected to one end of the inductor L1 and one end of the inductor L2 at the same time, the other terminal of the inductor L1 being connected to the drain of the N-type JFET tube J1 that can be turned on when the gate-source voltage is 0, the port C2 of the driving branch 2, and one end of the capacitor C1 at the same time, the other terminal of the capacitor C1 being connected to the port D2 of the driving branch 2, the anode of the driving branch 1, and one end of the inductor L3 at the same time, the other end of the inductor L3 is connected with the cathode of the diode D3, the cathode of the diode D1 is simultaneously connected with the cathode of the diode D2, one end of the capacitor Co and one end of the load, the other end of the capacitor Co is simultaneously connected with the other end of the load, the anode of the diode D3, the anode of the diode D4, the port b1 of the driving branch 1, the port b2 of the driving branch 2, the source of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0, the source of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and the negative end of the direct current power supply Vi, the other end of the inductor L2 is simultaneously connected with the drain of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0, the port C1 of the driving branch 1 and one end of the capacitor C2, the other end of the capacitor C2 is simultaneously connected with the port D1 of the driving branch 1, the anode of the diode D2 and one end of the inductor L4, the other end of the inductor L4 is connected to the cathode of the diode D4, and the gate of the N-type JFET J1, which is turned on when the gate-source voltage is 0, is connected to the port a1 of the driving branch 1, and the gate of the N-type JFET J2, which is turned on when the gate-source voltage is 0, is connected to the port a2 of the driving branch 2.
In the driving branch 1, when the N-type JFET J2, which can be turned on when the gate-source voltage is 0, is turned on, the port a1 thereof generates a negative voltage to turn off the N-type JFET J1, which can be turned on when the gate-source voltage is 0; in the driving branch 2, when the N-type JFET J1, which is turned on when the gate-source voltage is 0, is turned on, the port a2 thereof generates a negative voltage to turn off the N-type JFET J2, which is turned on when the gate-source voltage is 0.
The driving branch j comprises a voltage stabilizing tube Zaj, a resistor Raj and a capacitor Caj, the port aj of the driving branch j is connected with the anode of the voltage stabilizing tube Zaj and one end of the resistor Raj at the same time, the other end of the resistor Raj is connected with one end of the capacitor Caj, the other end of the capacitor Caj is connected with the port cj of the driving branch j, the cathode of the voltage stabilizing tube Zaj is connected with the port bj of the driving branch j, and the value range of j is 1-2.
Example 1 uses the internal inconsistencies to produce the desired oscillations and can be started at low input voltage. When it is in steady state, the operating state of the continuous conduction mode can be divided into the following 2 phases. (1) J1 which can be conducted when the gate-source voltage is 0 is conducted, D1 is turned off, D3 is conducted, L1 and L3 are magnetized, and the inductance current iL1 is increased; j2 which can be conducted when the gate-source voltage is 0 is off, D2 is conducted, D4 is conducted, L2 and L4 are demagnetized, and the inductance current iL2 is reduced; za2 is reversely conducted, ca2 is discharged through Za2 and Ra2, and the gate voltage va2 of J2 which can be conducted when the gate-source voltage is 0 is negative; za1 is forward conducting and Ca1 is charged by Ra1 and Za1, and the gate voltage va1 of J1, which can be conducted when the gate-source voltage is 0, is about zero. (2) J1 which can be conducted when the gate-source voltage is 0 is off, D1 is conducted, D3 is conducted, L1 and L3 are magnetized, and inductance current iL1 is reduced; j2 which can be conducted when the gate-source voltage is 0 is conducted, D2 is turned off, D4 is conducted, L2 and L4 are magnetized, and the inductance current iL2 is increased; za2 is turned on in the forward direction, ca2 is charged through Za2 and Ra2, and the gate voltage va2 of J2, which can be turned on when the gate-source voltage is 0, is about zero; za1 is turned on in reverse, ca1 is discharged through Za1 and Ra1, and the gate voltage va1 of J1, which can be turned on when the gate-source voltage is 0, is negative. The above 2 phases are alternately arranged and repeated.
Fig. 3 is a simulation waveform diagram of example 1. As can be seen from fig. 3, in the operating state of embodiment 1, J1 and J2, which can be turned on when the gate-source voltage is 0, are turned on and off alternately, and the output voltage Vo >0.
Example 2
Referring to fig. 1 and 4, a JFET-type self-excited interleaved Sepic converter includes a driving branch j having a resistor Rbj and a diode Dbj, one end of the resistor Rbj is connected to a port aj of the driving branch j, the other end of the resistor Rbj is connected to a cathode of a diode Dbj, an anode of the diode Dbj is connected to one end of a capacitor Caj, and the value of j ranges from 1 to 2.
The remaining structure of embodiment 2 is the same as that of embodiment 1.
The principle of operation of example 2 is also similar to example 1, except that the charge rate of Caj in example 2 is faster than that of Caj in example 1.
Example 3
Referring to fig. 1 and 5, a JFET-type self-excited interleaved Sepic converter includes a driving branch j including a resistor Rcj and a diode Dcj, an anode of the diode Dcj is connected to a port aj of the driving branch j, a cathode of the diode Dcj is connected to one end of the resistor Rcj, the other end of the resistor Rcj is connected to one end of a capacitor Caj, and the value of j ranges from 1 to 2.
The remaining structure of embodiment 3 is the same as that of embodiment 1.
The principle of operation of example 3 is also similar to that of example 1, except that the discharge rate of Caj in example 3 is faster than that of Caj in example 1.
Example 4
Referring to fig. 1 and 6, a JFET-type self-excited interleaved Sepic converter is disclosed, a driving branch j includes a regulator Zdj, a resistor Rdj and a capacitor Cdj, a port aj of the driving branch j is connected to an anode of the regulator Zdj and one end of the resistor Rdj at the same time, the other end of the resistor Rdj is connected to one end of the capacitor Cdj, the other end of the capacitor Cdj is connected to a port dj of the driving branch j, a cathode of the regulator Zdj is connected to a port bj of the driving branch j, and a value range of j is 1 to 2.
The remaining structure of embodiment 4 is the same as that of embodiment 1, and the working principle is also similar to that of embodiment 1.
Fig. 7 is a simulation waveform diagram of example 4. As can be seen from fig. 7, in the operating state of embodiment 4, J1 and J2, which are turned on when the gate-source voltage is 0, are alternately turned on and off, and the output voltage Vo >0.
Example 5
Referring to fig. 1 and 8, a JFET-type self-excited interleaved Sepic converter includes a driving branch j having a resistor Rej and a diode Dej, one end of the resistor Rej is connected to a port aj of the driving branch j, the other end of the resistor Rej is connected to a cathode of the diode Dej, an anode of the diode Dej is connected to one end of the capacitor Cdj, and the value of j ranges from 1 to 2.
The remaining structure of embodiment 5 is the same as that of embodiment 4.
The principle of operation of example 5 is also similar to example 4, except that the charging rate of Cdj in example 5 is faster than the charging rate of Cdj in example 4.
Example 6
Referring to fig. 1 and 9, a JFET-type self-excited interleaved Sepic converter includes a driving branch j having a resistor Rfj and a diode Dfj, an anode of the diode Dfj is connected to a port aj of the driving branch j, a cathode of the diode Dfj is connected to one end of the resistor Rfj, the other end of the resistor Rfj is connected to one end of the capacitor Cdj, and the value of j ranges from 1 to 2.
The remaining structure of embodiment 6 is the same as that of embodiment 4.
The principle of operation of example 6 is also similar to that of example 4, except that the discharge rate of Cdj in example 6 is faster than that of Cdj in example 4.
The embodiments described in the present specification are merely examples of implementation forms of the inventive concept, and the scope of protection of the present invention should not be construed as being limited to the specific forms set forth in the embodiments, but the scope of protection of the present invention and equivalent technical means that can be conceived by those skilled in the art based on the inventive concept.
Claims (9)
1. The utility model provides a JFET type self-excitation type crisscross parallelly connected Sepic converter which characterized in that: the self-excited staggered parallel Sepic converter comprises an inductor L1, an inductor L2, an N-type JFET tube J1 which can be conducted when the voltage of a gate source electrode is 0, an N-type JFET tube J2 which can be conducted when the voltage of the gate source electrode is 0, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an inductor L3, an inductor L4, a diode D3, a diode D4, a capacitor Co, a driving branch 1 and a driving branch 2, wherein the driving branch 1 is provided with a port a1, a port b1 and a port C1, the driving branch 2 is provided with a port a2, a port b2 and a port C2, the positive end of a direct current power supply Vi is simultaneously connected with one end of the inductor L1 and one end of the inductor L2, the other end of the inductor L1 is simultaneously connected with the drain electrode of the N-type JFET tube J1 which can be conducted when the voltage of the gate source electrode is 0, the port C2 and one end of the capacitor C1, the other end of the capacitor C1 is simultaneously connected with the anode of the diode D1 and one end of the inductor L3, the other end of the inductor L3 is connected with the cathode of the diode D3, the cathode of the diode D1 is simultaneously connected with the cathode of the diode D2, one end of the capacitor Co and one end of the load, the other end of the capacitor Co is simultaneously connected with the other end of the load, the anode of the diode D3, the anode of the diode D4, the port b1 of the driving branch 1, the port b2 of the driving branch 2, the source of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0, the source of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and the negative end of the direct current power supply Vi, the other end of the inductor L2 is simultaneously connected with the drain of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0, the port C1 of the driving branch 1 and one end of the capacitor C2, the other end of the capacitor C2 is simultaneously connected with the anode of the diode D2 and one end of the inductor L4, the other end of the inductor L4 is connected with the cathode of the diode D4, the grid electrode of the N-type JFET tube J1 which can be conducted when the grid source voltage is 0 is connected with the port a1 of the driving branch circuit 1, and the grid electrode of the N-type JFET tube J2 which can be conducted when the grid source voltage is 0 is connected with the port a2 of the driving branch circuit 2;
the driving branch circuit 1 comprises a voltage stabilizing tube Za1, a resistor Ra1 and a capacitor Ca1, wherein the port a1 of the driving branch circuit 1 is connected with the anode of the voltage stabilizing tube Za1 and one end of the resistor Ra1 at the same time, the other end of the resistor Ra1 is connected with one end of the capacitor Ca1, the other end of the capacitor Ca1 is connected with the port c1 of the driving branch circuit 1, and the cathode of the voltage stabilizing tube Za1 is connected with the port b1 of the driving branch circuit 1;
the driving branch circuit 2 comprises a voltage stabilizing tube Za2, a resistor Ra2 and a capacitor Ca2, the port a2 of the driving branch circuit 2 is connected with the anode of the voltage stabilizing tube Za2 and one end of the resistor Ra2 at the same time, the other end of the resistor Ra2 is connected with one end of the capacitor Ca2, the other end of the capacitor Ca2 is connected with the port c2 of the driving branch circuit 2, and the cathode of the voltage stabilizing tube Za2 is connected with the port b2 of the driving branch circuit 2;
at steady state, 2 phases of the operating state of the continuous conduction mode: (1) An N-type JFET tube J1 which can be conducted when the gate-source voltage is 0 is conducted, an N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 is cut off, the gate voltage of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 is negative, and the gate voltage of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0 is about zero; (2) The N-type JFET J1, which is turned on when the gate-source voltage is 0, is turned off, the N-type JFET J2, which is turned on when the gate-source voltage is 0, is turned on, the gate voltage of the N-type JFET J2, which is turned on when the gate-source voltage is 0, is about zero, and the gate voltage of the N-type JFET J1, which is turned on when the gate-source voltage is 0, is negative.
2. The utility model provides a JFET type self-excitation type crisscross parallelly connected Sepic converter which characterized in that: the self-excited staggered parallel Sepic converter comprises an inductor L1, an inductor L2, an N-type JFET tube J1 which can be conducted when the voltage of a gate source electrode is 0, an N-type JFET tube J2 which can be conducted when the voltage of the gate source electrode is 0, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an inductor L3, an inductor L4, a diode D3, a diode D4, a capacitor Co, a driving branch 1 and a driving branch 2, wherein the driving branch 1 is provided with a port a1, a port b1 and a port C1, the driving branch 2 is provided with a port a2, a port b2 and a port D2, the positive end of a direct current power supply Vi is simultaneously connected with one end of the inductor L1 and one end of the inductor L2, the other end of the inductor L1 is simultaneously connected with the drain electrode of the N-type JFET tube J1 which can be conducted when the voltage of the gate source electrode is 0 and one end of the capacitor C1, the other end of the capacitor C1 is simultaneously connected with the port D2 of the driving branch 2, the anode of the diode D1 and one end of the inductor L3, the other end of the inductor L3 is connected with the cathode of the diode D3, the cathode of the diode D1 is simultaneously connected with the cathode of the diode D2, one end of the capacitor Co and one end of the load, the other end of the capacitor Co is simultaneously connected with the other end of the load, the anode of the diode D3, the anode of the diode D4, the port b1 of the driving branch 1, the port b2 of the driving branch 2, the source of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0, the source of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and the negative end of the direct current power supply Vi, the other end of the inductor L2 is simultaneously connected with the drain of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0, the port C1 of the driving branch 1 and one end of the capacitor C2, the other end of the capacitor C2 is simultaneously connected with the anode of the diode D2 and one end of the inductor L4, the other end of the inductor L4 is connected with the cathode of the diode D4, the grid electrode of the N-type JFET tube J1 which can be conducted when the grid source voltage is 0 is connected with the port a1 of the driving branch circuit 1, and the grid electrode of the N-type JFET tube J2 which can be conducted when the grid source voltage is 0 is connected with the port a2 of the driving branch circuit 2;
the driving branch circuit 1 comprises a voltage stabilizing tube Za1, a resistor Ra1 and a capacitor Ca1, wherein the port a1 of the driving branch circuit 1 is connected with the anode of the voltage stabilizing tube Za1 and one end of the resistor Ra1 at the same time, the other end of the resistor Ra1 is connected with one end of the capacitor Ca1, the other end of the capacitor Ca1 is connected with the port c1 of the driving branch circuit 1, and the cathode of the voltage stabilizing tube Za1 is connected with the port b1 of the driving branch circuit 1;
the driving branch circuit 2 comprises a voltage stabilizing tube Zd2, a resistor Rd2 and a capacitor Cd2, the port a2 of the driving branch circuit 2 is connected with the anode of the voltage stabilizing tube Zd2 and one end of the resistor Rd2 at the same time, the other end of the resistor Rd2 is connected with one end of the capacitor Cd2, the other end of the capacitor Cd2 is connected with the port d2 of the driving branch circuit 2, and the cathode of the voltage stabilizing tube Zd2 is connected with the port b2 of the driving branch circuit 2.
3. The utility model provides a JFET type self-excitation type crisscross parallelly connected Sepic converter which characterized in that: the self-excited staggered parallel Sepic converter comprises an inductor L1, an inductor L2, an N-type JFET tube J1 which can be conducted when the voltage of a gate source electrode is 0, an N-type JFET tube J2 which can be conducted when the voltage of the gate source electrode is 0, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an inductor L3, an inductor L4, a diode D3, a diode D4, a capacitor Co, a driving branch 1 and a driving branch 2, wherein the driving branch 1 is provided with a port a1, a port b1 and a port D1, the driving branch 2 is provided with a port a2, a port b2 and a port C2, the positive end of a direct current power supply Vi is simultaneously connected with one end of the inductor L1 and one end of the inductor L2, the other end of the inductor L1 is simultaneously connected with the drain electrode of the N-type JFET tube J1 which can be conducted when the voltage of the gate source electrode is 0, the port C2 and one end of the capacitor C1, the other end of the capacitor C1 is simultaneously connected with the anode of the diode D1 and one end of the inductor L3, the other end of the inductor L3 is connected with the cathode of the diode D3, the cathode of the diode D1 is simultaneously connected with the cathode of the diode D2, one end of the capacitor Co and one end of the load, the other end of the capacitor Co is simultaneously connected with the other end of the load, the anode of the diode D3, the anode of the diode D4, the port b1 of the driving branch 1, the port b2 of the driving branch 2, the source of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0, the source of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and the negative end of the direct current power supply Vi, the other end of the inductor L2 is simultaneously connected with the drain of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and one end of the capacitor C2, the other end of the capacitor C2 is simultaneously connected with the port D1 of the driving branch 1, the anode of the diode D2 and one end of the inductor L4, the other end of the inductor L4 is connected with the cathode of the diode D4, the grid electrode of the N-type JFET tube J1 which can be conducted when the grid source voltage is 0 is connected with the port a1 of the driving branch circuit 1, and the grid electrode of the N-type JFET tube J2 which can be conducted when the grid source voltage is 0 is connected with the port a2 of the driving branch circuit 2;
the driving branch circuit 1 comprises a voltage stabilizing tube Zd1, a resistor Rd1 and a capacitor Cd1, the port a1 of the driving branch circuit 1 is connected with the anode of the voltage stabilizing tube Zd1 and one end of the resistor Rd1 at the same time, the other end of the resistor Rd1 is connected with one end of the capacitor Cd1, the other end of the capacitor Cd1 is connected with the port d1 of the driving branch circuit 1, and the cathode of the voltage stabilizing tube Zd1 is connected with the port b1 of the driving branch circuit 1;
the driving branch circuit 2 comprises a voltage stabilizing tube Za2, a resistor Ra2 and a capacitor Ca2, the port a2 of the driving branch circuit 2 is connected with the anode of the voltage stabilizing tube Za2 and one end of the resistor Ra2 at the same time, the other end of the resistor Ra2 is connected with one end of the capacitor Ca2, the other end of the capacitor Ca2 is connected with the port c2 of the driving branch circuit 2, and the cathode of the voltage stabilizing tube Za2 is connected with the port b2 of the driving branch circuit 2.
4. The utility model provides a JFET type self-excitation type crisscross parallelly connected Sepic converter which characterized in that: the self-excited staggered parallel Sepic converter comprises an inductor L1, an inductor L2, an N-type JFET tube J1 which can be conducted when the voltage of a gate source electrode is 0, an N-type JFET tube J2 which can be conducted when the voltage of the gate source electrode is 0, a capacitor C1, a capacitor C2, a diode D1, a diode D2, an inductor L3, an inductor L4, a diode D3, a diode D4, a capacitor Co, a driving branch 1 and a driving branch 2, wherein the driving branch 1 is provided with a port a1, a port b1 and a port D1, the driving branch 2 is provided with a port a2, a port b2 and a port D2, the positive end of a direct current power supply Vi is simultaneously connected with one end of the inductor L1 and one end of the inductor L2, the other end of the inductor L1 is simultaneously connected with the drain electrode of the N-type JFET tube J1 which can be conducted when the voltage of the gate source electrode is 0 and one end of the capacitor C1, the other end of the capacitor C1 is simultaneously connected with the port D2 of the driving branch 2, the anode of the diode D1 and one end of the inductor L3, the other end of the inductor L3 is connected with the cathode of the diode D3, the cathode of the diode D1 is simultaneously connected with the cathode of the diode D2, one end of the capacitor Co and one end of the load, the other end of the capacitor Co is simultaneously connected with the other end of the load, the anode of the diode D3, the anode of the diode D4, the port b1 of the driving branch 1, the port b2 of the driving branch 2, the source of the N-type JFET tube J1 which can be conducted when the gate-source voltage is 0, the source of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and the negative end of the direct current power supply Vi, the other end of the inductor L2 is simultaneously connected with the drain of the N-type JFET tube J2 which can be conducted when the gate-source voltage is 0 and one end of the capacitor C2, the other end of the capacitor C2 is simultaneously connected with the port D1 of the driving branch 1, the anode of the diode D2 and one end of the inductor L4, the other end of the inductor L4 is connected with the cathode of the diode D4, the grid electrode of the N-type JFET tube J1 which can be conducted when the grid source voltage is 0 is connected with the port a1 of the driving branch circuit 1, and the grid electrode of the N-type JFET tube J2 which can be conducted when the grid source voltage is 0 is connected with the port a2 of the driving branch circuit 2;
the driving branch circuit 1 comprises a voltage stabilizing tube Zd1, a resistor Rd1 and a capacitor Cd1, the port a1 of the driving branch circuit 1 is connected with the anode of the voltage stabilizing tube Zd1 and one end of the resistor Rd1 at the same time, the other end of the resistor Rd1 is connected with one end of the capacitor Cd1, the other end of the capacitor Cd1 is connected with the port d1 of the driving branch circuit 1, and the cathode of the voltage stabilizing tube Zd1 is connected with the port b1 of the driving branch circuit 1;
the driving branch circuit 2 comprises a voltage stabilizing tube Zd2, a resistor Rd2 and a capacitor Cd2, the port a2 of the driving branch circuit 2 is connected with the anode of the voltage stabilizing tube Zd2 and one end of the resistor Rd2 at the same time, the other end of the resistor Rd2 is connected with one end of the capacitor Cd2, the other end of the capacitor Cd2 is connected with the port d2 of the driving branch circuit 2, and the cathode of the voltage stabilizing tube Zd2 is connected with the port b2 of the driving branch circuit 2.
5. The JFET-type self-excited interleaved parallel Sepic converter of claim 1 or 2, wherein: the driving branch circuit 1 further comprises a resistor Rb1 and a diode Db1, one end of the resistor Rb1 is connected with the port a1 of the driving branch circuit 1, the other end of the resistor Rb1 is connected with the cathode of the diode Db1, and the anode of the diode Db1 is connected with one end of the capacitor Ca 1;
alternatively, the driving branch 1 further includes a resistor Rc1 and a diode Dc1, where an anode of the diode Dc1 is connected to the port a1 of the driving branch 1, a cathode of the diode Dc1 is connected to one end of the resistor Rc1, and the other end of the resistor Rc1 is connected to one end of the capacitor Caj.
6. The JFET-type self-excited interleaved parallel Sepic converter of claim 1 or 3, wherein: the driving branch circuit 2 further comprises a resistor Rb2 and a diode Db2, one end of the resistor Rb2 is connected with the port a2 of the driving branch circuit 2, the other end of the resistor Rb2 is connected with the cathode of the diode Db2, and the anode of the diode Db2 is connected with one end of the capacitor Ca 2;
alternatively, the driving branch 2 further includes a resistor Rc2 and a diode Dc2, where an anode of the diode Dc2 is connected to the port a2 of the driving branch 2, a cathode of the diode Dc2 is connected to one end of the resistor Rc2, and the other end of the resistor Rc2 is connected to one end of the capacitor Ca 2.
7. The JFET-type self-excited interleaved parallel Sepic converter of claim 2 or 4, wherein: the driving branch circuit 2 further comprises a resistor Re2 and a diode De2, one end of the resistor Re2 is connected with the port a2 of the driving branch circuit 2, the other end of the resistor Re2 is connected with the cathode of the diode De2, and the anode of the diode De2 is connected with one end of the capacitor Cd 2;
alternatively, the driving branch 2 further includes a resistor Rf2 and a diode Df2, where an anode of the diode Df2 is connected to the port a2 of the driving branch 2, a cathode of the diode Df2 is connected to one end of the resistor Rf2, and the other end of the resistor Rf2 is connected to one end of the capacitor Cd 2.
8. The JFET-type self-excited interleaved parallel Sepic converter of claim 3 or 4, wherein: the driving branch circuit 1 further comprises a resistor Re1 and a diode De1, one end of the resistor Re1 is connected with the port a1 of the driving branch circuit 1, the other end of the resistor Re1 is connected with the cathode of the diode De1, and the anode of the diode De1 is connected with one end of a capacitor Cd 1;
alternatively, the driving branch 1 further includes a resistor Rf1 and a diode Df1, where an anode of the diode Df1 is connected to the port a1 of the driving branch 1, a cathode of the diode Df1 is connected to one end of the resistor Rf1, and the other end of the resistor Rf1 is connected to one end of the capacitor Cd 1.
9. The JFET-type self-excited interleaved parallel Sepic converter of one of claims 1 to 4, characterized by: the N-type JFET J1 that can be turned on when the gate-source voltage is 0 and the N-type JFET J2 that can be turned on when the gate-source voltage is 0 can be replaced with depletion type MOSFET transistors.
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| CN201810839004.7A CN108880238B (en) | 2018-07-27 | 2018-07-27 | JFET type self-excited staggered parallel Sepic converter |
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| CN201810839004.7A CN108880238B (en) | 2018-07-27 | 2018-07-27 | JFET type self-excited staggered parallel Sepic converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101877534A (en) * | 2010-06-28 | 2010-11-03 | 浙江工业大学 | Bipolar transistor self-exciting Sepic converter |
| CN102403895A (en) * | 2011-11-22 | 2012-04-04 | 浙江工业大学 | Self-excitation Sepic converter based on MOSFET |
| CN106063103A (en) * | 2014-02-27 | 2016-10-26 | 丹麦技术大学 | Burst mode control |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050151518A1 (en) * | 2004-01-08 | 2005-07-14 | Schneiker Henry D. | Regulated open-loop constant-power power supply |
| WO2015200730A1 (en) * | 2014-06-25 | 2015-12-30 | Innosys, Inc. | Circadian rhythm alignment lighting |
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|---|---|---|---|---|
| CN101877534A (en) * | 2010-06-28 | 2010-11-03 | 浙江工业大学 | Bipolar transistor self-exciting Sepic converter |
| CN102403895A (en) * | 2011-11-22 | 2012-04-04 | 浙江工业大学 | Self-excitation Sepic converter based on MOSFET |
| CN106063103A (en) * | 2014-02-27 | 2016-10-26 | 丹麦技术大学 | Burst mode control |
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| Characteristics and Application of Normally-Off SiC-JFETs in Converters Without Antiparallel Diode.《2013 IEEE TRANSACTIONS ON POWER ELECTRONICS》.2013,第4851-4856页. * |
| Milovan Kovacevic et al..Very high frequency interleaved self-oscillating resonant SEPIC converter.《2013 15th European Conference on Power Electronics and Applications (EPE)》.2013,正文第1-6页. * |
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