CN108872828B

CN108872828B - Reset management circuit and method for resetting management circuit

Info

Publication number: CN108872828B
Application number: CN201810335558.3A
Authority: CN
Inventors: 亚当·杰里姆·怀特
Original assignee: NXP USA Inc
Current assignee: NXP USA Inc
Priority date: 2017-04-13
Filing date: 2018-04-13
Publication date: 2022-07-08
Anticipated expiration: 2038-04-13
Also published as: EP3388850B1; EP3388850A1; US10050618B1; CN108872828A

Abstract

A signal management circuit includes a first input to receive a first signal. A first logic portion is coupled to the first input and configured to provide a first output signal. The second logic portion is coupled to receive a second signal and configured to provide a second output signal. The second signal is based on the first output signal and the first signal. An output is coupled to provide a third output signal based on the first output signal and the second output signal.

Description

Reset management circuit and method for resetting management circuit

Technical Field

The present disclosure relates generally to integrated circuits, and more specifically to circuits and methods for controlling reset in integrated circuits.

Background

Today, many integrated circuits utilize testing techniques to improve the test coverage of complex digital circuitry. As the complexity of digital designs has increased, the reset architecture has also become very complex. For example, in modern system-on-chip (SoC) devices, a system reset typically resets a large portion of the SoC. The system reset may include multiple reset sources that may be generated by software or hardware. Reset sources such as power-on reset (POR), Low Voltage Detected (LVD) reset, watchdog timeout reset, debug reset, etc., may cause the assertion of a system reset signal. However, in testing complex integrated circuit systems, the reset source may provide significant challenges.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a signal management circuit comprising:

a first input to receive a first signal;

a first logic portion coupled to the first input and configured to provide a first output signal;

a second logic portion coupled to receive a second signal and configured to provide a second output signal, the second signal being based on the first output signal and the first signal; and

an output coupled to provide a third output signal based on the first output signal and the second output signal.

In one or more embodiments, the circuit further comprises:

a second input coupled to the second logic portion to receive an enable signal;

the third output signal transitions to a first state in response to receiving a first edge of a first signal when the enable signal is in the first state, and

delaying transition of the third output signal to the first state in response to receiving the first edge until after receiving the second edge of the first signal while the enable signal is in the second state.

In one or more embodiments, the enable signal is characterized as a test signal corresponding to a test mode.

In one or more embodiments, the first signal corresponds to a reset condition indication signal.

In one or more embodiments, the reset indication signal corresponds to a low voltage detection signal.

In one or more embodiments, the first logic portion includes a first flip-flop and a second flip-flop coupled in series, each coupled to receive the first signal at a reset input.

In one or more embodiments, the second logic portion includes a third flip-flop and a fourth flip-flop coupled in series, each coupled to receive the second signal at a reset input.

In one or more embodiments, the circuit further includes a first logic circuit having a first input coupled to receive the first output signal, a second input coupled to receive the first signal, and an output coupled to provide the second signal.

In one or more embodiments, the circuit further includes a second logic circuit having a first input coupled to receive the first output signal, a second input coupled to receive the second output signal, and an output coupled to the output.

According to a second aspect of the present invention, there is provided a signal management circuit comprising:

a first input to receive a reset condition indication signal;

a second input coupled to receive a test signal; and

an output coupled to provide an output signal;

the output signal transitions to a first state in response to receiving a first edge of the reset condition indication signal when the test signal is in a first state, and

delaying transition of the output signal to a first state in response to receiving a first edge of the reset condition indication signal while the test signal is in a second state until after receiving a second edge of the reset condition indication signal.

In one or more embodiments, the circuit further comprises:

a first logic portion coupled to the first input and configured to provide a first signal; and

a second logic portion coupled to the second input and configured to provide a second signal, the output signal being based on the first signal and the second signal.

In one or more embodiments, the first logic portion includes a first flip-flop and a second flip-flop coupled in series, each coupled to receive the reset condition indication signal at a reset input.

In one or more embodiments, the second logic portion includes a third flip-flop and a fourth flip-flop coupled in series, each coupled to receive a third signal at a reset input, the third signal based on the first signal and the reset condition indication signal.

In one or more embodiments, the circuit further includes a first logic circuit having a first input coupled to receive the first signal, a second input coupled to receive the reset condition indication signal, and an output coupled to provide the third signal.

In one or more embodiments, the circuit further includes a second logic circuit having a first input coupled to receive the first signal, a second input coupled to receive the second signal, and an output coupled to provide the output signal at the output.

In one or more embodiments, the test signal indicates a test mode.

In one or more embodiments, the reset condition indication signal corresponds to a low voltage detection signal.

According to a third aspect of the invention, there is provided a method comprising:

receiving an indication of a reset condition activity;

performing a reset operation in response to receiving the indication of the reset condition activity during a first state of a test signal; and

delaying the reset operation in response to receiving the indication that a reset condition is active during a second state of the test signal until after receiving an indication that the reset condition is no longer active.

In one or more embodiments, the test signal corresponds to a test mode that is inactive during the first state of the test signal and active during the second state of the test signal.

In one or more embodiments, the indication of reset condition activity is based on a low voltage detection signal.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

Fig. 1 illustrates, in simplified block diagram form, an exemplary integrated circuit in accordance with an embodiment of the present disclosure.

Fig. 2 illustrates, in simplified block diagram form, an exemplary reset management circuit in accordance with an embodiment of the present disclosure.

Figure 3 illustrates, in timing diagram form, an exemplary power up signal timing in accordance with an embodiment of the present disclosure.

Fig. 4 illustrates in timing diagram form exemplary blocking and delaying signal timing in accordance with an embodiment of the present disclosure.

Detailed Description

In general, an integrated circuit is provided that includes reset management circuitry to selectively block or delay indication of a reset condition during a test operation. For example, margin test operations typically include systematically reducing the voltage supplied to the digital circuitry under test until a fault is detected. Faults are likely to occur at voltage levels below a predetermined threshold of a voltage monitor designed to protect the operation of such circuitry. Reset conditions initiated by reducing the supplied voltage below a predetermined threshold can be safely blocked during test operations, allowing the test operations to complete without interruption and delaying the reset of the digital circuitry until the test operations are complete.

Fig. 1 illustrates, in simplified block diagram form, an exemplary integrated circuit processing system 100 in accordance with embodiments of the present disclosure. In some embodiments, processing system 100 may be characterized as a system-on-a-chip (SoC). Processing system 100 includes system bus 102, processor 104, memory 106, other peripherals 108, test controller 110, reset controller 112, and analog circuit blocks 114. Processor 104, memory 106, other peripherals 108, test controller 110, and reset controller 112 are each bidirectionally coupled to system bus 102 by way of respective communication buses. In some embodiments, analog circuit blocks 114 may be coupled to system bus 102 by way of a communication bus. In some embodiments, analog circuit block 114 may be formed on a separate die from the die that includes reset circuit block 112. In other embodiments, the processing system 100 may include other blocks, peripherals, and devices, and/or be arranged in other configurations.

System bus 102 may be any type of bus used to communicate any type of information, such as addresses, data, instructions, clocks, resets, and controls. System bus 102 provides a communications backbone for communications between processor 104, memory 106, other peripherals 108, test circuit block 110, and reset circuit block 112.

The processor 104 may be any type of processor including circuitry for processing, computing, etc., such as a Microprocessor (MPU), a Microcontroller (MCU), a Digital Signal Processor (DSP), or other type of processing core. The processing system 100 may include multiple processors, such as processor 104. The processor 104 is configured to execute instructions to carry out one or more specified tasks.

For example, memory 106 may comprise any suitable type of memory array, such as Static Random Access Memory (SRAM). The memory 106 may also be directly coupled or closely coupled to the processor 104. Processing system 100 may include multiple memories, such as memory 106, or a combination of different memories. For example, the processing system 100 may include flash memory in addition to the memory 106.

For example, other peripherals 108 of processing system 100 may include any number of other circuits and functional hardware blocks, such as accelerators, timers, counters, communication tools, interfaces, analog-to-digital converters, digital-to-analog converters, PLLs, and so forth. Other peripheral devices 108 are each bidirectionally coupled to system bus 102 by way of respective communication buses.

Test controller 110 is a circuit block used to control the testing of one or more peripherals, processors, memories, functional blocks, units, circuits, etc. of processing system 100. The test controller 110 may provide test control for determining manufacturing defects, operating margins, and the like. The test controller 110 includes one or more outputs for providing control signals to peripheral devices, functional blocks, units, circuits, and the like. For example, control signal 116 is provided to reset controller 112. The control signal 116 may be characterized as a test signal corresponding to a test mode and used as an enable signal for resetting the controller 112 circuitry.

Reset controller 112 is a circuit block used to control one or more reset functions of processing system 100. Reset controller 112 may include circuitry for reset detection from on-chip and/or off-chip sources and for reset signal distribution to peripherals, functional blocks, units, circuits, etc. of processing system 100. The reset source signal may be routed or communicated by way of the system bus 102 and the communication bus. The reset source signal may be routed or communicated directly to the reset controller 112. For example, a reset source signal labeled 118 from the analog circuit block is provided to the reset controller 112. Reset controller 112 includes a reset management circuit 120, reset management circuit 120 having a first input to receive a reset source signal, e.g., 118, a second input to receive an enable signal, e.g., 116, and an output to provide an output signal. The reset signal may be distributed to peripherals, functional blocks, units, circuits, etc., by way of the system bus 102 and the communication bus, or may be routed directly to such peripherals, functional blocks, units, circuits, etc.

Analog circuit blocks 114 of processing system 100 may include one or more analog circuits to perform any number of functions, such as temperature detection, voltage monitoring, and the like. In some embodiments, analog circuit blocks 114 may include features and functionality to communicate via system bus 102 and a locally coupled communication bus. In some embodiments, analog circuit block 114 may be formed on a separate die from the die that includes reset circuit block 112. In this embodiment, the analog circuit block 114 includes Low Voltage Detection (LVD) circuitry and provides an output signal labeled 118 to the reset controller 112. In some embodiments, the LVD circuitry may be located in other portions of the processing system 100.

Fig. 2 illustrates, in simplified block diagram form, an exemplary reset signal management circuit 120 in accordance with embodiments of the present disclosure. The reset management circuit 120 may be part of the reset controller 112. The reset management circuit 120 includes inputs to receive a clock signal labeled CLK, an input signal labeled IN, an ENABLE signal labeled ENABLE, and an output to provide an output signal labeled OUT. Signals IN and ENABLE are received at input terminals IN and ENABLE, respectively. In this embodiment, during the test mode, signal ENABLE (116) corresponds to a test signal. The signal ENABLE may be provided by a control register output, combinational logic, etc. located in the test controller 110. IN this embodiment, the signal IN (118) corresponds to an indication that a reset condition is active or occurring (e.g., a low voltage detect signal). The signal IN may be provided by analog circuitry outputs such as a sensor output, a voltage detector or monitor output, a temperature detector or monitor output, and so forth located IN the analog block 114. In some embodiments, the indication may correspond to other reset conditions generated by other circuitry in the processing system 100.

In this embodiment, the reset management circuit 120 includes flip-flops 202 to 208, a NAND gate 210, and an OR gate 212. Flip-flops 202-208 may be characterized as master-slave flip-flops, D-type flip-flops (DFFs), or the like. In some embodiments, the reset management circuit 120 may include other logic and circuitry configurations.

Each flip-flop 202 to 208 comprises a data input labeled D, a clock input indicated by a V-shaped symbol, a reset input labeled R and an output labeled Q. Flip-flops 202-208 may include other inputs and outputs. In this embodiment, the reset input R of each flip-flop includes a "bubble" shown at each flip-flop symbol to indicate that the reset input R is an active low input. For example, a logic low signal provided at such a reset input R will reset the flip-flop, causing a logic low signal to be provided at the corresponding output Q.

The first logic portion of the reset management circuit 120 includes flip-

flops

202 and 204. Input D of flip-flop 202 is coupled to receive a logic high signal by way of a power supply terminal labeled VDD. In this embodiment, the VDD voltage may be characterized as a nominal operating voltage for digital logic and applied at the VDD supply terminal. As used herein, the term VDD may be used interchangeably with the VDD voltage and the voltage applied at the VDD supply terminal. The reset input R of flip-flop 202 is coupled to receive signal IN and the output Q of flip-flop 202 is coupled to the input D of flip-flop 204. The reset input R of the flip-flop 204 is coupled to receive the signal IN, and the output Q of the flip-flop 204 is coupled to a first input of an or gate 212 at a node labeled a.

The second logic portion of the reset management circuit 120 includes flip-

flops

206 and 208. Input D of flip-flop 206 is coupled to receive signal ENABLE. The reset input R of flip-flop 206 is coupled to the output of nand gate 210 at a node labeled INDB, and the output Q of flip-flop 206 is coupled to the input D of flip-flop 208. The reset input R of flip-flop 204 is coupled to the output of nand gate 210 at a node labeled INDB, and the output Q of flip-flop 208 is coupled to a second input of or gate 212 at a node labeled B.

A first input of nand gate 210 is coupled to the output Q of flip-flop 204 at node a. A "bubble" is shown at the first input of the nand gate 210 sign to indicate that the first input is an inverting or negative input. A second input of nand gate 210 is coupled to receive signal IN. Nand gate 210 is coupled to receive signal IN and the signal at node a and provides the signal at node INDB at an output. An OR gate 212 is coupled to receive the signals at nodes A and B and provides a signal OUT at an output.

Fig. 3 illustrates, in timing diagram form, an exemplary power up signal timing sequence 300 in accordance with an embodiment of the present disclosure. The power-up signal timing sequence 300 includes various signal waveforms versus time for power-up operations consistent with the exemplary reset management circuit 120 shown in fig. 2. IN this embodiment, signal IN (e.g., 118 of FIG. 1) is provided by the low voltage detection circuitry of analog circuit block 114 and signal ENABLE (e.g., 116 of FIG. 1) is provided by test controller 110. Signals IN and ENABLE are received at inputs IN and ENABLE, respectively. The signal IN may be characterized as a Low Voltage Indication (LVI) signal, a Low Voltage Detection (LVD) signal, or a power saving signal, where a logic low indicates that a voltage below a predetermined threshold is detected and a logic high indicates that a voltage at or above the predetermined threshold is detected. An LVI, LVD or power save signal may be desirable to control an orderly reset or wake-up of digital circuitry. By way of example, the signal timing for the power-up operation is as follows.

At time t0, during a power-up operation, the voltage applied at the VDD power supply terminal ramps up and is below a predetermined threshold. Because the voltage has not reached the predetermined threshold, the output signal of the low voltage detection circuitry provides a low voltage indication as a logic low signal received at the input IN. The signal CLK is at logic low and the signals at node A, B, INDB and OUT are unknown. For the power-up operation depicted in FIG. 3, the signal ENABLE (not shown) is at logic low.

At time t1, the logic low signal received at input IN results IN a logic low signal being provided at output Q of flip-

flops

202 and 204. Also, the signal at node a transitions to logic low. A logic low signal received at input IN causes the output of nand gate 210 to transition to a logic high signal at node INDB.

At time t2, signal IN transitions to a logic high signal indicating that the voltage applied at the VDD power supply terminal meets or exceeds a predetermined threshold. The output signal of the low voltage detection circuitry (signal IN) transitions to a logic high signal received at input IN. Because the signal IN transitions to a logic high and the signal at node a is a logic low, the output of nand gate 210 transitions to a logic low signal at node INDB. The logic low signal at node INDB results in a logic low signal being provided at the output Q of flip-

flops

206 and 208. The logic low signals at nodes a and B, in turn, cause the output of or gate 212 to provide a logic low signal at output OUT. The resulting logic low signal at the output OUT may provide an indication, alone or in combination with other signals, that the reset condition is active or occurring.

At time t3, the clock signal CLK starts to rotate. In this embodiment, the logic high signal output from the low voltage detection circuitry indicates that the voltage applied at the VDD power supply terminal is at or above a predetermined threshold and is sufficient to provide normal operation of the digital circuitry. Thus, the clock circuitry may begin propagating the clock signal CLK.

At time t4, with a logic high signal at input IN, signal CLK clocks the flip-flop causing a logic high at input D of flip-flop 202 to propagate through output Q of flip-flop 204. The resulting logic high signal at node A causes the output signal of OR gate 212 to transition to a logic high at output OUT and the output signal of NAND gate 210 to transition to a logic high signal at node INDB. The logic high signal at the output OUT may provide an indication, alone or in combination with other signals, that the reset condition is no longer active or occurring.

Fig. 4 illustrates in timing diagram form an exemplary blocking and delaying signal timing 400 according to an embodiment of the present disclosure. The blocking and delaying signal timing 400 includes various signal waveforms versus time for signal blocking/delaying operations consistent with the exemplary reset management circuit 120 shown in fig. 2. IN this embodiment, the signal IN at the input IN (e.g., 118 of fig. 1) is provided by the low voltage detection circuitry of the analog circuit block 114, and the signal ENABLE at the ENABLE input (e.g., 116 of fig. 1) is provided by the test controller 110. The signal IN may be characterized as a Low Voltage Indication (LVI) signal, a Low Voltage Detection (LVD) signal, or a power saving signal, where a logic low indicates that a voltage below a predetermined threshold is detected and a logic high indicates that a voltage above the predetermined threshold is detected. An LVI, LVD or power save signal may be desirable to control an orderly reset or wake-up of digital circuitry. The signal ENABLE may be characterized as a test signal or a blocking signal that may be enabled during a test mode. Signal ENABLE may also provide an indication of test mode activity. By way of example, the signal timing for the reset signal blocking/delaying operation is as follows.

At time t0, a logic high signal is received at input IN indicating that the voltage applied at the VDD power supply terminal is equal to or greater than a predetermined threshold and sufficient to allow normal operation of the digital circuitry. During normal operation, the clock signal CLK rotates, the signal at node a is at logic high, the resulting signal at node INDB is at logic high, and the output signal OUT is at logic high. The signal ENABLE is at logic low and the signal at node B is at logic low. The logic high signal at the output OUT may provide an indication, alone or in combination with other signals, that the reset condition is not active or occurring.

At time t1, signal ENABLE transitions to logic high. In this embodiment, for example, signal ENABLE may be a test signal from test controller 110 that is provided to block another signal, such as a low voltage detection signal, during a test mode.

At time t2, a logic high signal ENABLE received at input D of flip-flop 206 propagates through output Q of flip-flop 208 as a logic high signal at node B. The output signal OUT remains at logic high.

At time t3, signal IN transitions to logic low. Also, flip-

flops

202 and 204 are reset and a logic low signal is generated at node A. The logic low signal (signal IN) provided by the low voltage detection circuitry of analog circuit block 114 indicates that the voltage applied at the VDD power supply terminal is below a predetermined threshold.

For example, during the test mode, the voltage applied at the VDD power supply terminal may be systematically lowered so that a minimum operating voltage for the digital circuitry under test may be determined. Because the signal ENABLE is asserted as a logic high, the low voltage detection signal at the input IN may be blocked from reaching the output OUT of the reset management circuit 120 so that the minimum operating voltage of the digital logic may be determined at a VDD voltage that is below a predetermined threshold.

IN some embodiments, the signal provided at input IN may be characterized as a high voltage detection signal provided by the voltage detection circuitry of analog circuit block 114. For example, a high voltage detection signal at input IN may be blocked from reaching the output OUT of the reset management circuit 120, such that the maximum operating voltage of the digital logic may be determined at a VDD voltage above another predetermined threshold. IN some embodiments, the signal provided at input IN may be any other suitable signal desirable for blocking when the ENABLE signal is asserted to a logic high.

At time t4, signal IN transitions to a logic high indicating that the voltage applied at the VDD power supply terminal meets or exceeds a predetermined threshold. The output signal of the low voltage detection circuitry transitions to a logic high signal received at input IN. Because the signal IN transitions to logic high and the signal at node a is at logic low, the output of nand gate 210 transitions to a logic low signal at node INDB. The logic low signal at node INDB coupled to the reset inputs R of flip-

flops

206 and 208 results in a logic low signal provided at the outputs Q of flip-

flops

206 and 208. The logic low signals at nodes a and B, in turn, cause the output of or gate 212 to provide a logic low signal at output OUT.

IN this embodiment, the logic low portion of the signal IN corresponds to a low voltage detection characterized as a reset condition. The logic low portion of the signal is blocked from time t3 to time t 4. After the signal IN transitions to a logic high, the resulting logic low at the output OUT may provide an indication, alone or IN combination with other signals, that a reset condition has occurred. By blocking the reset condition from time t3 to time t4, testing may continue uninterrupted. Once the voltage recovers to a level at or above the predetermined threshold, the blocked reset condition may be allowed to propagate as a delayed signal at the output OUT.

For example, the period from time t3 to time t4 may be used to determine a minimum operating voltage for the digital circuitry. During this period, the voltage applied at the VDD power supply terminal may be reduced so that a minimum operating voltage for the digital circuitry may be determined. Once the minimum operating voltage has been determined, the voltage applied at the VDD power supply terminal may be increased until a predetermined threshold is met or exceeded, causing the output signal of the low voltage detection circuitry to transition to a logic high signal indicating that the voltage applied at the VDD power supply terminal is sufficient to provide normal operation of the digital circuitry. Because digital circuitry may have become nonfunctional during the minimum operating voltage determination, a reset of the digital circuitry is desirable once the voltage applied at the VDD power supply terminal is sufficient for normal operation. Accordingly, a reset pulse signal may be generated at the output OUT to restore the functional operation.

At time t5, the signal at node A transitions to logic high. After the signal IN transitions to logic high, two clock cycles of the clock signal CLK are used to propagate a logic high at the input D of the flip-flop 202 through the output Q of the flip-flop 204 at node a. Also, the signals at the outputs of OR gate 212 and NAND gate 210 transition to logic high at output OUT and node INDB, respectively. The logic high signal at the output OUT may provide an indication, alone or in combination with other signals, that the reset condition is no longer active or occurring.

In general, there is provided a signal management circuit comprising: a first input to receive a first signal; a first logic portion coupled to the first input and configured to provide a first output signal; a second logic portion coupled to receive a second signal and configured to provide a second output signal, the second signal being based on the first output signal and the first signal; and an output coupled to provide a third output signal based on the first output signal and the second output signal. The circuit may further comprise: a second input coupled to the second logic portion to receive an enable signal; the third output signal transitions to the first state in response to receiving a first edge of a first signal when the enable signal is in the first state, and delays transitioning the third output signal to the first state in response to receiving the first edge until after receiving a second edge of the first signal when the enable signal is in the second state. The enable signal may be characterized as a test signal corresponding to a test mode. The first signal may correspond to a reset condition indication signal. The reset indication signal may correspond to a low voltage detection signal. The first logic portion may include a first flip-flop and a second flip-flop coupled in series, each coupled to receive the first signal at a reset input. The second logic portion may include a third flip-flop and a fourth flip-flop coupled in series, each coupled to receive the second signal at a reset input. The circuit may further include a first logic circuit having a first input coupled to receive the first output signal, a second input coupled to receive the first signal, and an output coupled to provide the second signal. The circuit may further include a second logic circuit having a first input coupled to receive the first output signal, a second input coupled to receive the second output signal, and an output coupled to the output.

In another embodiment, a signal management circuit is provided, comprising: a first input to receive a reset condition indication signal; a second input coupled to receive a test signal; and an output coupled to provide an output signal; the output signal transitions to a first state in response to receiving a first edge of the reset condition indication signal when the test signal is in a first state, and delays transitioning the output signal to the first state in response to receiving the first edge of the reset condition indication signal until after receiving a second edge of the reset condition indication signal when the test signal is in a second state. The circuit may further comprise: a first logic portion coupled to the first input and configured to provide a first signal; and a second logic coupled to the second input and configured to provide a second signal, the output signal being based on the first signal and the second signal. The first logic portion may include a first flip-flop and a second flip-flop coupled in series, each coupled to receive the reset condition indication signal at a reset input. The second logic portion may include a third flip-flop and a fourth flip-flop coupled in series, each coupled to receive a third signal at a reset input, the third signal being based on the first signal and the reset condition indication signal. The circuit may further include a first logic circuit having a first input coupled to receive the first signal, a second input coupled to receive the reset condition indication signal, and an output coupled to provide the third signal. The circuit may further include a second logic circuit having a first input coupled to receive the first signal, a second input coupled to receive the second signal, and an output coupled to provide the output signal at the output. The test signal may indicate a test mode. The reset condition indication signal may correspond to a low voltage detection signal.

In yet another embodiment, a method is provided, comprising: receiving an indication of a reset condition activity; performing a reset operation in response to receiving the indication of the reset condition activity during a first state of a test signal; and delaying the reset operation in response to receiving the indication that a reset condition is active during a second state of the test signal until after receiving an indication that the reset condition is no longer active. The test signal may correspond to a test mode that is inactive during the first state of the test signal and active during the second state of the test signal. The indication of reset condition activity may be based on a low voltage detection signal.

At this point it should be appreciated that an integrated circuit has been provided that includes reset management circuitry to selectively block or delay the indication of a reset condition during a test operation. For example, margin test operations typically include systematically reducing the voltage supplied to the digital circuitry under test until a fault is detected. Faults are likely to occur at voltage levels below a predetermined threshold of a voltage monitor designed to protect the operation of such circuitry. Reset conditions initiated by reducing the supplied voltage below a predetermined threshold can be safely blocked during test operations, allowing the test operations to complete without interruption and delaying the reset of the digital circuitry until the test operations are complete.

As used herein, the term "bus" is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status. Conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, multiple conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.

Each signal described herein may be designed as positive or negative logic, where negative logic may be indicated by a bar above the signal name, an asterisk (—) after the name, or the letter "B" at the end of the signal name. In the case of a negative logic signal, the signal is active low, where the logically true state corresponds to a logic level 0. In the case of a positive logic signal, the signal is active high, where the logically true state corresponds to a logic level 1. It should be noted that any of the signals described herein may be designed as negative or positive logic signals. Thus, in alternative embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Although the invention has been described with respect to specific conductivity types or polarity of potentials, it will be appreciated by those skilled in the art that conductivity types or polarities of potentials may be reversed.

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an". The same holds true for the use of definite articles.

Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A signal reset management circuit, comprising:

a first input to receive a first signal;

a second logic portion coupled to receive a second signal and configured to provide a second output signal, the second signal being based on the first output signal and the first signal;

an output coupled to provide a third output signal based on the first and second output signals; and

a second input coupled to the second logic portion to receive an enable signal;

2. The circuit of claim 1, wherein the enable signal is characterized as a test signal corresponding to a test mode.

3. The circuit of claim 1, wherein the first signal corresponds to a reset condition indication signal.

4. The circuit of claim 3, wherein the reset condition indication signal corresponds to a low voltage detection signal.

5. The circuit of claim 1, wherein the first logic portion comprises a first flip-flop and a second flip-flop coupled in series, the first flip-flop and the second flip-flop each coupled to receive the first signal at a reset input.

6. The circuit of claim 5, wherein the second logic portion comprises a third flip-flop and a fourth flip-flop coupled in series, the third flip-flop and the fourth flip-flop each coupled to receive the second signal at a reset input.

7. The circuit of claim 1, further comprising a first logic circuit having a first input coupled to receive the first output signal, a second input coupled to receive the first signal, and an output coupled to provide the second signal.

8. A signal reset management circuit, comprising:

a first input to receive a reset condition indication signal;

a second input coupled to receive a test signal; and

an output coupled to provide an output signal;

9. A method for resetting a managing circuit according to any of claims 1 to 8, comprising:

receiving an indication of a reset condition activity;