CN108847265B - Sensitive amplifier circuit - Google Patents
Sensitive amplifier circuit Download PDFInfo
- Publication number
- CN108847265B CN108847265B CN201810471387.7A CN201810471387A CN108847265B CN 108847265 B CN108847265 B CN 108847265B CN 201810471387 A CN201810471387 A CN 201810471387A CN 108847265 B CN108847265 B CN 108847265B
- Authority
- CN
- China
- Prior art keywords
- nmos transistor
- pmos transistor
- transistor
- electrode
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
The invention discloses a sensitive amplifier circuit, wherein the source electrode of a sixth PMOS transistor is connected with a power supply voltage end vpwr, the drain electrode and the grid electrode of the sixth PMOS transistor are connected with the grid electrode of a sixth NMOS transistor, the drain electrode of the sixth NMOS transistor is connected with the output end of a first phase inverter, the source electrode of the sixth NMOS transistor is connected with the drain electrode of a seventh NMOS transistor, the grid electrode of the seventh NMOS transistor inputs a read time control signal saen1, and the source electrode of the seventh NMOS transistor is grounded. The invention can have better consistency when reading VTP and VTE.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a sensitive amplifier circuit with SO NO (Silicon-O xid e-Nitride-Oxide-Silicon flash memory) read margin consistency.
Background
On a pure 5V process platform, the power supply voltage range of an EEPROM (Electrically Erasable Programmable read only memory) is as follows: 2.0V-5.5V.
The sense amplifier used by SONOS is now shown in fig. 1, and operates as follows:
when the selected SONOS unit is read:
the bl terminal is charged first. The potential of the drain terminal of the SONOS unit is controlled by the inverter inv1, and the potential of the node cl terminal is clamped near the turning point of the inverter inv 1. During precharging, the PMOS transistors P3, P4 are turned off.
After the precharge is completed, the PMOS transistor P3 is turned on. If the cell after SONOS erasure is read, the potential of the dl terminal will drop rapidly, the PMOS transistor P4 is turned on, so that the potential of the drain terminal of the PMOS transistor P4 is pulled up to the power voltage terminal vpwr, and the output terminal Dout is 0; if the cell after SONOS writing is read, the potential at the dl end cannot be pulled down, so that the PMOS transistor P4 cannot be turned on, the drain end of the PMOS transistor P4 continues to be 0 potential, and the output end Dout output is kept to be 1.
The mirror current of the PMOS transistor P1 in the sense amplifier is only required to ensure that the potential at the dl terminal is not dropped when reading the cell after SONOS writing, but is pulled down by the cell after SONOS erasing. The mirror current of the NMOS transistor N1 also only needs a small current, and when reading 1, the PMOS transistor P4 is turned off, and the drain of the PMOS transistor P4 can be pulled down to 0.
In a pure 5V process, the voltage of a power supply voltage end vpwr of the sensitive amplifier is as follows: 2.0V-5.5V. The voltage range is wide, and when the column is precharged during reading, the stable voltage point at cl can float greatly, which affects the consistency of the reading margin of the SONOS unit under different voltages. Namely, the cell written by the low-voltage read SONOS has better read margin, and the cell erased by the high-voltage read SONOS has better read margin.
Disclosure of Invention
The present invention is to provide a sense amplifier circuit, which has better consistency when reading VTP (read margin after the SONSO cell writes 1) and VTE (read margin after the SONSO cell erases).
To solve the above technical problem, the sense amplifier circuit of the present invention includes: first to fifth PMOS transistors; the source electrodes of the second PMOS transistor and the fourth PMOS transistor are connected with a power supply voltage end vpwr, a gate electrode of the third PMOS transistor is input with a pre-charged inverse signal preb, a gate electrode of the second PMOS transistor is input with a P-type mirror current gate electrode voltage signal pbias, and a gate electrode of the fourth PMOS transistor is input with an output signal sensb of the first NAND gate; the drain electrode of the second PMOS transistor is connected with the source electrode of the first PMOS transistor, the grid electrode of the first PMOS transistor inputs an inverted signal saen1b of a read time control signal saen1, the drain electrode of the fourth PMOS transistor is connected with the source electrode of the fifth PMOS transistor, the drain electrode of the third PMOS transistor is connected with the drain electrode of the first PMOS transistor, the grid electrode of the fifth PMOS transistor and the drain electrode of the first NMOS transistor, a connected node is recorded as dl, the source electrode of the first NMOS transistor is connected with the input end of the first inverter and one end of a column selection circuit CMUX, a connected node is recorded as cl, and the output end of the first inverter is connected with the grid electrode of the first NMOS transistor; the fourth NMOS transistor is used as a flash memory SONOS, the other end of the column selection circuit CMUX is connected with the drain electrode of the fourth NMOS transistor, the connected node is marked as bl, the grid electrode of the fourth NMOS transistor is input with a SONOS unit grid gate potential control signal wls, the fifth NMOS transistor is used as a SONOS unit selection tube, the source electrode of the fourth NMOS transistor is connected with the drain electrode of the fifth NMOS transistor, the grid electrode of the fifth NMOS transistor is input with a word line selection signal wl, and the source electrode of the fifth NMOS transistor is grounded;
the drain of the fifth PMOS transistor is connected with the drain of the second NMOS transistor, the drain of the third NMOS transistor and the input end of the second inverter, the gate of the second NMOS transistor is inputted with an N-type mirror current gate terminal voltage signal nbias, the gate of the third NMOS transistor is inputted with a reverse signal saen1b of a read time control signal saen1, and the source of the second NMOS transistor and the source of the third NMOS transistor are grounded; the output end of the second inverter is used as the output end Dout of the circuit;
the input end of the first nand gate inputs the pre-charged inverse signal preb, the other input end inputs the read time control signal saen1, and the output signal of the output end is marked as senseb; it is characterized by also comprising:
the source of the sixth PMOS transistor is connected to the power supply voltage terminal vpwr, the drain and the gate thereof are connected to the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the output terminal of the first inverter, the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor inputs the read time control signal saen1, and the source of the seventh NMOS transistor is grounded.
By adopting the sense amplifier circuit, the voltage of the node cl end is more convergent, and the VTP and VTE read have better consistency within the full voltage range of the power supply voltage vpwr. The read interference can be improved, the reliability of the EEPROM is also benefited, and the product yield is promoted.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic diagram of a prior art sense amplifier circuit;
FIG. 2 is a schematic diagram of an embodiment of an improved sense amplifier circuit.
Detailed Description
Referring to fig. 2, in order to achieve better uniformity of the read margin within the overall voltage range of the power voltage vpwr, a more stable voltage range is required at the node cl. As can be seen from a comparison between fig. 1 and fig. 2, the improved sense amplifier circuit in the following embodiment adjusts the control of the output terminal of the first inverter inv1 as follows. Three transistors, i.e., a PMOS transistor PM1, and NMOS transistors NM1, NM2, are added. When not reading, the NMOS transistor NM2 is turned off, and the PMOS transistor in the first inverter inv1 is prevented from being turned on to ground via the NMOS transistors NM1 and NM 2.
The gate terminal neta of the NMOS transistor NM1 is controlled by the PMOS transistor PM1, and has a voltage of the power supply voltage vpwr minus the PMOS transistor threshold voltage vth (PM 1). When the power supply voltage vpwr becomes larger, the voltage of neta also becomes larger, and the pull-down capability of the NMOS transistor NM1 increases accordingly, and the increase of the terminal voltage of the node cl with the increase of the power supply voltage vpwr can be suppressed.
The PMOS transistor PM1 can compensate for the effect of the process corner of the PMOS transistor in the portion of the first inverter inv 1. When the process angle of the PMOS transistor in the first inverter inv1 is faster, the pull-up capability of the PMOS transistor in the first inverter inv1 is stronger, but the voltage of neta is higher under the condition of faster process angle, and the pull-down capability of the NMOS transistor NM1 is also enhanced.
In the improved sense amplifier circuit, the voltage of the node cl end is more convergent in the full voltage range of the power supply voltage vpwr, and the VTP reading and VTE reading have better consistency.
With reference to fig. 2, the improved sense amplifier circuit has the following circuit structure in the following embodiments:
the sources of the PMOS transistors P1 to P3 are connected to the power voltage terminal vpwr, the gate of the PMOS transistor P2 inputs the pre-charged inverse signal preb, the gate of the PMOS transistor P1 inputs the P-type mirror current gate terminal voltage signal pbias, and the gate of the PMOS transistor P3 inputs the output signal senseb of the first nand gate.
The drain of the PMOS transistor P1 is connected to the source of the PMOS transistor P0, and the gate of the PMOS transistor P0 inputs the inverted signal saen1b of the read time control signal saen 1. The drain of the PMOS transistor P3 is connected to the source of the PMOS transistor P4.
The drain of the PMOS transistor P2 is connected to the drain of the PMOS transistor P0, the gate of the PMOS transistor P4, and the drain of the NMOS transistor N0, and the node at which these are connected is denoted as dl. The source of the NMOS transistor N0 is connected to the input terminal of the first inverter inv1 and one terminal of the column selection circuit CMUX, the node at which it is connected is denoted by cl (for example, CMUX is 1 from 8, cl is 1), and the output terminal of the first inverter inv1 is connected to the gate of the NMOS transistor N0. The other end of the column selection circuit CMUX is connected to the drain of SONOS (which can be understood as an N-type MOS transistor), and its connected node is denoted as bl (for example, CMUX is 8-to-1, 8 of CMUX is respectively connected to 8 columns bl, and the SONOS cell is connected to bl). The gate of the SONOS inputs a SONOS cell gate potential control signal wls, the source of the SONOS is connected to the drain of a SONOS cell select transistor (NMOS transistor) fnpass, the gate of the SONOS cell select transistor fnpass inputs a word line control signal wl, and the source of the SONOS cell select transistor fnpass is grounded.
The drain of the PMOS transistor P4 is connected to the drains of the NMOS transistors N1 and N2 and the input terminal of the second inverter inv2, the gate of the NMOS transistor N1 inputs the voltage signal nbias of the gate terminal of the N-type mirror current, the gate of the NMOS transistor N2 inputs the inverted signal saen1b of the read time control signal saen1, and the sources of the NMOS transistors N1 and N2 are grounded; the output of the second inverter inv2 serves as the output Dout of the circuit.
The first nand gate has an input terminal receiving the pre-charged inverted signal preb, another input terminal receiving the read time control signal saen1, and an output terminal outputting the signal senseb.
The source of the PMOS transistor PM1 is connected to the power supply voltage terminal vpwr, the drain and gate thereof are connected to the gate of the NMOS transistor NM1, the drain of the NMOS transistor NM1 is connected to the output terminal of the first inverter inv1, and the source of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM 2. The gate of the NMOS transistor NM2 inputs the read time control signal saen1, and the source thereof is grounded.
The present invention has been described in detail with reference to the specific embodiments, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (4)
1. A sense amplifier circuit, comprising: first to fifth PMOS transistors; the source electrodes of the second PMOS transistor and the fourth PMOS transistor are connected with a power supply voltage end vpwr, a gate electrode of the third PMOS transistor is input with a pre-charged inverse signal preb, a gate electrode of the second PMOS transistor is input with a P-type mirror current gate electrode voltage signal pbias, and a gate electrode of the fourth PMOS transistor is input with an output signal sensb of the first NAND gate; the drain electrode of the second PMOS transistor is connected with the source electrode of the first PMOS transistor, the grid electrode of the first PMOS transistor inputs an inverted signal saen1b of a read time control signal saen1, the drain electrode of the fourth PMOS transistor is connected with the source electrode of the fifth PMOS transistor, the drain electrode of the third PMOS transistor is connected with the drain electrode of the first PMOS transistor, the grid electrode of the fifth PMOS transistor and the drain electrode of the first NMOS transistor, a connected node is recorded as dl, the source electrode of the first NMOS transistor is connected with the input end of the first inverter and one end of a column selection circuit CMUX, a connected node is recorded as cl, and the output end of the first inverter is connected with the grid electrode of the first NMOS transistor; the fourth NMOS transistor is used as a flash memory SONOS, the other end of the column selection circuit CMUX is connected with the drain electrode of the fourth NMOS transistor, the connected node is marked as bl, the grid electrode of the fourth NMOS transistor is input with a SONOS unit grid gate potential control signal wls, the fifth NMOS transistor is used as a SONOS unit selection tube, the source electrode of the fourth NMOS transistor is connected with the drain electrode of the fifth NMOS transistor, the grid electrode of the fifth NMOS transistor is input with a word line selection signal wl, and the source electrode of the fifth NMOS transistor is grounded;
the drain of the fifth PMOS transistor is connected with the drain of the second NMOS transistor, the drain of the third NMOS transistor and the input end of the second inverter, the gate of the second NMOS transistor is inputted with an N-type mirror current gate terminal voltage signal nbias, the gate of the third NMOS transistor is inputted with a reverse signal saen1b of a read time control signal saen1, and the source of the second NMOS transistor and the source of the third NMOS transistor are grounded; the output end of the second inverter is used as the output end Dout of the circuit;
the input end of the first nand gate inputs the pre-charged inverse signal preb, the other input end inputs the read time control signal saen1, and the output signal of the output end is marked as senseb; it is characterized by also comprising:
the source of the sixth PMOS transistor is connected to the power supply voltage terminal vpwr, the drain and the gate thereof are connected to the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the output terminal of the first inverter, the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor inputs the read time control signal saen1, and the source of the seventh NMOS transistor is grounded.
2. The circuit of claim 1, wherein: and when the reading is not performed, the seventh NMOS transistor is closed.
3. The circuit of claim 1, wherein: the grid end of the sixth NMOS transistor is controlled by the sixth PMOS transistor, and the grid voltage of the sixth NMOS transistor is the power voltage vpwr minus the threshold voltage vth of the sixth PMOS transistor; when the power supply voltage vpwr becomes larger, the gate voltage of the sixth NMOS transistor also becomes larger, and the pull-down capability of the sixth NMOS transistor increases accordingly, so that the increase of the terminal voltage of the node cl with the increase of the power supply voltage vpwr can be suppressed.
4. The circuit of claim 1, wherein: the sixth PMOS transistor can compensate for the effect of the PMOS transistor process corner in part of the first inverter inv 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810471387.7A CN108847265B (en) | 2018-05-17 | 2018-05-17 | Sensitive amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810471387.7A CN108847265B (en) | 2018-05-17 | 2018-05-17 | Sensitive amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108847265A CN108847265A (en) | 2018-11-20 |
| CN108847265B true CN108847265B (en) | 2021-08-24 |
Family
ID=64213264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810471387.7A Active CN108847265B (en) | 2018-05-17 | 2018-05-17 | Sensitive amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108847265B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111969993B (en) * | 2020-07-31 | 2022-10-18 | 安徽大学 | Circuit structure based on CCSA and Sigmoid activated function multiplexing |
| CN112509617A (en) * | 2020-10-30 | 2021-03-16 | 普冉半导体(上海)股份有限公司 | Sensitive amplifier circuit |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266265A (en) * | 1999-02-12 | 2000-09-13 | 日本电气株式会社 | Latching type read amplifier circuit |
| US7821859B1 (en) * | 2006-10-24 | 2010-10-26 | Cypress Semiconductor Corporation | Adaptive current sense amplifier with direct array access capability |
| CN102290086A (en) * | 2011-04-22 | 2011-12-21 | 上海宏力半导体制造有限公司 | Memory and sensitive amplifier |
| JP5290243B2 (en) * | 2010-06-17 | 2013-09-18 | 凸版印刷株式会社 | Sense amplifier circuit |
| CN104575602A (en) * | 2010-04-16 | 2015-04-29 | 斯班逊有限公司 | Semiconductor memory |
| CN104979012A (en) * | 2015-08-07 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Memory circuit |
| US9318189B2 (en) * | 2012-11-21 | 2016-04-19 | Kabushiki Kaisha Toshiba | Sense amplifier circuit |
| CN105895139A (en) * | 2016-03-30 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | Sense amplifier |
| US9607693B2 (en) * | 2015-03-09 | 2017-03-28 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
-
2018
- 2018-05-17 CN CN201810471387.7A patent/CN108847265B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1266265A (en) * | 1999-02-12 | 2000-09-13 | 日本电气株式会社 | Latching type read amplifier circuit |
| US7821859B1 (en) * | 2006-10-24 | 2010-10-26 | Cypress Semiconductor Corporation | Adaptive current sense amplifier with direct array access capability |
| CN104575602A (en) * | 2010-04-16 | 2015-04-29 | 斯班逊有限公司 | Semiconductor memory |
| JP5290243B2 (en) * | 2010-06-17 | 2013-09-18 | 凸版印刷株式会社 | Sense amplifier circuit |
| CN102290086A (en) * | 2011-04-22 | 2011-12-21 | 上海宏力半导体制造有限公司 | Memory and sensitive amplifier |
| US9318189B2 (en) * | 2012-11-21 | 2016-04-19 | Kabushiki Kaisha Toshiba | Sense amplifier circuit |
| US9607693B2 (en) * | 2015-03-09 | 2017-03-28 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
| CN104979012A (en) * | 2015-08-07 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Memory circuit |
| CN105895139A (en) * | 2016-03-30 | 2016-08-24 | 上海华虹宏力半导体制造有限公司 | Sense amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108847265A (en) | 2018-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2015037088A1 (en) | Semiconductor storage device and memory system | |
| JPH0668690A (en) | Internal voltage generating circuit and non-volatile semiconductor memory in semiconductor device | |
| US6344764B2 (en) | Semiconductor integrated circuit device | |
| JP4083147B2 (en) | Semiconductor memory device | |
| JP2019522862A (en) | Asymmetric sense amplifier and related method for flash memory devices | |
| US8681567B2 (en) | Voltage regulator for biasing a NAND memory device | |
| US8588021B2 (en) | Sense amplifier apparatus and methods | |
| KR100781980B1 (en) | Decoder of nonvolatile memory device and decoding method by the same | |
| JP3532721B2 (en) | Constant voltage generator | |
| CN108847265B (en) | Sensitive amplifier circuit | |
| TWI691971B (en) | Method and apparatus for configuring array columns and rows for accessing flash memory cells | |
| US7813198B2 (en) | System and method for reading memory | |
| JP2021034066A (en) | Sense amplifier circuit and semiconductor memory device | |
| KR102113961B1 (en) | Improved sense amplifier with bit line pre-charge circuit for reading flash memory cells in array | |
| JP6752126B2 (en) | Sense amplifier circuit | |
| US5058062A (en) | Nonvolatile semiconductor memory circuit including a reliable sense amplifier | |
| CN110660416B (en) | Storage device, write driver thereof and operation method thereof | |
| US6292406B1 (en) | Method and low-power circuits used to generate accurate boosted wordline voltage for flash memory core cells in read mode | |
| US6956781B2 (en) | Amplifier and semiconductor storage device using the same | |
| JPH033317B2 (en) | ||
| JP3583052B2 (en) | Semiconductor storage device | |
| JPWO2007125590A1 (en) | Semiconductor device and control method thereof | |
| JP2891552B2 (en) | Nonvolatile semiconductor memory device | |
| CN116364132A (en) | Sense amplifier circuit | |
| JPH06309886A (en) | Semiconductor nonvolatile storage device and its using method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |