CN108831891A - Make the method and three-dimensional storage of the wordline bonding pad of three-dimensional storage - Google Patents
Make the method and three-dimensional storage of the wordline bonding pad of three-dimensional storage Download PDFInfo
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- CN108831891A CN108831891A CN201810652369.9A CN201810652369A CN108831891A CN 108831891 A CN108831891 A CN 108831891A CN 201810652369 A CN201810652369 A CN 201810652369A CN 108831891 A CN108831891 A CN 108831891A
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000003860 storage Methods 0.000 title claims abstract description 57
- 239000010410 layer Substances 0.000 claims abstract description 304
- 239000000463 material Substances 0.000 claims abstract description 107
- 239000004065 semiconductor Substances 0.000 claims abstract description 68
- 239000011241 protective layer Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 6
- 230000005516 deep trap Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000009966 trimming Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims 1
- 230000002035 prolonged effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 19
- 230000007547 defect Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910000765 intermetallic Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to the methods and three-dimensional storage of a kind of wordline bonding pad for forming three-dimensional storage.This approach includes the following steps：Semiconductor structure is provided, semiconductor structure has substrate, covers the stack layer of substrate and cover the hard mask layer of stack layer, and stack layer includes the multiple first material layers and multiple second material layers being alternately stacked；The hard mask layer is patterned to form multiple openings, multiple opening exposures stack layer；Multiple contact holes are formed in stack layer by multiple openings, each contact hole of multiple contact holes arrives separately at the first material layer of respective predetermined depth；Insulating layer is formed in each contact hole side wall of multiple contact holes；Protective layer is filled in the insulating layer of multiple contact holes；The first material layer in stack layer is replaced with into conductive layer；And contact portion is formed in each contact hole of multiple contact holes.The problems such as present invention can overcome the etching defect of wordline bonding pad and contact portion to be aligned.
Description
Technical field
The invention mainly relates to semiconductor making method more particularly to a kind of wordline bonding pads for making three-dimensional storage
Method and three-dimensional storage.
Background technique
In order to overcome the limitation of two dimensional memory, industry is had been developed that with the memory of three-dimensional (3D) structure, is passed through
Memory cell is three-dimensionally disposed in substrate to improve integration density.
In such as three-dimensional storage of 3D nand flash memory, storage array may include the core area (core) and ladder
The area (stair step, SS).Stepped region is used to draw contact portion for the control gate in each layer of storage array, connects as wordline
Area.Wordline of these control gates as storage array executes the operation such as programming, erasable, reading.
In the manufacturing process of 3D nand flash memory, etching forms contact hole in the hierarchic structures at different levels of stepped region, then
Contact portion is filled, to draw the electric signal of control gate.In the actual production process, contact hole falls in hierarchic structure not just
It is easy to accomplish.Etching incomplete (Underetch) or etching break-through (Punch Through) are the defects generally occurred.
On the other hand, in the forming process of stepped region, the consistency of the characteristic size of each hierarchic structure, Yi Jijie are kept
The alignment of contact portion and hierarchic structure is also very crucial.It is also the defect generally occurred that contact portion, which deviates corresponding hierarchic structure,.
Summary of the invention
The present invention provides the method and three-dimensional storage of a kind of wordline bonding pad in production three-dimensional storage, can overcome
The problems such as etching defect and contact portion alignment of wordline bonding pad.
The present invention is to solve above-mentioned technical problem and the technical solution adopted is that a kind of wordline for forming three-dimensional storage connects
The method for meeting area, includes the following steps：Semiconductor structure is provided, the semiconductor structure has substrate, covers the substrate
Stack layer and the hard mask layer for covering the stack layer, the stack layer include the multiple first material layers being alternately stacked and multiple
Second material layer；The hard mask layer is patterned to form multiple openings, the multiple opening exposure stack layer；Pass through institute
It states multiple openings and forms multiple contact holes in the stack layer, each contact hole of the multiple contact hole arrives separately at respectively
The first material layer of predetermined depth；Insulating layer is formed in each contact hole side wall of the multiple contact hole；It is connect the multiple
Protective layer is filled in the insulating layer of contact hole；The multiple first material layer in the stack layer is replaced with into conductive layer；
And contact portion is formed in each contact hole of the multiple contact hole.
In one embodiment of this invention, the material of the hard mask layer is polysilicon.
In one embodiment of this invention, with the deep trap of the first doping type in the substrate.
In one embodiment of this invention, after each contact hole side wall of the multiple contact hole forms insulating layer, also
Including removing the part first material layer of each contact hole bottom of the multiple contact hole, and horizontal size is formed greater than described
The recess of the horizontal size of each contact hole；While filling protective layer in the insulating layer of the multiple contact hole, described
Protective layer is filled in recess；And when forming contact portion in each contact hole of the multiple contact hole, together the multiple
Barb is formed in the recess of each contact hole bottom of contact hole.
In one embodiment of this invention, the side of multiple contact holes is formed in the stack layer by the multiple opening
Method includes sequentially forming the multiple contact hole, wherein forming the method packet of wherein one first contact hole of the multiple contact hole
It includes：Form the first photoresist pattern on the semiconductor structure, the in the multiple opening of the first photoresist pattern exposure
One opening；The first contact hole is formed in the stack layer by first opening, it is pre- that first contact hole reaches first
The first material layer of depthkeeping degree.
In one embodiment of this invention, the step of multiple contact holes is formed in the stack layer by the multiple opening
Rapid includes being formed simultaneously the multiple contact hole, if the quantity of the multiple contact hole is N, is formed in N number of contact hole
The step of i-th of contact hole includes：I-th of photoresist pattern is formed on the semiconductor structure, and i-th of photoresist pattern is sudden and violent
Reveal the 1st to i-th opening in the multiple opening；The i-th contact hole is formed in the stack layer by i-th opening,
I-th contact hole is the 1st depth；And the 1st to (i-1)-th contact hole is added respectively by described 1st to the (i-1)-th opening
Depth is the i-th depth to the 2nd depth；Wherein i=1,2,3 ..., N.
In one embodiment of this invention, i-th of photoresist pattern is to be trimmed by (i-1)-th photoresist pattern by photoresist
Mode formed.
In one embodiment of this invention, when patterning the hard mask layer, the upper surface of the stack layer is smooth
's.
In one embodiment of this invention, the multiple first material layer in the stack layer is first replaced with into conduction
Layer, then the contact portion is formed in each contact hole of the multiple contact hole.
In one embodiment of this invention, the multiple first material layer in the stack layer is replaced with into conductive layer
Step includes：By running through the slit of the stack layer from upper surface, the multiple first material in the stack layer is removed
After layer, the conductive material is filled to the stack layer to form the conductive layer.
In one embodiment of this invention, the step of contact portion is formed in each contact hole of the multiple contact hole is wrapped
It includes：Protective layer in each contact hole of the multiple contact hole is replaced with into contact portion.
In one embodiment of this invention, contact portion is first formed in each contact hole of the multiple contact hole, then will
The multiple first material layer in the stack layer replaces with conductive layer.
In one embodiment of this invention, it is formed before contact portion in each contact hole of the multiple contact hole, first
Protective layer is formed in each contact hole of the multiple contact hole, the protective layer covers the bottom of the contact hole, described
Contact site is in the protective layer.
The present invention also proposes a kind of three-dimensional storage, including semiconductor substrate, stack layer, multiple contact portions and one or
Multiple grid separate slots.Stack layer is located on the substrate and including spaced wordline.Each of the multiple contact portion
Contact portion is upward through the stack layer and the respectively wordline with respective predetermined depth in the side perpendicular to the semiconductor substrate
Contact, and the side wall of each contact portion and be electrically isolated between each perforative wordline of contact portion.It is one or more of
Grid separate slot extends vertically through the stack layer.
In one embodiment of this invention, the upper surface of the stack layer is smooth.
In one embodiment of this invention, each wordline continuously extends along word-line direction.
In one embodiment of this invention, with the deep trap of the first doping type in the substrate.
In one embodiment of this invention, the position that respective contact hole is corresponded in each wordline has barb,
The barb is integrally formed with the contact portion in corresponding contact hole.
The present invention due to using the technology described above, does not re-form hierarchic structure, thus there is no hierarchic structure with contact
The problem of portion is aligned avoids contact portion and deviates defect caused by corresponding hierarchic structure.Further, the process of contact hole is formed
The problem of depth of contact hole being easy to control by the material layer in selective etch stack layer, avoiding etching break-through.
In addition, the wordline of three-dimensional storage of the invention and preparation method thereof connects since the distance between contact portion can be closer
Connect area the size of word-line direction can be smaller.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, wherein：
Fig. 1 is the diagrammatic cross-section of three-dimensional storage.
Fig. 2 is the method flow diagram of the wordline bonding pad of the formation three-dimensional storage of first embodiment of the invention.
Fig. 3 A-3H is the exemplary mistake of the method for the wordline bonding pad of the formation three-dimensional storage of first embodiment of the invention
Diagrammatic cross-section in journey.
Fig. 4 A-4D is the section signal in the example process of the method for the multiple contact holes of formation of one embodiment of the invention
Figure.
Fig. 5 A-5F is that the section in the example process of the method for the multiple contact holes of formation of another embodiment of the present invention shows
It is intended to.
Fig. 6 A-6F is showing for the method for the wordline bonding pad of the formation three-dimensional storage for the first embodiment that the present invention optimizes
Diagrammatic cross-section during example property.
Fig. 7 is the method flow diagram of the wordline bonding pad of the formation three-dimensional storage of second embodiment of the invention.
Fig. 8 A-8E is the exemplary mistake of the method for the wordline bonding pad of the formation three-dimensional storage of second embodiment of the invention
Diagrammatic cross-section in journey.
Etching break-through occurs when being the stepped region formation contact hole as the three-dimensional storage compared by Fig. 9 and contact portion is not right
Quasi- diagrammatic cross-section.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, the sectional view of announcer structure can disobey general proportion work office
Portion's amplification, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in actual fabrication
In should include length, width and depth three-dimensional space.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, if overturning attached drawing in device, be described as be in other elements or feature " below " or " under " or
The direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " lower section "
" following " can include upper and lower both direction.Device may also have other directions (being rotated by 90 ° or in other directions),
Therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer in two layers of " it
Between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
As shown in Figure 1, in the three-dimensional storage 10 of such as floating gate type 3D nand flash memory, including storage array 100 and week
Border area 200.Storage array 100 may include area core (core) 110 and the area 120 ladder (Stair Step, SS).Stepped region 120
For drawing contact portion 102 for the control gate 101 in each layer of storage array 100.These control gates 101 are used as storage array 100
Wordline, execute programming, it is erasable, read etc. operation.
When etching the contact hole for drawing contact portion 102, it is desirable to which contact hole just rests on the table of control gate 101
Face does not have to across control gate 101 at least.By taking Fig. 9 as an example, it is desirable to be etched as bottom ladder 121 good and make contact portion
102a is normally contacted, and etching break-through occurs like that rather than high-rise ladder 123 (or 122), cause contact portion 102c (or
It 102b) passes through the control gate 101b for being intended to stop and reaches control gate 101a.In addition, being also not intended to occur as ladder 122
The case where contact portion 102b is with control gate misalignment.
The method of the wordline bonding pad of some embodiments of the present invention description production three-dimensional storage, can overcome wordline to connect
The problems such as etching defect and contact portion for meeting area are aligned.
Fig. 2 is the flow chart of the wordline bonding pad of the formation three-dimensional storage of first embodiment of the invention.Fig. 3 A-3F is this
The example process schematic diagram of the method in the wordline bonding pad for forming three-dimensional storage of invention first embodiment.Below with reference to
The method of the formation wordline bonding pad of description the present embodiment shown in Fig. 2-3H.
In step 202, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for structure of the follow-up process to ultimately form three-dimensional storage.
Semiconductor structure may include array area (array), and array area may include core space (core) and wordline bonding pad.Core space is packet
The region of storage unit is included, wordline bonding pad is the region for including wordline connection circuit.In terms of vertical direction, array area can have
The stack layer of substrate and covering substrate.It is formed with channel hole array on the stack layer of core space or is not yet formed with ditch
Road hole array.It should be pointed out that in the present embodiment, conventional ladder knot is not necessarily forming on the stack layer of wordline bonding pad
Structure.Each layer in stack layer can continuously extend substantially along word-line direction (horizontal direction in Fig. 1), without by ladder
Structure is interrupted.Upper surface due to not having hierarchic structure, entire stack layer is smooth.Stack layer may include being alternately stacked
Multiple first material layers and multiple second material layers.Hard mask layer can be covered on stack layer, be used for subsequent technique.
In the sectional view of the semiconductor structure exemplified by Fig. 3 A, semiconductor structure 300a may include substrate 310, stack layer
320 and hard mask layer 330.Substrate 310 is typically siliceous substrate, such as Si, SOI (silicon-on-insulator), SiGe, Si:C
Deng, although this and it is non-limiting.Stack layer 320 is first material layer 321 and the alternately stacked lamination of second material layer 322.For example,
First material layer 321 and second material layer 322 are the combination of silicon nitride and silica, silica and (undoped) polysilicon or non-
Combination, silicon oxide or silicon nitride and combination of amorphous carbon of crystal silicon etc..By taking the combination of silicon nitride and silica as an example, it can adopt
It is successively alternately heavy on substrate 310 with chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods
Product silicon nitride (for example, first material layer 321) and silica (for example, second material layer 322), form the stack layer 320.At this
In embodiment, 320 surface of stack layer is second material layer 322, such as silica.
Hard mask layer 330 is covered on stack layer 320, other areas of stack layer 320 can be protected when etching contact hole
Domain.The material of hard mask layer 330 is, for example, polysilicon, aluminium oxide (Al2O3) or metal.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.Such as it can be wrapped in substrate 310
The deep trap of the first doping type is included, the first doping type is, for example, N-type.In addition, the material for each layer illustrated is only example
Property, for example, first material layer 321 and second material layer 322 can also select charge trap-type (charge trap flash,
CTF) available other materials in three dimensional NAND memory.
In step 204, patterning hard mask layer is to form multiple openings, multiple opening exposure stack layers.
In this step, to form scheduled pattern, this pattern includes a part of alternative removal hard mask layer
The opening of multiple exposed stack layers.These openings are for removing a part of stack layer in the subsequent process to form contact hole.
The method of patterning hard mask layer may include but be not limited to lithography and etching.
In the sectional view of semiconductor structure 300b exemplified by Fig. 3 B, hard mask pattern 330a is obtained, there are 3 and open
Mouth 331,332 and 333.It is appreciated that the quantity of opening is related with the quantity of control gate in finally formed three-dimensional storage,
And it is not limited to the quantity enumerated herein.There is interval, the position that the position of opening and contact portion are set between each opening 331-333
It is equipped with pass.
In step 206, multiple contact holes, each contact hole of multiple contact holes are formed in stack layer by multiple openings
Arrive separately at the first material layer of respective predetermined depth.
In this step, from the material of each opening removal stack layer, to form each contact hole.Each contact hole
With respective predetermined depth, respective first material layer is arrived separately at.Typically, each contact hole reaches different first
Material layer, to allow subsequent each contact portion and different first material layers in electrical contact.
Each contact hole can be formed by selective etch.
In the sectional view of semiconductor structure 300c exemplified by Fig. 3 C, the shape separately down at each opening 331-333
At contact hole 341,342 and 343.Contact hole 341,342 and 343 has respective predetermined depth d1, d2 and d3, and arrives respectively
Up to different first material layer 321a, 321b and 321c.Selective etch first material layer and the second material respectively can be passed through
Layer at each opening 331-333 forms contact hole.Specifically, first selecting to first material layer etching rate height and to the second material
The low mode of bed of material etching rate etches first material layer, and reselection is high to second material layer etching rate and etches to first material layer
The low mode of rate etches second material layer.
In step 208, insulating layer is formed in each contact hole side wall of multiple contact holes, the insulating layer in each contact hole
The first material layer of predetermined depth in each contact hole of exposure.
In this step, insulating layer is formed in the side wall of each contact hole, and does not form insulating layer in the bottom of contact hole,
To the first material layer of predetermined depth in exposure contact hole.
In the sectional view of semiconductor structure 300d exemplified by Fig. 3 D, respectively in the side wall shape of each contact hole 341-343
At insulating layer 351,352 and 353, and insulating layer is not formed in the bottom of each contact hole 341-343, to expose contact hole respectively
First material layer 321a, 321b and 321c of predetermined depth in 341-343.
Here, the material of insulating layer 351-353 can be selected from a variety of materials, such as silica, silicon nitride, silicon oxynitride, carbon
SiClx and aluminium oxide etc..The mode for forming insulating layer 351-353 may include deposition, such as atomic layer deposition.
In step 210, protective layer is filled in each contact hole of multiple contact holes.
In this step, protective layer can be filled in the contact hole, and protective layer can be in subsequent removal first material layer
Hole is avoided contact in step to be corroded.
In the sectional view of semiconductor structure 300e exemplified by Fig. 3 E, protective layer is respectively formed in multiple contact holes
361,362 and 363.The material of protective layer 361-363 is, for example, aluminium oxide.
In step 212, multiple first material layers in stack layer are replaced with into conductive layer.
In this step, multiple first material layers in stack layer are removed, fill conduction material in the position of first material layer
Material, to form conductive layer.
In the sectional view of semiconductor structure 300f exemplified by Fig. 3 F, the first material layer in stack layer 320 is eliminated
321, to form gap S between second material layer 322.In this step, hard mask pattern 330a can be removed together.
The mode for removing first material layer is, for example, wet etching.360 (the example of slit from upper surface through stack layer 320 can be passed through
Such as, grid separate slot (Gate Line Slit, GLS)) carry out wet etching.
In the sectional view of semiconductor structure 300g exemplified by Fig. 3 G, conductive material is filled in stack layer 320, it is conductive
Material can enter stack layer 320 gap S in be filled with conductive layer 323.
In step 214, the protective layer in each contact hole of multiple contact holes is replaced with into contact portion.
In this step, the protective layer in each contact hole in stack layer is removed, fills conduction material in the position of protective layer
Material, to form contact portion.
In the sectional view of semiconductor structure 300h exemplified by Fig. 3 H, respectively in each contact hole formed contact portion 371,
372 and 373.It is appreciated that can have gap in each contact portion 371,372 and 373, as long as not influencing the electric conductivity of contact portion
Energy.
The material of contact portion is, for example, metal, such as tungsten (W) or metallic compound, such as titanium nitride (TiN).
In this step, by filling contact portion 371-373, conductive path is provided for each conductive layer 323.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.
Above-described embodiment is formed by semiconductor structure, and using subsequent conventional steps, three-dimensional storage can be obtained.
Semiconductor structure 300h, which is formed by, with reference to the present embodiment herein describes three-dimensional storage according to an embodiment of the invention.This reality
The type for applying the three-dimensional storage of example can be charge trap-type three dimensional NAND memory.Three-dimensional storage may include core space and word
Line bonding pad, wordline bonding pad include substrate 310 and the stack layer 320 on substrate, and stack layer 320 may include interval setting
Wordline (i.e. conductive layer) 323.Wordline 323 can be separated by dielectric layer 322.There are multiple contact portions in stack layer 320, such as contact
Portion 371,372 and 373.Each contact portion of multiple contact portions extends upward through stack layer 320 in the side perpendicular to substrate 310 respectively
To which the wordline with respective predetermined depth, such as wordline 323a, 323b and 323c contact.Each perforative depth of contact portion is different
, each contact portion can run through the one or more wordline and/or dielectric layer on corresponding wordline.As contact portion 371 passes through
Wear 2 wordline and 2 dielectric layers on wordline 323a, 1 wordline and 2 Jie of the contact portion 372 on wordline 323b
Matter layer.1 dielectric layer of the contact portion 373 on wordline 323c.Due to each contact portion run through be not intended to it is in electrical contact
Wordline, thus the side wall of each contact portion and by between the perforative wordline of the contact portion have insulating layer.Such as contact portion 371 with
There is insulating layer 351 between two layers of word lines 323b and 323c on wordline 323a.One layer on contact portion 372 and wordline 323b
There is insulating layer 352 between wordline 323c, to form electric isolution.For the needs for facilitating production, in the entire side of each contact portion
Wall and by between the perforative wordline of the contact portion, dielectric layer all have insulating layer, as shown in 351,352 and 353 in figure.
In the present embodiment, three-dimensional storage can be smooth in the upper surface of the stack layer 320 of wordline bonding pad, and
Hierarchic structure is formed unlike conventional word line bonding pad.In stack layer 320, each wordline 323 and each dielectric layer 322 are in word
Line bonding pad continuously extends along word-line direction (horizontal direction in figure).It is appreciated that might have in stack layer 320
Round or bar shaped structure, but wordline 323 and dielectric layer 322 still generally continuously extend.
In one embodiment, there can be array common source (Array Common Source, ACS) in stack layer 320,
Array common source can be formed in grid separate slot 360 as illustrated in Figure 3 F.There is insulation between array common source and grid separate slot 360
Layer, i.e., array common source is located in insulating layer.
In three-dimensional storage of the present embodiment and preparation method thereof, hierarchic structure is not re-formed, therefore ladder is not present
The problem of structure is aligned with contact portion avoids contact portion and deviates defect caused by corresponding hierarchic structure.On the other hand, it is formed
The process of contact hole can be easy to control the depth of contact hole, avoid quarter by the material layer in selective etch stack layer
The logical problem of eating thrown.In addition, since the distance between contact portion can be closer, the three-dimensional storage and its system of the present embodiment
Make the wordline bonding pad of method the size of word-line direction can be smaller.
Etching break-through occurs when being the stepped region formation contact hole as the three-dimensional storage compared by Fig. 9 and contact portion is not right
Quasi- diagrammatic cross-section.As shown in figure 9, there is etching break-through in high-rise ladder 123 (or 122), cause contact portion 102c (or
It 102b) passes through the control gate 101b for being intended to stop and reaches control gate 101a.There is contact portion 102b and control gate in ladder 122
The case where misalignment.The case where reviewing Fig. 3 F of the application, etching break-through and contact portion misalignment be all not in.
Some further details are set forth below, with help skilled addressee readily understands that and implement the present invention, so
And it is appreciated that even if following details, those skilled in the art not will also appreciate that and implement the present invention.
For summary, in step 206 shown in Fig. 2, the side of multiple contact holes is formed in stack layer by multiple openings
Method may include sequentially forming multiple contact holes.The method for forming a wherein contact hole (referred to here as the first contact hole) may include
The first photoresist pattern is formed on semiconductor structure, the first opening in the multiple openings of the first photoresist pattern exposure then passes through
First opening forms the first contact hole in stack layer, and the first contact hole reaches the first material layer of the first predetermined depth.
Fig. 4 A-4D is the section signal in the example process of the method for the multiple contact holes of formation of one embodiment of the invention
Figure.The step of multiple contact holes are formed in the present invention, such as step 206 shown in Fig. 2 can be with reference to the method realities of Fig. 4 A-4D
It applies.First as shown in Figure 4 A, semiconductor structure 400a may include substrate 410, stack layer 420 and hard mask layer 430.Hard mask layer
The first opening 431, second opening 432 and third opening 433 can be formed on 430.Firstly, forming on semiconductor structure 400a
The first opening 431 in the one multiple openings of photoresist pattern 450a, the first photoresist pattern 450a exposure.Then such as the semiconductor of Fig. 4 B
Shown in structure 400b, the first contact hole 441 is formed in stack layer 420 by the first opening 431, the first contact hole 441 reaches
The first material layer 421a of first predetermined depth.Then as shown in Figure 4 C, the second photoresist figure is formed on semiconductor structure 400c
The second opening 432 in the multiple openings of case 450b, the second photoresist pattern 450b exposure.Then it is being stacked by the second opening 432
The second contact hole 442 is formed in layer 420, the second contact hole 442 reaches the second material layer 421b of the second predetermined depth.It repeats same
Sample process forms third photoresist pattern 450c, third photoresist pattern 450c exposure as shown in Figure 4 D on semiconductor structure 400d
Third opening 433 in multiple openings.Then third contact hole 443 is formed in stack layer 420 by third opening 433, the
The second material layer 421c of three contact holes 443 arrival third predetermined depth.
Alternatively, not being to sequentially form each contact hole, and be simultaneously formed each contact hole.Specifically, it is assumed that
The quantity of multiple contact holes is N, and the step of i-th of contact hole formed in N number of contact hole includes：It is formed on semiconductor structure
I-th of photoresist pattern, i-th of photoresist pattern expose the 1st to i-th opening in multiple openings；By the i-th opening in stack layer
The i-th contact hole of middle formation, the i-th contact hole are the 1st depth；And by the 1st, the 2nd ..., to (i-1)-th opening respectively will
1st, the 2nd ..., to (i-1)-th contact hole respectively deepen for the i-th depth, the (i-1)-th depth ..., the 2nd depth；Wherein i
=1,2,3 ..., N.
Fig. 5 A-5F is that the section in the example process of the method for the multiple contact holes of formation of another embodiment of the present invention shows
It is intended to.The step of multiple contact holes are formed in the present invention, such as step 206 shown in Fig. 2 can be with reference to the method realities of Fig. 5 A-5F
It applies.First as shown in Figure 5A, semiconductor structure 500a may include substrate 510, stack layer 520 and hard mask layer 530.Hard mask layer
The first opening 531, second opening 532 and third opening 533 can be formed on 530, i.e. the quantity of N is 3.Firstly, in semiconductor junction
A photoresist pattern 550a of the 1st (i=1), the 1st (i=in the 1st multiple openings of photoresist pattern 550a exposure are formed on structure 500a
1) a opening 531.Then it as shown in the semiconductor structure 500b of Fig. 5 B, is formed in stack layer 520 by the 1st opening 531
1st (i=1) contact hole 541, at this time the 1st contact hole 541 be the 1st depth d4, the 1st depth d4 be the 1st contact hole 541 rather than most
Whole predetermined depth.Then as shown in Figure 5 C, a photoresist pattern 550b (example of the 2nd (i=2) is formed on semiconductor structure 500c
Such as, by modifying photoresist pattern 550a), the 2nd photoresist pattern 550b exposes the 1st to 2 (i=2) a opening in multiple openings
531 and 532.Then as shown in the semiconductor structure 500d of Fig. 5 D, the 2nd is formed in stack layer 520 by the 2nd opening 532
(i=2) contact hole 542, the 2nd contact hole 542 is the 1st depth d4 at this time, and the 1st depth d4 is the initial depth of the 2nd contact hole 542
And non-final predetermined depth.And at this time the 1st contact hole 541 is deepened to be the 2nd depth d5 by the 1st opening 531.So
Afterwards as shown in fig. 5e, a photoresist pattern 550c of the 3rd (i=3) is formed on semiconductor structure 500e (for example, by further repairing
Whole photoresist pattern 550b), the 3rd photoresist pattern 550c exposes 531,532 and of a opening of the 1st to 3 (i=3) in multiple openings
533.Then as shown in the semiconductor structure 500f of Fig. 5 F, the 3rd (i=3) is formed in stack layer 520 by the 3rd opening 533
Contact hole 543, at this time the 3rd contact hole 543 be the 1st depth d4, the 1st depth d4 be the initial depth of the 3rd contact hole 543 rather than most
Whole predetermined depth.And pass through a opening 531 and 532 of the 1st to 2 (i-1=2) at this time for the 1st to 2 (i-1=2) a contact hole
541 and 542 deepen to be the 3rd (i=3) depth d6 and the 2nd depth d5 respectively.At this point, d6, d5 and d4 are respectively the 1st contact hole
541, the predetermined depth of the 2nd contact hole 542 and the 3rd contact hole 543.When contact hole it is more when, according to this side
Formula forms multiple contact holes.In one embodiment, i-th of photoresist pattern can pass through photoresist by (i-1) a photoresist pattern
The mode of trimming is formed.Such as the 2nd photoresist pattern can be formed in such a way that photoresist is trimmed by the 1st photoresist pattern, the 3rd
A photoresist pattern can be formed in such a way that photoresist is trimmed by the 2nd photoresist pattern ... ..., and so on.
In above-mentioned first embodiment, conductive layer and contact portion are to be respectively formed.The embodiment optimized according to one, can
To make a barb under contact portion.Barb can be integrally formed with contact portion, to essentially become contact portion
A part.It summarily says, multiple contact holes can be removed after each contact hole side wall of multiple contact holes forms insulating layer
The first material layer of each contact hole bottom, and form recess of the horizontal size greater than the horizontal size of each contact hole.Recess
It is the space being connected to contact hole.It, can be simultaneously in the recess of each contact hole bottom in the contact portion formed in contact hole
Middle formation barb.
Fig. 6 A-6F is showing for the method for the wordline bonding pad of the formation three-dimensional storage for the first embodiment that the present invention optimizes
Diagrammatic cross-section during example property.Fig. 6 A can then step 208 and the structure of Fig. 3 D.The semiconductor junction exemplified by Fig. 6 A
In the sectional view of structure 600e, remove the bottom of each contact hole 341,342 and 343 part first material layer 321a, 321b and
321c, and form recess 381,382 and 383 of the horizontal size greater than the horizontal size of each contact hole.Here, contact hole 341,
342 and 343 due to insulating layer 351,352 and 353 presence and become smaller, as long as recess 381,382 and 383 be greater than become smaller after connecing
Contact hole.
In the sectional view of semiconductor structure 600f exemplified by Fig. 6 B, in multiple contact hole 341-343 and recess 381-
Protective layer 361,362 and 363 is respectively formed in 383.The material of protective layer 361-363 is, for example, aluminium oxide.
In the sectional view of semiconductor structure 600g exemplified by Fig. 6 C, the first material layer in stack layer 320 is eliminated
321, to form gap S between second material layer 322.In this step, hard mask pattern 330a can be removed together.
The mode for removing first material layer is, for example, wet etching.Can by from upper surface through stack layer 320 through-hole 360 come into
Row wet etching.
In the sectional view of semiconductor structure 600h exemplified by Fig. 6 D, conductive material is filled in stack layer 320, it is conductive
Material can enter stack layer 320 gap S in be filled with conductive layer 323.
In the sectional view of semiconductor structure 600i exemplified by Fig. 6 E, the protective layer in each contact hole 341-343 is removed
361-363.In the sectional view of semiconductor structure 600j exemplified by Fig. 6 F, is formed connect in each contact hole 341-343 respectively
Contact portion 371,372 and 373, and barb 391,392 and 393 is formed in each recess 381-383.It is appreciated that each contact portion
371, there can be gap in 372 and 373, as long as not influencing the electric conductivity of contact portion.Here, due to contact portion 371-373 and
Barb 391-393 is the contact area for being integrally formed, therefore helping to increase contact portion 371-373, reduces resistance.
Contact portion and the material of barb are, for example, metal, such as tungsten (W) or metallic compound, such as titanium nitride
(TiN)。
In the first embodiment, conductive layer and contact portion are to be respectively formed, and be initially formed conductive layer and re-form contact portion.?
In following second embodiment, contact portion can also be initially formed and re-form conductive layer.
Fig. 7 is the method flow diagram of the wordline bonding pad of the formation three-dimensional storage of second embodiment of the invention.Fig. 8 A-8E
It is the section signal in the example process of the method for the wordline bonding pad of the formation three-dimensional storage of third embodiment of the invention
Figure.Below with reference to the method for the formation wordline bonding pad for describing the present embodiment shown in Fig. 7-8E.
In step 702, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for structure of the follow-up process to ultimately form three-dimensional storage.
Semiconductor structure may include array area (array), and array area may include core space (core) and wordline bonding pad.Core space is packet
The region of storage unit is included, wordline bonding pad is the region for including wordline connection circuit.In terms of vertical direction, array area can have
The stack layer of substrate and covering substrate.It is formed with channel hole array on the stack layer of core space or is not yet formed with ditch
Road hole array.It should be pointed out that in the present embodiment, conventional ladder knot is not necessarily forming on the stack layer of wordline bonding pad
Structure.Each layer in stack layer can continuously extend substantially along word-line direction (horizontal direction in Fig. 1), without by ladder
Structure is interrupted.Upper surface due to not having hierarchic structure, entire stack layer is smooth.Stack layer may include being alternately stacked
Multiple first material layers and multiple second material layers.Hard mask layer can be covered on stack layer, be used for subsequent technique.
The example of the semiconductor structure of this step can refer to the sectional view of semiconductor structure 300a exemplified by Fig. 3 A.
In step 704, patterning hard mask layer is to form multiple openings, multiple opening exposure stack layers.
In this step, to form scheduled pattern, this pattern includes a part of alternative removal hard mask layer
The opening of multiple exposed stack layers.These openings are for removing a part of stack layer in the subsequent process to form contact hole.
The method of patterning hard mask layer may include but be not limited to lithography and etching.
The example of the semiconductor structure of this step can refer to the sectional view of semiconductor structure 300b exemplified by Fig. 3 B.
In step 706, multiple contact holes, each contact hole of multiple contact holes are formed in stack layer by multiple openings
Arrive separately at the first material layer of respective predetermined depth.
In this step, from the material of each opening removal stack layer, to form each contact hole.Each contact hole
With respective predetermined depth, respective first material layer is arrived separately at.Typically, each contact hole reaches different first
Material layer, to allow subsequent each contact portion and different first material layers in electrical contact.
Each contact hole can be formed by selective etch.
The example of the semiconductor structure of this step can refer to the sectional view of semiconductor structure 300c exemplified by Fig. 3 C.
In step 708, insulating layer is formed in each contact hole side wall of multiple contact holes, the insulating layer in each contact hole
The first material layer of predetermined depth in each contact hole of exposure.
In this step, insulating layer is formed in the side wall of each contact hole, and does not form insulating layer in the bottom of contact hole,
To the first material layer of predetermined depth in exposure contact hole.
The example of the semiconductor structure of this step can refer to the sectional view of semiconductor structure 300d exemplified by Fig. 3 D.
In step 710, recess is formed in each contact hole bottom of multiple contact holes.
In the sectional view of semiconductor structure 800e exemplified by Fig. 8 A, the bottom of each contact hole 341,342 and 343 is removed
Part first material layer 321a, 321b and 321c, and formed horizontal size greater than each contact hole horizontal size recess
381,382 and 383.Here, contact hole 341,342 and 343 due to insulating layer 351,352 and 353 presence and become smaller, be recessed
As long as 381,382 and 383 are greater than the contact hole after becoming smaller.
In step 712, protective layer is formed in each contact hole of multiple contact holes.
In this step, a protective layer can be formed in the contact hole, and protective layer can be in the first material of subsequent removal
The portion of avoiding contact with is corroded in the step of layer.Due to foring recess in step 710, guarantor is also formd in the valley in this step
Sheath.
In the sectional view of semiconductor structure 800f exemplified by Fig. 8 B, in multiple contact hole 341-343 and multiple recess
Protective layer 361a, 362a and 363a are respectively formed in 381-383.Protective layer 361a-363a only covers the table of contact hole 341-343
Face and it is unfilled inside it.The material of protective layer 361a-363a is, for example, aluminium oxide.
In step 714, contact portion is formed in each contact hole of multiple contact holes, forms barb in the valley.
In the sectional view of semiconductor structure 800g exemplified by Fig. 8 C, is formed connect in each contact hole 341-343 respectively
Contact portion 371,372 and 373, and barb 391,392 and 393 is formed in each recess 381-383.It is appreciated that each contact portion
371, there can be gap in 372 and 373, as long as not influencing the electric conductivity of contact portion.
The material of contact portion is, for example, metal, such as tungsten (W) or metallic compound, such as titanium nitride (TiN).
In this step, by filling contact portion 371-373, conductive path is provided for each conductive layer 323.
In step 716, multiple first material layers in stack layer are replaced with into conductive layer.
In this step, the protective layer for removing multiple first material layers in stack layer and being contacted with first material layer,
Conductive material is filled in the position of first material layer, to form conductive layer.
In the sectional view of semiconductor structure 800h exemplified by Fig. 8 D, the first material layer in stack layer 320 is eliminated
321, to form gap S between second material layer 322.In this step, the protective layer one contacted with first material layer 321
And be removed, leave behind the protective layer of contact hole 341-343 side wall.The mode for removing first material layer is, for example, wet etching.
It can be by carrying out wet etching from upper surface through the through-hole 360 of stack layer 320.
In the sectional view of semiconductor structure 800i exemplified by Fig. 8 E, conductive material is filled in stack layer 320, it is conductive
Material can enter stack layer 320 gap S in be filled with conductive layer 323.
Other details of three-dimensional storage, such as structure, the periphery interconnection of storage array etc., and the emphasis of non-present invention,
Not reinflated description herein.
In the context of the present invention, three-dimensional storage can be 3D flash memory, such as 3D nand flash memory.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect therefore of the invention protection model
It encloses to work as and subject to the definition of the claims.
Claims (18)
1. a kind of method for the wordline bonding pad for forming three-dimensional storage, includes the following steps：
Semiconductor structure is provided, the semiconductor structure has substrate, the stack layer of the covering substrate and the covering stacking
The hard mask layer of layer, the stack layer includes the multiple first material layers and multiple second material layers being alternately stacked；
The hard mask layer is patterned to form multiple openings, the multiple opening exposure stack layer；
Multiple contact holes, each contact hole point of the multiple contact hole are formed in the stack layer by the multiple opening
It is clipped to the first material layer up to respective predetermined depth；
Insulating layer is formed in each contact hole side wall of the multiple contact hole；
Protective layer is filled in the insulating layer of the multiple contact hole；
The multiple first material layer in the stack layer is replaced with into conductive layer；And
Contact portion is formed in each contact hole of the multiple contact hole.
2. the method as described in claim 1, which is characterized in that the material of the hard mask layer is polysilicon.
3. the method as described in claim 1, which is characterized in that with the deep trap of the first doping type in the substrate.
4. the method as described in claim 1, which is characterized in that
It further include remove the multiple contact hole every after each contact hole side wall of the multiple contact hole forms insulating layer
The part first material layer of a contact hole bottom, and it is recessed greater than the horizontal size of each contact hole to form horizontal size
It falls into；
While filling protective layer in the insulating layer of the multiple contact hole, protective layer is filled in the recess；
And when forming contact portion in each contact hole of the multiple contact hole, connect together in each of the multiple contact hole
Barb is formed in the recess of contact hole bottom.
5. the method as described in claim 1, which is characterized in that formed in the stack layer by the multiple opening multiple
The method of contact hole includes sequentially forming the multiple contact hole, wherein forming wherein one first contact of the multiple contact hole
The method in hole includes：
Form the first photoresist pattern on the semiconductor structure, the in the multiple opening of the first photoresist pattern exposure
One opening；
The first contact hole is formed in the stack layer by first opening, first contact hole reaches the first pre- depthkeeping
The first material layer of degree.
6. the method as described in claim 1, which is characterized in that formed in the stack layer by the multiple opening multiple
The step of contact hole includes being formed simultaneously the multiple contact hole, if the quantity of the multiple contact hole is N, is formed described N number of
The step of i-th of contact hole in contact hole includes：
I-th of photoresist pattern is formed on the semiconductor structure, and i-th of photoresist pattern exposes in the multiple opening
1st to i-th opening；
The i-th contact hole is formed in the stack layer by i-th opening, i-th contact hole is the 1st depth；And pass through
1st to the (i-1)-th opening deepens the 1st to (i-1)-th contact hole to be the i-th depth to the 2nd depth respectively；
Wherein i=1,2,3 ..., N.
7. method as claimed in claim 6, which is characterized in that i-th of photoresist pattern is led to by (i-1)-th photoresist pattern
The mode for crossing photoresist trimming is formed.
8. the method as described in claim 1, which is characterized in that when patterning the hard mask layer, the stack layer it is upper
Surface is smooth.
9. the method as described in claim 1, which is characterized in that first replace the multiple first material layer in the stack layer
It is changed to conductive layer, then forms the contact portion in each contact hole of the multiple contact hole.
10. the method as described in claim 1, which is characterized in that replace the multiple first material layer in the stack layer
The step of being changed to conductive layer include：By running through the slit of the stack layer from upper surface, remove described in the stack layer
After multiple first material layers, the conductive material is filled to the stack layer to form the conductive layer.
11. the method as described in claim 1, which is characterized in that formed and connect in each contact hole of the multiple contact hole
The step of contact portion includes：Protective layer in each contact hole of the multiple contact hole is replaced with into contact portion.
12. the method as described in claim 1, which is characterized in that first formed in each contact hole of the multiple contact hole
Contact portion, then the multiple first material layer in the stack layer is replaced with into conductive layer.
13. method as claimed in claim 12, which is characterized in that formed and connect in each contact hole of the multiple contact hole
Before contact portion, protective layer is first formed in each contact hole of the multiple contact hole, the protective layer covers the contact hole
Bottom, the contact site is in the protective layer.
14. a kind of three-dimensional storage, including：
Semiconductor substrate；
Stack layer is located on the substrate and including spaced wordline；
Each contact portion of multiple contact portions, the multiple contact portion is upward through institute in the side perpendicular to the semiconductor substrate
It states stack layer and the respectively word line contact with respective predetermined depth, and the side wall of each contact portion and is passed through by each contact portion
It is electrically isolated between the wordline worn；
One or more grid separate slots, extend vertically through the stack layer.
15. three-dimensional storage as claimed in claim 14, which is characterized in that the upper surface of the stack layer is smooth.
16. three-dimensional storage as claimed in claim 14, which is characterized in that each wordline is continuously prolonged along word-line direction
It stretches.
17. three-dimensional storage as claimed in claim 14, which is characterized in that with the depth of the first doping type in the substrate
Trap.
18. three-dimensional storage as claimed in claim 14, which is characterized in that correspond to respective contact hole in each wordline
Position have barb, the barb in corresponding contact hole contact portion integrated molding.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112786447A (en) * | 2021-01-22 | 2021-05-11 | 长江存储科技有限责任公司 | Method for removing aluminum oxide and method for preparing three-dimensional memory |
| CN113540040A (en) * | 2021-07-15 | 2021-10-22 | 长江存储科技有限责任公司 | Manufacturing method and testing method of semiconductor structure |
| WO2022213514A1 (en) * | 2021-04-07 | 2022-10-13 | 长鑫存储技术有限公司 | Fabrication method for memory and memory |
| WO2024087787A1 (en) * | 2022-10-25 | 2024-05-02 | 长鑫存储技术有限公司 | Semiconductor structure, formation method therefor, and memory |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101911298A (en) * | 2008-01-16 | 2010-12-08 | 美光科技公司 | 3-d and 3-d schottky diode for cross-point, variable-resistance material memories, processes of forming same, and methods of using same |
| US20120276696A1 (en) * | 2011-04-29 | 2012-11-01 | Yang Jun-Kyu | Vertical structure non-volatile memory device and method of manufacturing the same |
| US20140106569A1 (en) * | 2012-10-16 | 2014-04-17 | Jung-Ik Oh | Method of fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated using the same |
| CN103872005A (en) * | 2012-12-13 | 2014-06-18 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
| US20140306279A1 (en) * | 2013-04-11 | 2014-10-16 | Jintaek Park | Semiconductor devices including word line interconnecting structures |
| US20150380418A1 (en) * | 2014-06-27 | 2015-12-31 | SanDisk Technologies, Inc. | Three dimensional nand device with channel contacting conductive source line and method of making thereof |
| US9236392B1 (en) * | 2014-08-26 | 2016-01-12 | Sandisk Technologies Inc. | Multiheight electrically conductive via contacts for a multilevel interconnect structure |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| US9824966B1 (en) * | 2016-08-12 | 2017-11-21 | Sandisk Technologies Llc | Three-dimensional memory device containing a lateral source contact and method of making the same |
| US20180012937A1 (en) * | 2016-07-06 | 2018-01-11 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices |
| US20180102314A1 (en) * | 2016-09-02 | 2018-04-12 | SK Hynix Inc. | Semiconductor device |
| CN208835065U (en) * | 2018-06-22 | 2019-05-07 | 长江存储科技有限责任公司 | Three-dimensional storage |
-
2018
- 2018-06-22 CN CN201810652369.9A patent/CN108831891B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101911298A (en) * | 2008-01-16 | 2010-12-08 | 美光科技公司 | 3-d and 3-d schottky diode for cross-point, variable-resistance material memories, processes of forming same, and methods of using same |
| US20120276696A1 (en) * | 2011-04-29 | 2012-11-01 | Yang Jun-Kyu | Vertical structure non-volatile memory device and method of manufacturing the same |
| US20140106569A1 (en) * | 2012-10-16 | 2014-04-17 | Jung-Ik Oh | Method of fabricating three-dimensional semiconductor device and three-dimensional semiconductor device fabricated using the same |
| CN103872005A (en) * | 2012-12-13 | 2014-06-18 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
| US20140306279A1 (en) * | 2013-04-11 | 2014-10-16 | Jintaek Park | Semiconductor devices including word line interconnecting structures |
| US20150380418A1 (en) * | 2014-06-27 | 2015-12-31 | SanDisk Technologies, Inc. | Three dimensional nand device with channel contacting conductive source line and method of making thereof |
| US9236392B1 (en) * | 2014-08-26 | 2016-01-12 | Sandisk Technologies Inc. | Multiheight electrically conductive via contacts for a multilevel interconnect structure |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| US20180012937A1 (en) * | 2016-07-06 | 2018-01-11 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices |
| US9824966B1 (en) * | 2016-08-12 | 2017-11-21 | Sandisk Technologies Llc | Three-dimensional memory device containing a lateral source contact and method of making the same |
| US20180102314A1 (en) * | 2016-09-02 | 2018-04-12 | SK Hynix Inc. | Semiconductor device |
| CN208835065U (en) * | 2018-06-22 | 2019-05-07 | 长江存储科技有限责任公司 | Three-dimensional storage |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112786447A (en) * | 2021-01-22 | 2021-05-11 | 长江存储科技有限责任公司 | Method for removing aluminum oxide and method for preparing three-dimensional memory |
| WO2022213514A1 (en) * | 2021-04-07 | 2022-10-13 | 长鑫存储技术有限公司 | Fabrication method for memory and memory |
| CN113540040A (en) * | 2021-07-15 | 2021-10-22 | 长江存储科技有限责任公司 | Manufacturing method and testing method of semiconductor structure |
| WO2024087787A1 (en) * | 2022-10-25 | 2024-05-02 | 长鑫存储技术有限公司 | Semiconductor structure, formation method therefor, and memory |
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|---|---|
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