CN108831876B - Packaging structure embedded with filter chip and provided with holes and manufacturing method thereof - Google Patents
Packaging structure embedded with filter chip and provided with holes and manufacturing method thereof Download PDFInfo
- Publication number
- CN108831876B CN108831876B CN201810911108.4A CN201810911108A CN108831876B CN 108831876 B CN108831876 B CN 108831876B CN 201810911108 A CN201810911108 A CN 201810911108A CN 108831876 B CN108831876 B CN 108831876B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- insulating layer
- hole
- cofferdam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 187
- 238000000465 moulding Methods 0.000 claims description 56
- 238000007747 plating Methods 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 238000007789 sealing Methods 0.000 claims description 19
- 238000000227 grinding Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims 9
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract description 5
- 238000012536 packaging technology Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 16
- 230000006872 improvement Effects 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a packaging structure with embedded filter chip and holes and a manufacturing method thereof, wherein the packaging structure comprises: a package substrate having a chamber; the filter chip is arranged in the cavity, the first upper surface and the upper surface of the substrate are positioned on the same side, and the first upper surface is provided with a plurality of first electrodes; the functional chip is arranged above the packaging substrate, the second lower surface and the upper surface of the substrate are arranged face to face, and the second upper surface is provided with a plurality of second electrodes; and the interconnection structures are used for conducting the first electrode and the second electrode through the holes. According to the invention, two different chips are packaged on the same packaging substrate by using a packaging technology, so that high integration of multiple chips can be realized; the filter chips and the functional chips are distributed up and down, and the functional chips above the packaging substrate do not occupy the space of the packaging substrate, so that the utilization rate of the packaging substrate can be improved, and the interconnection structure is simplified; the filter chip is embedded in the cavity, so that the packaging structure is lighter and thinner.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a packaging structure embedded with a filter chip and provided with holes and a manufacturing method thereof.
Background
In order to meet the trend of increasingly thin, light, thin and small electronic products, the filter, the radio frequency transmitting component and the radio frequency receiving component need to be highly integrated in a package structure with a limited area to form a system-in-package (SystemInPackage, SIP) structure so as to reduce the size of a hardware system.
For the integration technology of the filter and the rf front-end module package in the system-in-package structure, there are still a number of technical issues to be solved in the industry, such as the protection structure of the filter, the connection structure between the chips, the layout of the chips, and so on.
Disclosure of Invention
The invention aims to provide a packaging structure with a built-in filter chip and holes and a manufacturing method thereof.
In order to achieve one of the above objects, an embodiment of the present invention provides a package structure with a built-in filter chip and a hole, including:
the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged, and the packaging substrate is provided with a cavity;
the filter chip is arranged in the cavity and provided with a first upper surface and a first lower surface which are oppositely arranged, the first upper surface and the upper surface of the substrate are positioned on the same side, and the first upper surface is provided with a plurality of first electrodes;
The functional chip is arranged above the packaging substrate and is provided with a second upper surface and a second lower surface which are oppositely arranged, the second lower surface and the upper surface of the substrate are arranged face to face, and the second upper surface is provided with a plurality of second electrodes;
and the interconnection structures are used for conducting the first electrodes and the second electrodes through the holes.
As a further improvement of an embodiment of the present invention, one side of the lower surface of the substrate has a plurality of external pins, the package substrate has a plurality of through holes, and the interconnection structure conducts the first electrode, the second electrode and the external pins through the through holes.
As a further improvement of an embodiment of the present invention, the through holes and the second electrodes are spaced apart from each other.
As a further improvement of an embodiment of the present invention, the interconnection structure includes a metal pillar and a plating layer structure, the metal pillar conducts the second electrode, the plating layer structure conducts the first electrode and the metal pillar, and the plating layer structure extends to the lower side of the package substrate through the through hole to conduct the external pin.
As a further improvement of an embodiment of the present invention, the plating layer structure includes an upper redistribution layer, a middle redistribution layer and a lower redistribution layer, wherein the upper redistribution layer is located above the package substrate and conducts the first electrode and the second electrode, the lower redistribution layer is located below the package substrate and conducts the external pin, and the middle wiring layer includes a first plating layer located on an upper surface of the substrate, a second plating layer located on an inner wall of the through hole and a third plating layer located on a lower surface of the substrate, where the first plating layer is connected to the upper redistribution layer, and the third plating layer is connected to the lower redistribution layer.
As a further improvement of an embodiment of the present invention, the package structure includes a first insulating layer located on the upper surface of the substrate and above the first upper surface, a first upper redistribution layer passing through the hole on the first insulating layer to conduct the first plating layer and the first electrode, a second insulating layer connecting the first insulating layer and the second lower surface, and a second upper redistribution layer passing through the hole on the second insulating layer to conduct the first upper redistribution layer, wherein the second upper redistribution layer conducts the metal pillar.
As a further improvement of an embodiment of the present invention, the first insulating layer and the second insulating layer cooperate to form a dam, the dam cooperates with the second lower surface and the first upper surface to enclose a cavity, the dam includes a first dam located inside the plurality of first electrodes and a second dam located outside the plurality of first electrodes, the first dam cooperates with the second lower surface and the first upper surface to enclose a cavity, the second dam extends in a direction away from the first dam until an outer edge of the second dam is flush with an outer edge of the package substrate, and the second dam exposes the through hole.
As a further improvement of an embodiment of the present invention, the package structure further includes a first molding layer and a top molding layer located on a side of the package substrate away from the lower surface of the substrate, the first molding layer encapsulates an upper surface area of the second insulating layer exposed, the functional chip and the metal pillar, the first molding layer fills the through hole, the second upper redistribution layer passes through holes on the first molding layer and the second insulating layer to conduct the first upper redistribution layer, the second redistribution layer extends to the upper surface of the first molding layer to conduct the metal pillar, and the top molding layer encapsulates the first molding layer and the second upper redistribution layer.
As a further improvement of an embodiment of the present invention, the package structure includes a third insulating layer covering the third plating layer and the lower surface of the substrate, a lower redistribution layer passing through the hole on the third insulating layer to conduct the third plating layer and extending toward the lower surface of the third insulating layer, and a fourth insulating layer covering the third insulating layer and the lower redistribution layer, wherein the external pins are connected to the lower redistribution layer, and the fourth insulating layer exposes the external pins.
As a further improvement of an embodiment of the present invention, a gap between the filter chip and the cavity, the lower surface of the substrate and the first lower surface are provided with a second plastic sealing layer, and the first upper surface is flush with the upper surface of the substrate.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for manufacturing a package structure with a built-in filter chip and a hole, including the steps of:
s1: providing a packaging substrate, wherein the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged;
s2: forming a cavity on the packaging substrate;
s3: providing a filter chip, wherein the filter chip is provided with a first upper surface and a first lower surface which are oppositely arranged, and the first upper surface is provided with a plurality of first electrodes;
s4: loading the filter chip into the chamber, the first upper surface being on the same side as the substrate upper surface;
s5: forming a first interconnection structure on the packaging substrate, wherein the first interconnection structure conducts the first electrode;
s6: providing a functional chip, wherein the functional chip is provided with a second upper surface and a second lower surface which are oppositely arranged, and the second upper surface is provided with a plurality of second electrodes;
S7: the functional chip is loaded above the packaging substrate, the second lower surface and the upper surface of the substrate are arranged face to face, and a second interconnection structure for conducting the second electrode and the first interconnection structure through the hole is formed;
s8: a third interconnect structure is formed that conducts the external pins and the first interconnect structure.
As a further improvement of an embodiment of the present invention, step S4 specifically includes:
providing a temporary bonding plate;
bonding the upper surface of the substrate of the packaging substrate to the temporary bonding plate;
loading the filter chip into the chamber, the first upper surface being on the same side as the substrate upper surface;
forming a second plastic layer which covers the gap between the filter chip and the cavity, the lower surface of the substrate and the first lower surface;
removing the temporary bonding plate;
inverting the package substrate;
forming a plurality of through holes on the packaging substrate, wherein the through holes penetrate through the second plastic sealing layer;
the step S5 specifically comprises the following steps:
forming a first electroplated layer on the upper surface of the substrate, forming a second electroplated layer on the inner wall of the through hole, and forming a third electroplated layer below the second plastic sealing layer;
a first insulating layer is arranged on the upper surface of the substrate;
Forming a first upper rewiring layer above the first insulating layer, wherein the first upper rewiring layer is used for conducting the first electrode and the first electroplated layer through holes in the first insulating layer;
a second insulating layer is arranged above the first insulating layer, the first upper rewiring layer and the protection area, the first insulating layer and the second insulating layer are matched to form a cofferdam, the cofferdam comprises a first cofferdam and a second cofferdam, the first cofferdam is positioned at the periphery of a cavity, the outer side edge of the second cofferdam is flush with the outer side edge of the packaging substrate, and the second cofferdam exposes the through hole;
the steps S7 and S8 specifically include:
forming a metal column above the second electrode;
the functional chip is loaded above the packaging substrate, the second lower surface and the upper surface of the substrate are arranged face to face, and the first cofferdam, the second lower surface and the first upper surface are mutually matched to enclose a cavity corresponding to the protection area;
forming a first plastic sealing layer on one side of the packaging substrate, which is far away from the lower surface of the substrate, wherein the first plastic sealing layer simultaneously covers the upper surface area, the functional chip and the metal column, which are exposed outside the second cofferdam, and the first plastic sealing layer fills the through hole;
Grinding the first plastic sealing layer to expose the metal posts;
forming a second upper rewiring layer on the first plastic sealing layer, wherein the second upper rewiring layer is communicated with the first upper rewiring layer through holes in the first plastic sealing layer and the second insulating layer, and the second upper rewiring layer is communicated with the second electrode;
forming a top molding layer over the first molding layer and the second upper rewiring layer;
forming a third insulating layer below the third electroplated layer and the second plastic sealing layer;
forming a lower rewiring layer below the third insulating layer, wherein the lower rewiring layer is communicated with the third electroplated layer through a hole in the third insulating layer;
forming a fourth insulating layer covering the third insulating layer and the lower rewiring layer, wherein the fourth insulating layer exposes the lower rewiring layer;
the exposed lower rewiring layer forms a ball grid array.
Compared with the prior art, the invention has the beneficial effects that: according to the embodiment of the invention, two different chips are packaged on the same packaging substrate by using a packaging technology, so that high integration of multiple chips can be realized, the utilization rate of the packaging substrate is improved, and further miniaturization of a packaging structure is realized; in addition, the filter chips and the functional chips are distributed up and down, the functional chips above the packaging substrate do not occupy the space of the packaging substrate, the utilization rate of the packaging substrate can be further improved, the space between the filter chips and the functional chips is reduced, the interconnection between the filter chips and the functional chips is convenient to realize, and the interconnection structure is simplified; moreover, the filter chip is embedded in the cavity, so that the packaging structure is lighter and thinner.
Drawings
FIG. 1 is an exemplary radio frequency front end module of the present invention;
FIG. 2 is a radio frequency front end module of another example of the present invention;
FIG. 3 is a cross-sectional view of a package structure according to an embodiment of the present invention;
FIG. 4 is a schematic view of a dam-fitting through hole and a first electrode according to an embodiment of the present invention;
FIG. 5 is a step diagram of a method for fabricating a package structure according to an embodiment of the present invention;
fig. 6a to 6z-19 are flowcharts illustrating a method for fabricating a package structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
In the various illustrations of the present application, certain dimensions of structures or portions may be exaggerated relative to other structures or portions for convenience of illustration, and thus serve only to illustrate the basic structure of the subject matter of the present application.
In addition, terms such as "upper", "above", "lower", "below", and the like, used herein to denote spatially relative positions are used for convenience of description to describe one element or feature relative to another element or feature as illustrated in the figures. The term spatially relative position may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Referring to fig. 1 and fig. 2, an embodiment of the present invention provides a general rf front-end module, which may be used in mobile devices such as a mobile phone and a computer, or other electronic devices.
Referring to fig. 1, in an example, the radio frequency front end module includes a power amplifier module 200 (Power Amplifier Module, PAM), and the power amplifier module 200 includes a first amplifier unit 201, a first RF switch unit 202, and a first RF filter unit 203 electrically connected in sequence, where the first amplifier unit 201 is a multimode-wide bandwidth power amplifier unit.
In actual operation, the first amplifier unit 201 is configured to receive the modulated signal output by other components, and output the modulated signal through the filter unit 203 after the modulation, amplification and filtering operations of the power amplifier module 200.
Referring to fig. 2, in another example, the radio frequency front end module includes a receive diversity module 300 (Receive Diversity Module, RDM), where the receive diversity module 300 includes a low noise amplification multiplexer 301 (LNA Multiplexer Module, LMM), a second RF filter unit 302, and an RF antenna switch unit 303 electrically connected in sequence, and the low noise amplification multiplexer 301 includes a second amplifier unit 3011 and a second RF switch unit 3012 electrically connected, the second amplifier unit 3011 is a multimode-wide bandwidth low noise amplifier unit, and two ends of the second RF switch unit 3012 are connected to the second amplifier unit 3011 and the second RF filter unit 302, respectively.
In actual operation, the signal is divided into a high frequency signal and a low frequency signal by the diplexer 304, where the high frequency signal is taken as an example, the high frequency signal enters the RF antenna switch unit 303, and then sequentially passes through the second RF filter unit 302 and the low noise amplification multiplexer 301 for filtering, modulating, amplifying, and outputting by the second amplifier unit 3011.
It will be appreciated that the electrical connection between the various units, such as the RF switch unit, the filter unit, the amplifier unit, etc., may be achieved by a packaging process, i.e. packaging the RF switch chip, the amplifier chip, the filter chip, etc., together to achieve various functions.
The present embodiment describes an example of a package structure and a process of an RF switch chip, an amplifier chip, and a filter chip.
Referring to fig. 3, a cross-sectional view of a package structure 100 with a built-in filter chip and holes according to an embodiment of the invention is shown.
The package structure 100 includes a package substrate 10, a filter chip 20, a functional chip 30, and a plurality of interconnect structures 50.
The package substrate 10 has a substrate upper surface 11 and a substrate lower surface 12 disposed opposite to each other, and the package substrate 10 has a chamber 101.
Here, the package substrate 10 is a carrier plate for carrying chips, and the package substrate 10 may be a printed circuit board made of an organic resin, a glass substrate, a ceramic substrate, or the like.
The chamber 101 may be a through hole penetrating the package substrate 10, but is not limited thereto.
The filter chip 20 is disposed in the chamber 101, the filter chip 20 has a first upper surface 21 and a first lower surface 22 disposed opposite to each other, the first upper surface 21 and the substrate upper surface 11 are located on the same side, and the first upper surface 21 has a plurality of first electrodes 211.
The first electrode 211 protrudes from the first upper surface 21 in a direction away from the first lower surface 22, but is not limited thereto.
The filter chip 20 may be a surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or a bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but is not limited thereto, and an Active Zone (Active Zone) on the surface of the filter chip 20 needs to be in contact with or covered by an external object to work normally, that is, a cavity needs to be formed under the filter chip 20 to protect the Active Zone.
The functional chip 30 is disposed above the package substrate 10, the functional chip 30 has a second upper surface 31 and a second lower surface 32 disposed opposite to each other, the second lower surface 32 is disposed opposite to the substrate upper surface 11, and the second upper surface 31 has a plurality of second electrodes 311.
The second electrode 311 protrudes from the second upper surface 31 in a direction away from the second lower surface 32, but is not limited thereto.
The functional chip 30 is an amplifier chip or an RF switch chip, but not limited thereto.
The interconnection structures 50 are connected to the first electrodes 211 and the second electrodes 311 through the holes.
Here, "the plurality of interconnection structures 50 are connected to the plurality of first electrodes 211 and the plurality of second electrodes 311 through the holes" means that at least a portion of the interconnection structures 50 are electrically connected to the first electrodes 211 and the second electrodes 311 through the holes, that is, the interconnection between the filter chip 20 and the functional chip 30 is achieved.
In the present embodiment, two different chips (the filter chip 20 and the functional chip 30) are packaged on the same package substrate 10 by using the packaging technology, so that high integration of multiple chips can be realized, the utilization rate of the package substrate 10 can be improved, and further, the miniaturization of the package structure 100 can be realized.
In addition, the filter chip 20 and the functional chip 30 are vertically distributed, the functional chip 30 above the package substrate 10 does not occupy the space of the package substrate 10, the utilization rate of the package substrate 10 can be further improved, the space between the filter chip 20 and the functional chip 30 is reduced, the interconnection between the filter chip 20 and the functional chip 30 is convenient to realize, and the interconnection structure is simplified.
Furthermore, the filter chip 20 is embedded in the cavity 101, so that the package structure 100 is lighter and thinner.
It should be noted that, in the package structure 100 of the present embodiment, one filter chip 20 and one functional chip 30 are mounted on the package substrate 10 as an example, it is understood that in practical application, referring to fig. 1 and 2, the package structure may include a plurality of filter chips 20 and a plurality of functional chips 30, for example, the periphery (including the up-down, front-back, left-right three-dimensional directions) of the filter chips 20 may be electrically connected with a plurality of functional chips 30.
In the present embodiment, the functional chip 30 is located above the chamber 101, and the plurality of first electrodes 211 and the plurality of second electrodes 311 are disposed opposite to each other.
That is, the filter chip 20 and the functional chip 30 are disposed vertically correspondingly, and the first electrode 211 and the second electrode 311 are disposed on opposite sides of the package substrate 10, so that the filter chip 20 does not occupy too much space in the horizontal direction of the package substrate 10, and the package substrate 10 can be made small in size.
Here, the size of the functional chip 30 is larger than that of the filter chip 20, and there is partial overlap between the functional chip 30 and the chamber 101.
That is, the outline of the functional chip 30 is partially overlapped between the vertical projection on the package substrate 10 and the chamber 101.
In the present embodiment, one side of the package substrate 10 has a plurality of external pins 121, and the interconnection structure 50 is used for conducting the first electrode 211, the second electrode 311 and the external pins 121.
The external pins 121 may be Ball Grid Array (BGA), pads, etc., and the package structure 100 may be electrically connected to other chips or substrates through the external pins 121, where the external pins 121 take the BGA 121 as an example, and the external pins 121 protrude from the lower surface of the package structure 100.
In addition, the external pins 121 are located on one side of the lower surface 12 of the substrate, but not limited to this, the external pins 121 may be located in other areas.
The package substrate 10 has a plurality of through holes 13, and the interconnection structure 50 conducts the first electrode 211, the second electrode 311 and the external pins 121 through the through holes 13.
In the present embodiment, the through holes 13 and the second electrodes 311 are spaced apart from each other.
Here, the through hole 13 is located at the outer side of the second electrode 311, and the through hole 13 is located at the outer side of the cavity 101, at this time, the external pins 121 located at the side of the lower surface 12 of the substrate may be moved outward toward both sides of the functional chip 30, so that the space in which other chips are buried is conveniently arranged in advance, thereby facilitating realization of a high-performance and small-sized multi-chip 2.5D or 3D stacked integrated package and module.
In this embodiment, the interconnect structure 50 includes a metal pillar 51 and a plating layer structure 53.
The metal pillar 51 conducts the second electrode 311, and at this time, the metal pillar 51 is disposed above the second electrode 311.
The plating structure 53 conducts the first electrode 211 and the metal post 51, and the plating structure 53 extends to the lower side of the package substrate 10 through the through hole 13 to conduct the external pin 121.
Specifically, the plating layer structure 53 includes an upper rewiring layer 531, an intermediate wiring layer 532, and a lower rewiring layer 533 which are conductive to each other.
The upper re-wiring layer 531 is located above the package substrate 10 and conducts the first electrode 211 and the second electrode 311.
The intermediate wiring layer 532 includes a first plating layer 5321 on the substrate upper surface 11, a second plating layer 5322 on the inner wall of the through hole 13, and a third plating layer 5323 on the substrate lower surface 12 connected.
The first plating layer 5321 is connected to the upper rerouting layer 531.
The width of the first plating layer 5321 connecting the upper re-wiring layer 531 extending to the substrate upper surface 11 is substantially equal to the width of the corresponding third plating layer 5323 extending to the substrate lower surface 12.
Here, on one hand, the upper surface 11 and the lower surface 12 of the substrate are provided with plating layers, so that the bonding firmness of the plating layers and the packaging substrate 10 can be improved; on the other hand, the first plating layer 5321 extends toward the first electrode 211 so that the upper re-wiring layer 531 is connected to the first plating layer 5321, and the through holes 13 can be moved outward toward both sides, thereby allowing the external pins 121 of the lower surface 12 of the substrate to be moved outward.
The lower rerouting layer 533 is located under the package substrate 10 and conducts the external pins 121, and the lower rerouting layer 533 is connected to the third plating layer 5323.
Here, the upper rerouting layer 531 includes a first upper rerouting layer 5311 and a second upper rerouting layer 5312.
Specifically, the package structure 100 includes a first insulating layer 70 disposed on the upper surface 11 of the substrate and above the first upper surface 21, a first upper redistribution layer 5311 passing through the hole on the first insulating layer 70 to conduct the first plating layer 5321 and the first electrode 211, a second insulating layer 71 connecting the first insulating layer 70 and the second lower surface 32, and a second upper redistribution layer 5312 passing through the hole on the second insulating layer 71 to conduct the first upper redistribution layer 5311, wherein the second upper redistribution layer 5312 conducts the metal pillar 51.
The package structure 100 includes a third insulating layer 72 covering the third plating layer 5323 and the lower surface 12 of the substrate, a lower rerouting layer 533 passing through the hole on the third insulating layer 72 to conduct the third plating layer 5323 and extending toward the lower surface of the third insulating layer 72, and a fourth insulating layer 73 covering the third insulating layer 72 and the lower rerouting layer 533, wherein the external leads 121 are connected to the lower rerouting layer 533, and the fourth insulating layer 73 exposes the external leads 121.
The arrangement of the lower rerouting layer 533 not only can expand the rerouting range and improve the degree of freedom of the subsequent layout of the external pins 121, but also can further assist the outward movement of the external pins 121.
The metal posts 51 are copper posts, and the upper rerouting layer 531, the intermediate rerouting layer 532, and the lower rerouting layer 533 are copper layers.
The electrical connection among the first electrode 211, the second electrode 311 and the external pin 121 is realized by adopting a simple re-wiring (RDL) scheme, so that the process is stable and the reliability is high.
The metal wire material of the redistribution layer is copper (i.e., the upper redistribution layer 531, the middle redistribution layer 532, and the lower redistribution layer 533 are all copper layers), and a metal or alloy film for enhancing the mutual adhesion of the redistribution copper and the chip electrode (including the first electrode 211 and the second electrode 311) may be disposed between the redistribution copper and the chip electrode, and the metal or alloy material may be nickel, titanium, nickel-chromium, titanium-tungsten, or the like.
The first, second and third insulating layers 70, 71 and 72 are interposed among the package substrate 10, the upper and lower re-wiring layers 531 and 533, thereby achieving electrical isolation between the respective components.
It is understood that the upper redistribution layer 531 in the redistribution scheme is not limited to the two layers, and the lower redistribution layer 533 is not limited to the one layer, and may be determined according to practical situations.
In addition, the present embodiment provides the second upper rerouting layer 5312 with advantages in that: simple structure reduces the technology degree of difficulty, improves production efficiency.
In the present embodiment, the first insulating layer 70 and the second insulating layer 71 cooperate to form the bank 40, and the bank 40 cooperates with the second lower surface 32 and the first upper surface 21 to enclose a cavity S, which corresponds to the active region of the surface of the filter chip 20.
In this embodiment, the cofferdam 40 is provided to form the cavity S, so that the influence of the external substances entering the cavity S during the manufacturing process of the package structure or the use process of the package structure on the normal use of the filter chip 20 can be effectively avoided, thereby improving the overall performance of the package structure 100.
In the present embodiment, the cavity S is located inside the plurality of first electrodes 211.
The cofferdam 40 comprises a first cofferdam 41 positioned at the inner side of the first electrodes 211 and a second cofferdam 42 positioned at the outer side of the first electrodes 211, and the first cofferdam 41, the second lower surface 32 and the first upper surface 21 are mutually matched to form a cavity S.
Here, the first cofferdam 41 is located inside the through hole 13, the second cofferdam 42 is located partly inside the through hole 13, and partly outside the through hole 13.
Because the cofferdam 40 has a certain height, when the lower surface area of the cofferdam 40 is too small, the cofferdam 40 with the height can not be supported, so that the cofferdam 40 is collapsed, the cofferdam 40 in the embodiment comprises a first cofferdam 41 and a second cofferdam 42, and the cofferdam 40 has a sufficiently large lower surface, so that the stability of the whole cofferdam 40 is improved; in addition, the lower surface of the dam 40 can be combined with the whole area of the upper surface of the filter chip 20 outside the area of the cavity S on the upper surface of the filter chip 20, thereby further improving the molding stability of the cavity S.
Referring to fig. 4, a plurality of through holes 13 are distributed on the upper surface 11 of the substrate in an array, and an interval is provided between two adjacent through holes 13, a space is provided between two rows of through holes 13, a cavity 101 is located in the space, and an interval is provided between the cavity 101 and the through holes 13, a first cofferdam 41 corresponds to an inner area of the cavity 101, the first cofferdam 41 is substantially located at an inner side of the first electrode 211, a second cofferdam 42 extends from the inner area of the corresponding cavity 101 towards the direction of the through holes 13, a slot 43 is located above the cofferdam 40, and the slot 43 is located at an outer side of the functional chip 30.
In addition, the second dam 42 extends in a direction away from the first dam 41 until an outer edge of the second dam 42 is flush with an outer edge of the package substrate 10, and the second dam 42 exposes the through hole 13.
Of course, since the package substrate 10 has a quadrilateral structure, the outer edge further includes the front side edge and the rear side edge of the package substrate 10, and the second cofferdam 42 also extends to the front side edge and the rear side edge, but not limited thereto, the package substrate 10 may have other shapes.
It should be noted that, the first cofferdam 41 and the second cofferdam 42 may be independent from each other, for example, the first cofferdam 41 is a first annular structure, the first annular structure is located at the inner sides of the plurality of first electrodes 211, the second cofferdam 42 is a second annular structure, and the second annular structure is located at the outer sides of the plurality of first electrodes 211.
Of course, the first cofferdam 41 and the second cofferdam 42 may be mutually communicated, and in this case, the first cofferdam 41 and the second cofferdam 42 are mutually connected through the third weir 45, and the third weir 45 is located between the adjacent through holes 13, the adjacent first electrodes 211 or other areas, that is, the cofferdam 40 is distributed over the upper surface 11 and the upper surface 21 of the substrate except for the whole areas of the cavity S and the through holes 13.
In the present embodiment, the second lower surface 32 of the functional chip 30 covers the upper surface of the first bank 41, and the second lower surface 32 partially overlaps the upper surface of the second bank 42, and the first upper surface 21 and the substrate upper surface 11 cover the lower surfaces of the first bank 41 and the second bank 42 together.
The dam 40 is made of a light-sensitive insulating material, but is not limited thereto.
In this embodiment, the package structure 100 further includes a first molding layer 60 and a top molding layer 62.
The first molding layer 60 encapsulates the exposed upper surface area of the second insulating layer 71 (i.e., the exposed upper surface area of the second dam 42), the functional chip 30 and the metal pillars 51, the first molding layer 60 fills the through holes 13, the second upper redistribution layer 5312 passes through the holes on the first molding layer 60 and the second insulating layer 71 to conduct the first upper redistribution layer 5311, the second redistribution layer 5312 extends to the upper surface of the first molding layer 60 to conduct the metal pillars 51, and the top molding layer 62 encapsulates the first molding layer 60 and the second upper redistribution layer 5312.
Here, the first molding layer 60 exposes the upper end surface of the metal pillar 51, the first molding layer 60 and the second insulating layer 71 are formed with a groove 43, the groove 43 exposes the first upper redistribution layer 5311, the groove 43 is a chute with a wide upper portion and a narrow lower portion, and the second upper redistribution layer 5312 is disposed along the inner wall of the groove 43 and extends to the upper surface of the first molding layer 60 to conduct the metal pillar 51.
The first molding layer 60 and the top molding layer 62 are both located on the side of the package substrate 10 away from the substrate lower surface 12.
That is, at this time, the first molding layer 60 is located above the second dam 42 and inside the through hole 13, the first molding layer 60 covers all the open areas around the functional chip 30 and the inner area of the through hole 13, and the top molding layer 62 covers the exposed first molding layer 60 and the second upper redistribution layer 5312.
The first plastic layer 60 and the top plastic layer 62 may be EMC (Epoxy Molding Compound) plastic layers, and since the cofferdam 40 is utilized in this embodiment to block external substances from entering the cavity S, it is not necessary to consider whether the first plastic layer 60 and the top plastic layer 62 affect the protection area in the cavity S due to material problems, and thus the selection range of the materials of the first plastic layer 60 and the top plastic layer 62 is greatly enlarged, and further, the selection of specific plastic materials can be avoided, the plastic packaging process window is greatly widened, and the cost is effectively reduced.
In the present embodiment, the first upper surface 21 of the filter chip 20 is flush with the substrate upper surface 11, and the second molding layer 61 is provided in the gap between the filter chip 20 and the chamber 101, the substrate lower surface 12, and the first lower surface 22.
That is, the third plating layer 5323 is substantially located under the second molding layer 61, and the third insulating layer 72 is also substantially located under the second molding layer 61, and further description of the second molding layer 61 will be omitted herein with reference to the description of the first molding layer 60.
Here, by the arrangement of the second molding layer 61, on the one hand, the thickness difference between the filter chip 20 and the package substrate 10 can be compensated, so that the first upper surface 21 is flush with the substrate upper surface 11, so that the subsequent formation of the structures of the first insulating layer 70, the third insulating layer 72, and the like is facilitated; on the other hand, the second molding layer 61 may function to protect the filter chip 20 and fix the relative positions of the filter chip 20 and the chamber 101.
An embodiment of the present invention further provides a method for manufacturing the package structure 100, and the method for manufacturing the package structure 100 includes the following steps in combination with the description of the package structure 100 and fig. 5, 6a to 6 z-19:
s1: referring to fig. 6a, a package substrate 10 is provided, which has a substrate upper surface 11 and a substrate lower surface 12 disposed opposite to each other;
S2: referring to fig. 6b, a chamber 101 is formed on the package substrate 10;
s3: referring to fig. 6c, a filter chip 20 is provided, the filter chip 20 has a first upper surface 21 and a first lower surface 22 disposed opposite to each other, the first upper surface 21 has a plurality of first electrodes 211;
s4: referring to fig. 6d to 6j, the filter chip 20 is loaded into the chamber 101 with the first upper surface 21 on the same side as the substrate upper surface 11;
the step S4 is specifically as follows:
referring to fig. 6d, a temporary bonding board 90 is provided;
referring to fig. 6e, the upper substrate surface 11 of the package substrate 10 is bonded to the temporary bonding board 90;
referring to fig. 6f, the filter chip 20 is loaded into the chamber 101 with the first upper surface 21 on the same side as the substrate upper surface 11;
here, the first upper surface 21 is also bonded to the temporary bonding board 90, so that the first upper surface 21 can be flush with the substrate upper surface 11.
Referring to fig. 6g, a second molding layer 61 is formed to cover the gap between the filter chip 20 and the cavity 101, the lower surface 12 of the substrate, and the first lower surface 22;
referring to fig. 6h, temporary bonding board 90 is removed;
referring to fig. 6i, the package substrate 10 is inverted.
Referring to fig. 6j, a plurality of through holes 13 are formed on the package substrate 10, and the through holes 13 penetrate through the second plastic layer 61.
S5: referring to fig. 6k to 6v, a first interconnection structure is formed on the package substrate 10, and the first interconnection structure conducts the first electrode 211;
The step S5 is specifically as follows:
referring to fig. 6k to 6n, a first plating layer 5321 is formed on the upper surface 11 of the substrate, a second plating layer 5322 is formed on the inner wall of the through hole 13, and a third plating layer 5323 is formed under the second molding layer 61;
the method comprises the following steps:
referring to fig. 6k, a first photoresist layer 81 and a second photoresist layer 82 are formed above the upper surface 11 of the substrate and below the second molding layer 61, respectively;
referring to fig. 6l, a first opening 811 is formed by exposing and developing the first photoresist layer 81, the first opening 811 exposes the through hole 13 and the upper surface 11 of the substrate, a second opening 821 is formed by exposing and developing the second photoresist layer 82, and the second opening 821 exposes the through hole 13 and the second molding layer 61;
referring to fig. 6m, a first plating layer 5321 is formed on the exposed upper surface 11 of the substrate, a second plating layer 5322 is formed on the exposed inner wall of the through hole 13, and a third plating layer 5323 is formed on the exposed second molding layer 61;
referring to fig. 6n, the first photoresist layer 81 and the second photoresist layer 82 are removed.
Referring to fig. 6o, a first insulating layer 70 is disposed on the upper surface 11 of the substrate;
referring to fig. 6p to 6t, a first upper re-wiring layer 5311 is formed over the first insulating layer 70 to conduct the first electrode 211 and the first plating layer 5321 through the hole on the first insulating layer 70;
The method comprises the following steps:
referring to fig. 6p, a first hole 701 is formed by exposing and developing the first insulating layer 70, wherein the first hole 701 exposes the first electrode 211, the through hole 13, the first plating layer 5321 and the protection region, the protection region is located on the first upper surface 21, and the protection region is located on the inner sides of the first electrodes 211;
referring to fig. 6q, a third photoresist layer 83 is formed over the first insulating layer 70;
referring to fig. 6r, a third opening 831 is formed by exposing and developing the third photoresist layer 83, and the third opening 831 exposes the first electrode 211, the first plating layer 5321, and the first insulating layer 70;
referring to fig. 6s, a first upper redistribution layer 5311 is formed in the third opening 831;
referring to fig. 6t, the third photoresist layer 83 is removed.
Referring to fig. 6u and 6v, a second insulating layer 71 is disposed above the first insulating layer 70, the first upper rerouting layer 5311 and the protection area, the first insulating layer 70 and the second insulating layer 71 cooperate to form a dam 40, the dam 40 includes a first dam 41 and a second dam 42, the first dam 41 is located at the periphery of the cavity S, the outer edge of the second dam 42 is flush with the outer edge of the package substrate 10, and the second dam 42 exposes the through hole 13;
the method comprises the following steps:
referring to fig. 6u, a second insulating layer 71 is disposed over the first insulating layer 70, the first upper redistribution layer 5311, and the protection region;
Referring to fig. 6v, a second hole 711 is formed by exposing and developing the second insulating layer 71, the second hole 711 exposes the through hole 13 and the protection area, the first insulating layer 70 and the second insulating layer 71 cooperate to form a dam 40, the dam 40 includes a first dam 41 and a second dam 42, the first dam 41 is located at the periphery of the protection area, the outer edge of the second dam 42 is flush with the outer edge of the package substrate 10, and the second dam 42 exposes the through hole 13.
The dam 40 may include a third dam 45 connecting the first dam 41 and the second dam 42, that is, the dam 40 may be formed on the upper surface 11 of the substrate except for the areas corresponding to the cavity S and the through hole 13.
In addition, since the individual package substrate 10 can be formed by dividing a wafer-level large substrate, when the cofferdam 40 is formed, a plurality of cofferdams 40 can be directly formed on the large substrate, and then dividing the large substrate to obtain a single package substrate 10 with a single cofferdam 40, the packaging efficiency can be greatly improved, and of course, the cofferdam 40 can also be formed on the functional chip 30.
S6: referring to fig. 6w, a functional chip 30 is provided, the functional chip 30 has a second upper surface 31 and a second lower surface 32 disposed opposite to each other, and the second upper surface 31 has a plurality of second electrodes 311;
S7: referring to fig. 6x to fig. 6z-16, the functional chip 30 is mounted above the package substrate 10, and the second lower surface 32 is disposed opposite to the upper surface 11 of the substrate, and forms a second interconnection structure for conducting the second electrode 311 and the first interconnection structure through the hole;
s8: referring to fig. 6z-17 to 6z-19, a third interconnect structure is formed that conducts the external pin 121 and the first interconnect structure.
The steps S7 and S8 are specifically as follows:
referring to fig. 6x to 6z-1, a metal pillar 51 is formed over the second electrode 311;
the method comprises the following steps:
referring to fig. 6x, a fourth photoresist layer 84 is formed on the second upper surface 31;
referring to fig. 6y, a fourth opening 841 is formed by exposing and developing the fourth photoresist layer 84, and the fourth opening 841 exposes the second electrode 311;
referring to fig. 6z, metal posts 51 are formed in fourth openings 841;
referring to fig. 6z-1, the fourth photoresist layer 84 is removed.
Referring to fig. 6z-2, the functional chip 30 is mounted above the package substrate 10, the second lower surface 32 is disposed opposite to the substrate upper surface 11, and the first dam 41, the second lower surface 32, and the first upper surface 21 cooperate with each other to define a cavity S corresponding to the protection area.
Referring to fig. 6z-3, a first molding layer 60 is formed on a side of the package substrate 10 away from the substrate lower surface 12, the first molding layer 60 simultaneously covers the exposed upper surface area of the second dam 42, the functional chip 30 and the metal pillars 51, and the first molding layer 60 fills the through holes 13;
Referring to fig. 6z-4, the first molding layer 60 is polished to expose the metal posts 51;
referring to fig. 6z-5 to fig. 6z-9, a second upper re-wiring layer 5312 is formed on the first molding layer 60 to pass through the holes on the first molding layer 60 and the second insulating layer 71 to conduct the first upper re-wiring layer 5311, and the second upper re-wiring layer 5312 conducts the second electrode 311;
the method comprises the following steps:
referring to fig. 6z-5, a recess 44 is formed in the first molding layer 60 and the second insulating layer 71 and exposes the first upper redistribution layer 5311;
referring to fig. 6z-6, a fifth temporary photoresist film 85 is formed over the first molding layer 60;
referring to fig. 6z-7, a fifth opening 851 is formed by exposing and developing the fifth photoresist layer 85, and the fifth opening 851 exposes the recess 44 and the first molding layer 60;
referring to fig. 6z-8, a second upper re-wiring layer 5312 is formed along the inner wall of the recess 44, and the second upper re-wiring layer 5312 extends above the first molding layer 60 to conduct the second electrode 311;
referring to fig. 6z-9, the fifth temporary photoresist film 85 is removed.
Referring to fig. 6z-10, a top molding layer 62 is formed over the first molding layer 60 and the second upper redistribution layer 5312;
referring to fig. 6z-11, a third insulating layer 72 is formed under the third plating layer 5323 and the second molding layer 61;
referring to fig. 6z-12 to 6z-16, a lower rerouting layer 533 is formed under the third insulating layer 72 to pass through the hole on the third insulating layer 72 to pass through the third plating layer 5323;
The method comprises the following steps:
referring to fig. 6z-12, a third hole 721 is formed in the third insulating layer 72 by exposure and development, and the third plating layer 5323 is exposed to the third hole 721;
referring to fig. 6z-13, a fifth photoresist layer 85 is formed under the third insulating layer 72;
referring to fig. 6z-14, a fifth opening 851 is formed by exposing and developing the fifth photoresist layer 85, and the third opening 721 and the third insulating layer 72 are exposed by the fifth opening 851;
referring to fig. 6z-15, a lower redistribution layer 533 is formed within the fifth opening 851;
referring to fig. 6z-16, the fifth photoresist layer 85 is removed.
Referring to fig. 6z-17 and fig. 6z-18, a fourth insulating layer 73 is formed to cover the third insulating layer 72 and the lower rerouting layer 533, the fourth insulating layer 73 exposing the lower rerouting layer 533;
the method comprises the following steps:
referring to fig. 6z-17, a fourth insulating layer 73 is formed under the lower rerouting layer 533 and the third insulating layer 72;
referring to fig. 6z-18, a fourth hole 731 is formed in the fourth insulating layer 73 by exposure and development, and the fourth hole 731 exposes the lower re-wiring layer 533.
Referring to fig. 6z-19, the ball grid array 121 is formed in the exposed lower re-wiring layer 533, i.e., the ball grid array 121 is formed in the fourth hole 731.
Other descriptions of the manufacturing method of the package structure 100 in this embodiment may refer to the descriptions of the package structure 100 described above, and will not be repeated here.
The dam 40 of the present invention is located on the inner side and the outer side of the first electrode 211, and the outer side edge of the second dam 42 is flush with the outer side edge of the package substrate 10, in other embodiments, the dam 40 may be located on the inner side of the first electrode 211, or the outer side edge of the second dam 42 is flush with the outer side edge of the functional chip 30, or the outer side edge of the second dam 42 is located between the outer side edge of the functional chip 30 and the outer side edge of the package substrate 10, and so on.
In summary, the present embodiment can effectively avoid the influence of the external substances entering the cavity S during the manufacturing process of the package structure or the use process of the package structure on the normal use of the filter chip 20 by arranging the cofferdam 40 to form the cavity S, thereby improving the overall performance of the package structure 100.
In addition, the present embodiment encapsulates two different chips (the filter chip 20 and the functional chip 30) on the same package substrate 10 by using the packaging technology, so that high integration of multiple chips can be realized, the utilization rate of the package substrate 10 can be improved, and further, the miniaturization of the package structure 100 can be realized.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (6)
1. A package structure with a built-in filter chip and holes, comprising:
the packaging substrate is provided with a cavity, and the cavity penetrates through the packaging substrate;
the filter chip is arranged in the cavity and provided with a first upper surface and a first lower surface which are oppositely arranged, the first upper surface and the upper surface of the substrate are positioned on the same side, and the first upper surface is provided with a plurality of first electrodes;
the functional chip is arranged above the packaging substrate and is provided with a second upper surface and a second lower surface which are oppositely arranged, the second lower surface and the upper surface of the substrate are arranged face to face, and the second upper surface is provided with a plurality of second electrodes;
a plurality of interconnection structures, which are communicated with a plurality of first electrodes and a plurality of second electrodes through holes;
One side of the lower surface of the substrate is provided with a plurality of external pins, the packaging substrate is provided with a plurality of through holes, and the interconnection structure conducts the first electrode, the second electrode and the external pins through the through holes;
the interconnection structure comprises a metal column and a plating layer structure, the metal column is communicated with the second electrode, the plating layer structure is communicated with the first electrode and the metal column, and the plating layer structure extends to the lower side of the packaging substrate through the through hole to be communicated with the external pin;
the electroplating layer structure comprises an upper rewiring layer, a middle wiring layer and a lower rewiring layer which are communicated with each other, wherein the upper rewiring layer is positioned above the packaging substrate and is used for conducting the first electrode and the second electrode, the lower rewiring layer is positioned below the packaging substrate and is used for conducting the external pin, the middle wiring layer comprises a first electroplating layer, a second electroplating layer and a third electroplating layer, the first electroplating layer is positioned on the upper surface of the substrate, the second electroplating layer is positioned on the inner wall of the through hole, the third electroplating layer is positioned on the lower surface of the substrate, the first electroplating layer is connected with the upper rewiring layer, and the third electroplating layer is connected with the lower rewiring layer;
The packaging structure comprises a first insulating layer, a first upper rerouting layer, a second insulating layer and a second upper rerouting layer, wherein the first insulating layer is positioned on the upper surface of the substrate, above the first upper surface, the first upper rerouting layer is used for conducting the first electroplated layer and the first electrode through a hole in the first insulating layer, the second insulating layer is used for connecting the first insulating layer and the second lower surface, and the second upper rerouting layer is used for conducting the first upper rerouting layer through a hole in the second insulating layer, and the second upper rerouting layer is used for conducting the metal column;
the first insulating layer and the second insulating layer are matched to form a cofferdam, the cofferdam is matched with the second lower surface and the first upper surface to form a cavity, the cofferdam comprises a first cofferdam positioned at the inner sides of the first electrodes and a second cofferdam positioned at the outer sides of the first electrodes, and the first cofferdam is matched with the second lower surface and the first upper surface to form a cavity;
the packaging structure further comprises a first plastic layer and a top plastic layer which are positioned on one side, far away from the lower surface of the substrate, of the packaging substrate, wherein the first plastic layer is used for coating the upper surface area, exposed out of the second insulating layer, of the functional chip and the metal column, the first plastic layer is used for filling the through hole, the second upper rewiring layer is used for conducting the first upper rewiring layer through holes in the first plastic layer and the second insulating layer, the second upper rewiring layer is extended to the upper surface of the first plastic layer and is used for conducting the metal column, and the top plastic layer is used for coating the first plastic layer and the second upper rewiring layer.
2. The package structure of claim 1, wherein the through holes are spaced apart from the second electrodes.
3. The package structure of claim 1, wherein the second dam extends in a direction away from the first dam until an outer edge of the second dam is flush with an outer edge of the package substrate, and the second dam exposes the through hole.
4. The package structure of claim 1, wherein the package structure comprises a third insulating layer covering the third plating layer and the lower surface of the substrate, a lower redistribution layer passing through the hole on the third insulating layer to conduct the third plating layer and extending toward the lower surface of the third insulating layer, and a fourth insulating layer covering the third insulating layer and the lower redistribution layer, wherein the external leads are connected to the lower redistribution layer, and the fourth insulating layer exposes the external leads.
5. The package structure of claim 1, wherein a gap between the filter chip and the cavity, the substrate lower surface, and the first lower surface are provided with a second molding layer, and the first upper surface is flush with the substrate upper surface.
6. The manufacturing method of the packaging structure with the embedded filter chip and the holes is characterized by comprising the following steps:
s1: providing a packaging substrate, wherein the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged;
s2: forming a cavity on the packaging substrate;
s3: providing a filter chip, wherein the filter chip is provided with a first upper surface and a first lower surface which are oppositely arranged, and the first upper surface is provided with a plurality of first electrodes;
s4: loading the filter chip into the chamber, the first upper surface being on the same side as the substrate upper surface;
s5: forming a first interconnection structure on the packaging substrate, wherein the first interconnection structure conducts the first electrode;
s6: providing a functional chip, wherein the functional chip is provided with a second upper surface and a second lower surface which are oppositely arranged, and the second upper surface is provided with a plurality of second electrodes;
s7: the functional chip is loaded above the packaging substrate, the second lower surface and the upper surface of the substrate are arranged face to face, and a second interconnection structure for conducting the second electrode and the first interconnection structure through the hole is formed;
s8: forming a third interconnection structure for conducting the external pins and the first interconnection structure, wherein step S4 specifically includes:
Providing a temporary bonding plate;
bonding the upper surface of the substrate of the packaging substrate to the temporary bonding plate;
loading the filter chip into the chamber, the first upper surface being on the same side as the substrate upper surface;
forming a second plastic layer which covers the gap between the filter chip and the cavity, the lower surface of the substrate and the first lower surface;
removing the temporary bonding plate;
inverting the package substrate;
forming a plurality of through holes on the packaging substrate, wherein the through holes penetrate through the second plastic sealing layer;
the step S5 specifically comprises the following steps:
forming a first electroplated layer on the upper surface of the substrate, forming a second electroplated layer on the inner wall of the through hole, and forming a third electroplated layer below the second plastic sealing layer;
a first insulating layer is arranged on the upper surface of the substrate;
exposing and developing the first insulating layer to form a first hole, wherein the first hole exposes the first electrode, the through hole, the first electroplated layer and the protection area, the protection area is positioned on the first upper surface, and the protection area is positioned on the inner sides of the first electrodes;
forming a third photoresist layer over the first insulating layer;
exposing and developing the third photoresist layer to form a third opening, wherein the third opening exposes the first electrode, the first electroplated layer and the first insulating layer;
Forming a first upper rewiring layer in the third opening;
removing the third photoresist layer;
a second insulating layer is arranged above the first insulating layer, the first upper rewiring layer and the protection area;
exposing and developing the second insulating layer to form a second hole, wherein the second hole exposes the through hole and the protection area, the first insulating layer and the second insulating layer are matched to form a cofferdam, the cofferdam comprises a first cofferdam and a second cofferdam, the first cofferdam is positioned at the periphery of the protection area, the outer side edge of the second cofferdam is flush with the outer side edge of the packaging substrate, and the second cofferdam exposes the through hole;
the steps S7 and S8 specifically include:
forming a metal column above the second electrode;
the functional chip is loaded above the packaging substrate, the second lower surface and the upper surface of the substrate are arranged face to face, and the first cofferdam, the second lower surface and the first upper surface are mutually matched to enclose a cavity corresponding to the protection area;
forming a first plastic sealing layer on one side of the packaging substrate, which is far away from the lower surface of the substrate, wherein the first plastic sealing layer simultaneously covers the upper surface area, the functional chip and the metal column, which are exposed outside the second cofferdam, and the first plastic sealing layer fills the through hole;
Grinding the first plastic sealing layer to expose the metal posts;
forming a second upper rewiring layer on the first plastic sealing layer, wherein the second upper rewiring layer is communicated with the first upper rewiring layer through holes in the first plastic sealing layer and the second insulating layer, and the second upper rewiring layer is communicated with the second electrode;
forming a top molding layer over the first molding layer and the second upper rewiring layer;
forming a third insulating layer below the third electroplated layer and the second plastic sealing layer;
forming a lower rewiring layer below the third insulating layer, wherein the lower rewiring layer is communicated with the third electroplated layer through a hole in the third insulating layer;
forming a fourth insulating layer covering the third insulating layer and the lower rewiring layer, wherein the fourth insulating layer exposes the lower rewiring layer;
the exposed lower rewiring layer forms a ball grid array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810911108.4A CN108831876B (en) | 2018-08-10 | 2018-08-10 | Packaging structure embedded with filter chip and provided with holes and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810911108.4A CN108831876B (en) | 2018-08-10 | 2018-08-10 | Packaging structure embedded with filter chip and provided with holes and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108831876A CN108831876A (en) | 2018-11-16 |
| CN108831876B true CN108831876B (en) | 2024-03-08 |
Family
ID=64153237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810911108.4A Active CN108831876B (en) | 2018-08-10 | 2018-08-10 | Packaging structure embedded with filter chip and provided with holes and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108831876B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800660A (en) * | 2011-05-26 | 2012-11-28 | 英飞凌科技股份有限公司 | Module and method of manufacturing a module |
| JP2015146333A (en) * | 2014-01-31 | 2015-08-13 | 太陽誘電株式会社 | module |
| CN106449554A (en) * | 2016-12-06 | 2017-02-22 | 苏州源戍微电子科技有限公司 | Chip embedded packaging structure with sealed cavity and manufacturing method of structure |
| CN208923126U (en) * | 2018-08-10 | 2019-05-31 | 付伟 | The encapsulation modular structure with filter chip for forming cavity is stacked by chip |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3937840B2 (en) * | 2002-01-10 | 2007-06-27 | 株式会社日立製作所 | High frequency module |
| US20080174008A1 (en) * | 2007-01-18 | 2008-07-24 | Wen-Kun Yang | Structure of Memory Card and the Method of the Same |
| SG148901A1 (en) * | 2007-07-09 | 2009-01-29 | Micron Technology Inc | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
| US8237257B2 (en) * | 2008-09-25 | 2012-08-07 | King Dragon International Inc. | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
| US8878360B2 (en) * | 2012-07-13 | 2014-11-04 | Intel Mobile Communications GmbH | Stacked fan-out semiconductor chip |
| KR101634067B1 (en) * | 2014-10-01 | 2016-06-30 | 주식회사 네패스 | Semiconductor package and method of manufacturing the same |
-
2018
- 2018-08-10 CN CN201810911108.4A patent/CN108831876B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800660A (en) * | 2011-05-26 | 2012-11-28 | 英飞凌科技股份有限公司 | Module and method of manufacturing a module |
| JP2015146333A (en) * | 2014-01-31 | 2015-08-13 | 太陽誘電株式会社 | module |
| CN106449554A (en) * | 2016-12-06 | 2017-02-22 | 苏州源戍微电子科技有限公司 | Chip embedded packaging structure with sealed cavity and manufacturing method of structure |
| CN208923126U (en) * | 2018-08-10 | 2019-05-31 | 付伟 | The encapsulation modular structure with filter chip for forming cavity is stacked by chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108831876A (en) | 2018-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101963292B1 (en) | Fan-out semiconductor package | |
| KR102005830B1 (en) | Flip-chip, face-up and face-down centerbond memory wirebond assemblies | |
| US8592952B2 (en) | Semiconductor chip and semiconductor package with stack chip structure | |
| US8378478B2 (en) | Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts | |
| KR101653856B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN109003961B (en) | 3D system integrated structure and manufacturing method thereof | |
| CN108711570B (en) | Multi-chip packaging structure of integrated chip packaging structure and manufacturing method thereof | |
| KR101982056B1 (en) | Fan-out semiconductor package module | |
| US20140256089A1 (en) | Stacked semiconductor packages | |
| KR20080038035A (en) | Semiconductor package and stacked layer type semiconductor package | |
| KR20190005697A (en) | Fan-out semiconductor package module | |
| CN111081646B (en) | Stack packaging structure and manufacturing method thereof | |
| KR20120062366A (en) | Method for manufacturing multi-chip package | |
| JP2007150154A (en) | Semiconductor device | |
| US9917073B2 (en) | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package | |
| KR20190090180A (en) | Electronic component package | |
| KR101653563B1 (en) | Stack type semiconductor package and method for manufacturing the same | |
| CN109103173B (en) | Package structure with embedded filter chip and upper pins and manufacturing method thereof | |
| CN109087911B (en) | Multi-chip packaging structure with functional chip accommodating cavity and manufacturing method thereof | |
| CN108831881B (en) | Vertically stacked multi-chip packaging structure with cavity and manufacturing method thereof | |
| CN108766956B (en) | Multi-chip packaging structure with multiple chambers and manufacturing method thereof | |
| US20040245651A1 (en) | Semiconductor device and method for fabricating the same | |
| KR20200058918A (en) | Fan-out semiconductor package | |
| CN109087909B (en) | Multi-cavity packaging structure with metal posts and manufacturing method thereof | |
| CN108807350B (en) | Multi-cavity packaging structure with amplifier chip electrode arranged outside and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200612 Address after: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Applicant after: Zhejiang Rongcheng Semiconductor Co.,Ltd. Address before: 215123 Jiangsu city Suzhou Industrial Park 99 Jinji Hu Road 99 Suzhou Nancheng NW-05 building 301 Applicant before: Fu Wei |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |