CN108829633A - A kind of multifunctional core core based on EPLD - Google Patents
A kind of multifunctional core core based on EPLD Download PDFInfo
- Publication number
- CN108829633A CN108829633A CN201811032324.8A CN201811032324A CN108829633A CN 108829633 A CN108829633 A CN 108829633A CN 201811032324 A CN201811032324 A CN 201811032324A CN 108829633 A CN108829633 A CN 108829633A
- Authority
- CN
- China
- Prior art keywords
- epld
- bottom plate
- transmission circuit
- core
- data transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 38
- 238000012545 processing Methods 0.000 abstract description 5
- 238000012544 monitoring process Methods 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 1
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Programmable Controllers (AREA)
Abstract
The invention provides a kind of multifunctional core core based on EPLD, including core board and bottom plate, and core board and bottom plate couple, and the core board is equipped with EPLD erasable programmable logical device and CPU, CPU and EPLD erasable programmable logical device data connection；The bottom plate is driveway controller bottom plate or RFID reader bottom plate；The erasable logical device of EPLD respectively on driveway controller bottom plate relay and PSAM card couple；EPLD also respectively on RFID reader bottom plate FPGA and security module connect；Core board where the present invention mainly makes EPLD not only can control bottom plate and use as driveway controller, but also can control bottom plate and use as RFID reader.EPLD logic is mainly responsible for veneer decoding, bus driver, the demultiplexing of data address multiplexing line, reset control, boot downloading, house dog control, interrupt processing, board version and relevant control in external device interface, FLASH and status monitoring, lighting control etc..
Description
Technical field
The invention belongs to design of electronic products field, more particularly, to a kind of multi-functional board based on EPLD.
Background technique
Radio Frequency Identification Technology (RFID) belongs to the technology scope of automatic identification, is the skill to grow up in recent years
Art.It is widely used in the various fields such as industrial automation, business automation, communications and transportation control management, such as automobile, train are handed over
Logical monitoring, reader is the important component of RFID；And driveway controller has at stronger business as front-end control facilities
Reason ability.Both products play critically important effect in electronic license plate industry.
Summary of the invention
In view of this, the invention be directed to one kind can by change EPLD pin state come adaptive two kinds of bottoms
The multifunctional core core based on EPLD of plate.
In order to achieve the above objectives, the technical solution of the invention is realized in：
A kind of multifunctional core core based on EPLD is coupled with bottom plate, and it is erasable that the core board is equipped with CPU, EPLD
Except programmed logic device, interior data transmission circuit and outer data transmission circuit；The CPU can by interior data transmission circuit and EPLD
Wipe programmed logic device connection；The EPLD erasable programmable logical device passes through outer data transmission circuit and external bottom
Plate connection, is additionally provided with two switching pins on the EPLD erasable programmable logical device, on two switching pins
It is respectively equipped with a pull down resistor, switching pin is used to switch the working condition of EPLD.
Further, the bottom plate is driveway controller bottom plate, and driveway controller bottom plate is equipped with relay, GPIO interface
With PSAM card.
Further, the CPU in the core board is connect by interior data transmission circuit with EPLD erasable programmable logic device,
EPLD erasable programmable logic device passes through relay, GPIO the and PSAM card on outer data transmission circuit and driveway controller bottom plate
Communication connection；The interior data transmission circuit is IFC bus, and the outer data transmission circuit is 220pin COMe interface.
Further, the bottom plate is RFID reader bottom plate, and RFID reader bottom plate is equipped with security module and FPGA.
Further, the CPU in the core board is connect by interior data transmission circuit with EPLD erasable programmable logic device,
EPLD erasable programmable logic device by outer data transmission circuit on driveway controller bottom plate FPGA and security module connect；
The interior data transmission circuit is IFC bus and SPI serial line interface, and the outer data transmission circuit is 220pin COMe interface.
Further, the SPI signal input voltage of the EPLD erasable programmable logic device is 1.8V, and output voltage is
3.3V。
Compared with the existing technology, a kind of multifunctional core core based on EPLD described in the invention has following excellent
Gesture：
Core board where the present invention mainly makes EPLD not only can control bottom plate and use as driveway controller, but also can control
Bottom plate processed is used as RFID reader.EPLD logic is mainly responsible for veneer decoding, bus driver, the solution of data address multiplexing line
Multiplexing, reset control, the boot downloading in external device interface, FLASH, house dog control, interrupt processing, board version and
Relevant control and status monitoring, lighting control etc..Using mini system as daughter board form, by patching different bottom plates, and
Switch the corresponding code of EPLD, cutting for two type both may be implemented and replaced.This seed plate form make to control it is more flexible, from long-range
Angle also saves the cost of product.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide to further understand the invention, present invention wound
The illustrative embodiments and their description made are used to explain the present invention creation, do not constitute the improper restriction to the invention.?
In attached drawing：
Fig. 1 is that driveway controller connected mode schematic diagram is used for described in the invention embodiment；
Fig. 2 is that RFID reader connected mode schematic diagram is used for described in the invention embodiment；
Fig. 3 is EPLD erasable programmable logic device pin schematic diagram；
Fig. 4 is EPLD erasable programmable logical device module diagram.
Specific embodiment
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the invention can
To be combined with each other.
In the description of the invention, it is to be understood that term " center ", " longitudinal direction ", " transverse direction ", "upper", "lower",
The orientation or positional relationship of the instructions such as "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description the invention and simplifies description, rather than indicate
Or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore cannot understand
For the limitation to the invention.In addition, term " first ", " second " etc. are used for description purposes only, and should not be understood as indicating
Or it implies relative importance or implicitly indicates the quantity of indicated technical characteristic." first ", " second " etc. are defined as a result,
Feature can explicitly or implicitly include one or more of the features.In the description of the invention, unless separately
It is described, the meaning of " plurality " is two or more.
In the description of the invention, it should be noted that unless otherwise clearly defined and limited, term " peace
Dress ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integrally
Connection；It can be mechanical connection, be also possible to be electrically connected；Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection inside two elements.For the ordinary skill in the art, on being understood by concrete condition
State concrete meaning of the term in the invention.
The present invention will be described in detail below with reference to the accompanying drawings and embodiments creates.
A kind of multifunctional core core based on EPLD is coupled with bottom plate, and it is erasable that the core board is equipped with CPU, EPLD
Except programmed logic device, interior data transmission circuit and outer data transmission circuit；The CPU can by interior data transmission circuit and EPLD
Wipe programmed logic device connection；The EPLD erasable programmable logical device passes through outer data transmission circuit and external bottom
Plate connection, is additionally provided with two switching pins on the EPLD erasable programmable logical device, on two switching pins
It is respectively equipped with a pull down resistor, switching pin is used to switch the working condition of EPLD.
The bottom plate is driveway controller bottom plate, and driveway controller bottom plate is equipped with relay, GPIO interface and PSAM card.
CPU in the core board is connect by interior data transmission circuit with EPLD erasable programmable logic device, and EPLD can
Programmed logic device is wiped to connect by relay, GPIO the and PSAM cartoon letters on outer data transmission circuit and driveway controller bottom plate
It connects；The interior data transmission circuit is IFC bus, and the outer data transmission circuit is 220pin COMe interface.
The bottom plate is RFID reader bottom plate, and RFID reader bottom plate is equipped with security module and FPGA.
CPU in the core board is connect by interior data transmission circuit with EPLD erasable programmable logic device, and EPLD can
Erasing programmed logic device by outer data transmission circuit on driveway controller bottom plate FPGA and security module connect；It is described
Interior data transmission circuit is IFC bus and SPI serial line interface, and the outer data transmission circuit is 220pin COMe interface.
The SPI signal input voltage of the EPLD erasable programmable logic device is 1.8V, output voltage 3.3V.The present invention
Core board and bottom plate between use the COMe standard interface of 220Pin, the pin of the connector, which defines, to be fixed, and interface is richer
Richness, supply voltage value may conform to the requirement of two products, and NC pin of having more than needed is more, can define respectively and distinguish two kinds of products
Signal, other general pins can share.
Flexibly, each pin can be customized according to demand, controls bottom plate, this hair downwards by inter-board interface for present invention work
One engineering of Code synthesis of two kinds of products need to be used the different function in engineering by two pins difference of EPLD by bright EPLD
It can block.
EPLD also needs to realize the level conversion function of signal, because the different BANK of EPLD can define voltage respectively
Value, therefore the CPU signal come out can be converted into the level of bottom plate needs.
In addition, the voltage and power consumption of on board supply will meet the needs of two products；Daughter board structure size will meet two
The demand of product cannot interfere with other components.
When the present invention is used for driveway controller：As shown in Figure 1, being mainly one on bottom plate in addition to other common pins
A little peripheral interfaces, thus the main function of EPLD be with CPU with IFC bus form communication, and by configure bus register come
The relay and PSAM card of bottom plate are controlled, this part is mainly the EPLD CPU_interface module in corresponding diagram 1.
When the present invention is used for reader：As shown in Fig. 2, on bottom plate more than driveway controller FPGA, CPU and FPGA
It is still communicated by IFC bus form, so EPLD only does transparent transmission processing at this time, and using some GPIO of CPU as FPGA
The configuration pin of starting.In addition reader also needs security module, since the CPU selected in the present invention the SPI signal issued is
1.8V, but 3.3V is needed in security module application, so EPLD needs to do level conversion processing.
The logic switch pin of two kinds of products：As shown in figure 3, there are two pin EPLD_ in EPLD<0>And EPLD_<1
>, the two pins add pull down resistor respectively, as control EPLD_<0>And EPLD_<1>When being 01, the program of EPLD supports vehicle
Track control unit version, if EPLD_<0>And EPLD_<1>When being 11, the program of EPLD supports reader version.
EPLD module of the present invention：As shown in Figure 1, including, Clk_gen module provides all for entire EPLD
Timing signal, it generates all timing signals from pp1us (mono- pulse of 1us) to pp1024ms (mono- pulse of about 1s), and
And the square-wave signal of different frequency is generated as needed.Reset_ctl module controls entire veneer and the reset of EPLD.Cpu_
Interface module provides the decoding and control function of the read-write capability of all registers, bus.Fpga_config module
The logic downloading data that in CPU_interface module, CPU write goes out only is subjected to parallel-serial conversion, is sent after generating DCLK clock
Out.Int_controller is interruption control module, under the control of interrupt mask register, is produced to the interrupt source of external world's input
Raw CPU interrupt request singal, and interrupt status register is provided and is read for CPU.Flash and LPC module main function be in order to
Programming EPLD and BOOT file uses.The module sends and receivees synch command and data, Neng Goushi from a serial line interface
Existing FLASH downloading is used for simple debugging and production programming interface.Pwm_ctrl module, when which is breath light control
Sequence.Psam module is control signal of the system board to bottom plate Psam card, it then follows Psam agreement, PSAM card by come interface with
EPLD carries out data transmission and receives, and then carries out data interaction with CPU after EPLD progress data processing.Relay in Fig. 1
Circuit is interacted by come and EPLD, and data are interacted further through EPLD and CPU, realizes the relay function of equipment.
Green portion is driveway controller use, and RED sector is that reader uses module.
Platform architecture of the present invention is more flexible：Daughter board can be replaced to replace to cut by cutting convenient for different product using daughter board framework
Platform and mini system can be distinguished low with version and high with version, the development cost of reduction later period new product；It controls more flexible：EPLD
It is more more flexible than CPU pin assignment, it is applying in driveway controller, is being mainly used to control peripheral interface, be applied to read
It is mainly used to do the distribution of bus when device；The connection of EPLD plate grade solves the problems, such as level conversion：Present CPU mostly uses low-voltage
Low power dissipation design, output level is lower, and if SPI is 1.8V output, but the level of most of driving chip is synchronous not yet, still for
Conventional voltage such as 3.3V.And the most pin number of electrical level transferring chip is few, package dimension is big, occupies substrate major part area.And
EPLD can solve the problems, such as level conversion；Save the cost：Mini system is made into the compatible two kinds of products of daughter board form, a plate multipotency
Mode can save research and development cost.
The foregoing is merely the preferred embodiments of the invention, are not intended to limit the invention creation, all at this
Within the spirit and principle of innovation and creation, any modification, equivalent replacement, improvement and so on should be included in the invention
Protection scope within.
Claims (6)
1. a kind of multifunctional core core based on EPLD is coupled with bottom plate, it is characterised in that：The core board be equipped with CPU,
EPLD erasable programmable logic device, interior data transmission circuit and outer data transmission circuit；The CPU passes through interior data transmission circuit
It is connect with EPLD erasable programmable logical device；The EPLD erasable programmable logical device by outer data transmission circuit with
External bottom plate connects, and is additionally provided with two switching pins on the EPLD erasable programmable logical device, described two are cut
It changes on pin and is respectively equipped with a pull down resistor, switching pin is used to switch the working condition of EPLD.
2. a kind of multifunctional core core based on EPLD according to claim 1, it is characterised in that：The bottom plate is lane
Controller bottom plate, driveway controller bottom plate are equipped with relay, GPIO interface and PSAM card.
3. a kind of multifunctional core core based on EPLD according to claim 2, it is characterised in that：In the core board
CPU is connect by interior data transmission circuit with EPLD erasable programmable logic device, and EPLD erasable programmable logic device passes through outer number
It is connect according to transmission circuit with relay, GPIO the and PSAM cartoon letters on driveway controller bottom plate；The interior data transmission circuit
For IFC bus, the outer data transmission circuit is 220pin COMe interface.
4. a kind of multifunctional core core based on EPLD according to claim 1, it is characterised in that：The bottom plate is RFID
Reader bottom plate, RFID reader bottom plate are equipped with security module and FPGA.
5. a kind of multifunctional core core based on EPLD according to claim 4, it is characterised in that：In the core board
CPU is connect by interior data transmission circuit with EPLD erasable programmable logic device, and EPLD erasable programmable logic device passes through outer number
According to transmission circuit on driveway controller bottom plate FPGA and security module connect；The interior data transmission circuit is IFC bus
With SPI serial line interface, the outer data transmission circuit is 220pin COMe interface.
6. a kind of multifunctional core core based on EPLD according to claim 5, it is characterised in that：The EPLD is erasable
The SPI signal input voltage of programmed logic device is 1.8V, output voltage 3.3V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811032324.8A CN108829633A (en) | 2018-09-05 | 2018-09-05 | A kind of multifunctional core core based on EPLD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811032324.8A CN108829633A (en) | 2018-09-05 | 2018-09-05 | A kind of multifunctional core core based on EPLD |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108829633A true CN108829633A (en) | 2018-11-16 |
Family
ID=64149520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811032324.8A Pending CN108829633A (en) | 2018-09-05 | 2018-09-05 | A kind of multifunctional core core based on EPLD |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108829633A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112099390A (en) * | 2020-07-27 | 2020-12-18 | 深圳市风云实业有限公司 | Multi-level peripheral control system and method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080000455A (en) * | 2006-06-27 | 2008-01-02 | 서울통신기술 주식회사 | Method and apparatus for multi-function combination board |
| CN101582688A (en) * | 2008-05-15 | 2009-11-18 | 中兴通讯股份有限公司 | Dynamic configuration circuit with FPGA loading mode |
| CN205334488U (en) * | 2015-12-21 | 2016-06-22 | 天津中兴智联科技有限公司 | Support reading ware of multiple cipher mode |
| CN205692167U (en) * | 2016-06-12 | 2016-11-16 | 成都傅立叶电子科技有限公司 | General purpose core core based on PowerPC framework central processing unit |
| CN205812033U (en) * | 2016-06-24 | 2016-12-14 | 成都傅立叶电子科技有限公司 | A kind of general purpose core core |
| CN108121687A (en) * | 2016-11-28 | 2018-06-05 | 沈阳新松机器人自动化股份有限公司 | Core board and board |
| CN208622095U (en) * | 2018-09-05 | 2019-03-19 | 天津中兴智联科技有限公司 | A kind of multifunctional core core based on EPLD |
-
2018
- 2018-09-05 CN CN201811032324.8A patent/CN108829633A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080000455A (en) * | 2006-06-27 | 2008-01-02 | 서울통신기술 주식회사 | Method and apparatus for multi-function combination board |
| CN101582688A (en) * | 2008-05-15 | 2009-11-18 | 中兴通讯股份有限公司 | Dynamic configuration circuit with FPGA loading mode |
| CN205334488U (en) * | 2015-12-21 | 2016-06-22 | 天津中兴智联科技有限公司 | Support reading ware of multiple cipher mode |
| CN205692167U (en) * | 2016-06-12 | 2016-11-16 | 成都傅立叶电子科技有限公司 | General purpose core core based on PowerPC framework central processing unit |
| CN205812033U (en) * | 2016-06-24 | 2016-12-14 | 成都傅立叶电子科技有限公司 | A kind of general purpose core core |
| CN108121687A (en) * | 2016-11-28 | 2018-06-05 | 沈阳新松机器人自动化股份有限公司 | Core board and board |
| CN208622095U (en) * | 2018-09-05 | 2019-03-19 | 天津中兴智联科技有限公司 | A kind of multifunctional core core based on EPLD |
Non-Patent Citations (1)
| Title |
|---|
| 饶志强: "《智慧城市停车系统工程研究》", 31 May 2016, 科学技术文献出版社, pages: 45 - 50 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112099390A (en) * | 2020-07-27 | 2020-12-18 | 深圳市风云实业有限公司 | Multi-level peripheral control system and method |
| CN112099390B (en) * | 2020-07-27 | 2022-04-12 | 深圳市风云实业有限公司 | Multi-level peripheral control system and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101604301B (en) | Use of bond option to alternate between pci configuration space | |
| CN101256544B (en) | Method, apparatus and system for expansion of inside integrated circuit bus | |
| US7209995B2 (en) | Efficient connection between modules of removable electronic circuit cards | |
| CN100395728C (en) | Single board read/writ system and method for information | |
| US20020103944A1 (en) | Arrangement with a microprocessor | |
| KR20070075102A (en) | Apparatus for cognizing memory | |
| CN101877070B (en) | Non-contact IC card reader-writer and card searching method thereof | |
| CN101571842A (en) | PCI integrated circuit board device used for ARINC429 communication | |
| CN108205393A (en) | For the system and method for the communication in semiconductor equipment | |
| CN101510184A (en) | Multichannel serial communications system and control method thereof | |
| CN103500154A (en) | Serial bus interface chip, serial bus transmission system and method | |
| US5465106A (en) | Generic driver interface card | |
| CN108829633A (en) | A kind of multifunctional core core based on EPLD | |
| CN105373511B (en) | A kind of device and method that can be communicated simultaneously with multiple optical modules | |
| CN208622095U (en) | A kind of multifunctional core core based on EPLD | |
| CN105118441A (en) | LED display screen control card for asynchronous control system | |
| US6886066B2 (en) | Method and apparatus for sharing signal pins on an interface between a system controller and peripheral integrated circuits | |
| CN111538689A (en) | Multi-channel PCIE (peripheral component interface express) adapter card with two heterogeneous ends | |
| CN205050537U (en) | LED asynchronous control ware | |
| JP2000181858A (en) | Universal asynchronous transmitter-receiver provided with ic card read interface, and ic card read system applied with the same | |
| CN204968201U (en) | LED asynchronous control ware | |
| CN202563497U (en) | Communication interface for Flash-Net animation game | |
| CN101213501A (en) | Memory card input/output apparatus and control method thereof | |
| CN101751115B (en) | Method for solving data transmission matching of DSP and low-speed output device | |
| EP1043662B1 (en) | Apparatus and method for reconfiguring the pin assignments of one or more functional circuits in a microcontroller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |