CN108807522B - N-type tunneling field effect transistor and manufacturing method thereof - Google Patents
N-type tunneling field effect transistor and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The invention discloses an N-type tunneling field effect transistor and a manufacturing method thereof, wherein the transistor comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a P-type source region formed on the semiconductor substrate and located at a first side of the channel region, the P-type source region having P+Type doping; an N-type drain region formed on the semiconductor substrate and located on a second side of the channel region opposite to the first side, the N-type drain region having N+Type doping; the grid electrode is arranged on the third side of the channel region, and a grid oxide layer is arranged between the grid electrode and the channel region; the isolation region is arranged at the region where the drain body junction between the channel region and the N-type drain region is located, the isolation region is filled with a preset isolation oxide, the isolation region is overlapped with the gate oxide layer, and the isolation region is used for isolating electrons between the N-type drain region and the channel region and avoiding tunneling at the region where the drain body junction is located.
Description
Technical Field
The invention relates to the technical field of integrated semiconductors, in particular to an N-type tunneling field effect transistor and a manufacturing method thereof.
Background
In the prior art, the development of the CMOS technology is always following moore's law, the size is continuously reduced in proportion, the integration level is continuously improved, the cost is continuously reduced, the performance of the integrated circuit is continuously improved, but the continuous reduction of the size of the CMOS device also brings a series of problems, and the problem of energy consumption is the first place. Because the reduction speed of the power supply voltage is far less than the reduction speed of the device size, the energy consumption density is inevitably greatly increased, and when the energy consumption density of a chip is more than 100W/cm2In time, the product basically loses the practical value, so the classical moore law is difficult to continue infinitely and can meet the limit bottleneck of energy consumption.
One way to solve the energy consumption problem is to reduce the subthreshold swing of the device, thereby reducing the off-current Ioff while ensuring the on-current Ion. The subthreshold swing of the CMOS device has a limit value of 60mv/dec, so as to break through the limit of the limit, the traditional drift diffusion mechanism must be abandoned, the work of a tunneling transistor (TFET) device is based on the quantum tunneling effect of a current carrier, the ultra-steep subthreshold slope can be realized theoretically, the advantages of the TFET device in the low power consumption application field are gradually shown, and the TFET device becomes a new principle device with great development potential in the post-molar age. However, the N-type TFET device in the prior art has a technical problem of large leakage current.
Disclosure of Invention
The embodiment of the application provides the N-type tunneling field effect transistor capable of effectively reducing the leakage current and the manufacturing method thereof.
In a first aspect, the present embodiment provides an N-type tunneling field effect transistor, including:
a semiconductor substrate;
a channel region formed on the semiconductor substrate;
a P-type source region formed on the semiconductor substrate and located at a first side of the channel region, the P-type source region having P+Type doping;
an N-type drain region formed on the semiconductor substrate and located on a second side of the channel region opposite to the first side, the N-type drain region having N+Type doping;
the grid electrode is arranged on the third side of the channel region, and a grid oxide layer is arranged between the grid electrode and the channel region;
the isolation region is arranged at the region where the drain body junction between the channel region and the N-type drain region is located, the isolation region is filled with a preset isolation oxide, the isolation region is overlapped with the gate oxide layer, and the isolation region is used for isolating electrons between the N-type drain region and the channel region and avoiding tunneling at the region where the drain body junction is located.
Optionally, the predetermined isolation oxide includes silicon dioxide and/or aluminum oxide.
Optionally, the channel region hasWith N-Type doping or P-Type doping with a concentration range of e15/cm3～e17/cm3。
Optionally, P of the P-type source region+The concentration range of the type doping is e19/cm3～e21/cm3。
Optionally, N of the N-type drain region+The concentration range of the type doping is e19/cm3～e21/cm3。
Optionally, the thickness range of the gate oxide layer is 1nm to 10 nm.
Optionally, the length range of the channel region is 10nm to 10 um.
Optionally, the material of the semiconductor substrate includes any one or a combination of more than one of bulk silicon, bulk germanium, silicon-on-insulator, and germanium-on-insulator.
In a second aspect, the present embodiment provides a method for manufacturing an N-type tunneling field effect transistor, including:
forming a channel region, an isolation region, a P-type source region and an N-type drain region on a semiconductor substrate, wherein the isolation region is filled with a preset isolation oxide, and the P-type source region is provided with a P+Type doping, the N type drain region has N+The isolation region is arranged in a region where a drain body junction between the channel region and the N-type drain region is located, and is used for isolating electrons between the N-type drain region and the channel region and avoiding tunneling in the region where the drain body junction is located;
and sequentially forming a gate oxide layer and a grid electrode on the channel region, wherein the isolation region is overlapped with the gate oxide layer.
Optionally, the predetermined isolation oxide includes silicon dioxide and/or aluminum oxide.
Optionally, the channel region has N-Type doping or P-Type doping with a concentration range of e15/cm3～e17/cm3。
Optionally, P of the P-type source region+The concentration range of the type doping is e19/cm3～e21/cm3。
Optionally, N of the N-type drain region+The concentration range of the type doping is e19/cm3～e21/cm3。
Optionally, the thickness range of the gate oxide layer is 1nm to 10 nm.
Optionally, the length range of the channel region is 10nm to 10 um.
Optionally, the material of the semiconductor substrate includes any one or a combination of more than one of bulk silicon, bulk germanium, silicon-on-insulator, and germanium-on-insulator.
One or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
the N-type tunneling field effect transistor provided by the embodiment of the application comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a P-type source region formed on the semiconductor substrate and located at the first side of the channel region, the P-type source region having P+Type doping; an N-type drain region formed on the semiconductor substrate and located at a second side of the channel region opposite to the first side, the N-type drain region having N+Type doping; the grid electrode is arranged on the third side of the channel region, and a grid oxide layer is arranged between the grid electrode and the channel region; and the isolation region is arranged in a region where a drain body junction between the channel region and the N-type drain region is located, the isolation region is filled with a preset isolation oxide, and the isolation region is overlapped with the gate oxide layer. The isolation region is arranged in the region where the drain body junction of the N-type drain region and the channel region is located, after the isolation region is filled with the preset isolation oxide, the isolation region is used for isolating electrons between the N-type drain region and the channel region from tunneling in the region where the drain body junction is located, so that tunneling leakage of the drain body junction is fundamentally eliminated, and leakage caused by bipolar characteristics of an N-type TFET device can be effectively reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an N-type tunneling field effect transistor according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of transfer curves corresponding to drain currents of an N-type tunneling field effect transistor according to a first embodiment of the present invention and an N-type tunneling field effect transistor according to the prior art under different gate-source voltages;
fig. 3 is a flowchart of a method for manufacturing an N-type tunneling field effect transistor according to a second embodiment of the present invention.
Detailed Description
The embodiment of the application provides an N-type tunneling field effect transistor and a manufacturing method thereof, and is used for reducing the leakage current of the N-type tunneling transistor. The N-type tunneling field effect transistor includes: a semiconductor substrate; a channel region formed on the semiconductor substrate, the channel region having P-Type doping; a P-type source region formed on the semiconductor substrate and located at a first side of the channel region, the P-type source region having N+Type doping; an N-type drain region formed on the semiconductor substrate and located on a second side of the channel region opposite to the first side, the N-type drain region having N+Type doping; the grid electrode is arranged on the third side of the channel region, and a grid oxide layer is arranged between the grid electrode and the channel region; the isolation region is arranged at the region where the drain body junction between the channel region and the N-type drain region is located, the isolation region is filled with a preset isolation oxide, the isolation region is overlapped with the gate oxide layer, and the isolation region is used for isolating electrons between the N-type drain region and the channel region and avoiding tunneling at the region where the drain body junction is located.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a first embodiment of the present invention provides an N-type tunneling field effect transistor, including:
a semiconductor substrate 101;
a channel region 102 formed on the semiconductor substrate 101;
a P-type source region 103 formed on the semiconductor substrate 101 and located at a first side of the channel region 102, the P-type source region 103 having a P+Type doping;
an N-type drain region 104 formed on the semiconductor substrate 101 and located at a second side of the channel region 102 opposite to the first side, the N-type drain region 104 having N+Type doping;
a gate 105 disposed on a third side of the channel region 102, wherein a gate oxide layer is disposed between the gate 105 and the channel region 102;
and an isolation region 106 arranged at a region where a drain junction between the channel region 102 and the N-type drain region is located, wherein the isolation region 106 is filled with a preset isolation oxide, the isolation region 106 is overlapped with the gate oxide layer 107, and the isolation region 106 is used for isolating electrons between the N-type drain region and the channel region 102 and avoiding tunneling at the region where the drain junction is located.
Specifically, in this embodiment, for the N-type tunneling field effect transistor in the prior art, due to the bipolar characteristic, when the absolute value of the drain voltage of the N-type tunneling field effect transistor is relatively large (the drain voltage is positive) or the gate voltage is negative, the drain-body junction may also generate the tunneling effect, thereby increasing the leakage current of the device. Therefore, in order to solve the problem, because the main cause of the leakage current is from the drain-body junction tunneling leakage, the N-type tunneling field effect transistor provided in this embodiment increases the isolation region 106 in the region where the drain-body junction is located, for example, at the boundary between the N-type drain region 104 and the channel region 102 shown in fig. 1, on the basis of the N-type tunneling field effect transistor structure in the prior art, and the isolation region 106 is filled with the predetermined oxide isolation, so as to fundamentally eliminate the drain-body junction tunneling leakage, the top of the isolation region 106 is overlapped with the gate oxide, and the isolation region cannot block the drain-body junction, so the area of the isolation region 106 is smaller than the area of the region where the drain-body junction is located, and is disposed in the region close to the gate oxide region, which is.
As shown in fig. 1, the isolation region 106 is a rectangular region having a width and a height related to other parameters of the mold, specifically, the width of the isolation region 106 is to ensure that no oxide tunneling occurs, and the height of the isolation region 106 is to ensure that all regions where tunneling may occur at the drain junction are isolated. In a specific implementation process, the shape and the size of the isolation region 106 may be set according to actual conditions, and the present application is not limited herein.
Further, in the present embodiment, the predetermined isolation oxide comprises silicon dioxide and/or aluminum oxide, and the channel region 102 is lightly doped with P-Type doping or N-Type doping with a concentration range of e15/cm3～e17/cm3. P of P-type source region 103+The concentration range of the type doping is e19/cm3～e21/cm3And is heavily doped. N of N-type drain region+The concentration range of the type doping is e19/cm3～e21/cm3And also heavily doped. The thickness of the gate oxide layer 107 is in the range of 1nm to 10 nm. The length of the channel region 102 ranges from 10nm to 10 um. The semiconductor substrate 101 may be an intrinsic doped or lightly doped semiconductor substrate, and if the semiconductor substrate 101 is a lightly doped semiconductor substrate 101, the doping type may be the same as the P-type source region 103, having P+And (4) carrying out type doping. The material of the semiconductor substrate 101 may include bulk silicon (bulk Si), bulk germanium (bulk Ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or other compound semiconductor substrate such as: SiGe, SiC, GaN, GaAs, InP, and the like, as well as combinations of these. To be compatible with existing IC fabrication processes, the semiconductor substrate 101 is preferably a silicon-containing substrate, such as: in the implementation of the substrate including Si, SOI, SiGe, etc., the material of the semiconductor substrate 101 may be set according to actual needs, and the present application is not limited thereto.
Further, in the present embodiment, the gate 105 is a metal-based gate electrode layer, for example, including a simple metal, or an alloy of these metals, and a conductive nitride or a conductive oxide of these metals, where the metals may include: co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc. The metal in the gate 105 may also be doped with C, F, N, O, B, P, As elements to adjust the work function of the metal.
Further, in the embodiment, the gate oxide layer 107 is disposed between the gate 105 and the channel region 102, and a filling material of the gate oxide layer 107 may include any one or a combination of several of high-k gate dielectric layers such as HfO2, Al2O3, ZrO2, and the like, and may be selected according to needs in a specific implementation process, which is not limited in the present application. The thickness of the gate oxide layer 107 is in a range of 1nm to 10nm, and may be set according to actual requirements in the specific implementation process, and the application is not limited herein.
When the gate voltage of the gate 105 is a negative voltage, if no isolation region is provided, an electron accumulation state occurs on the surface of the channel region 102, and at the same time, the surface drain junction is reversely biased, so that tunneling occurs at the drain junction (close to the gate oxide layer side), and after the isolation region is provided, the tunneling can be blocked by a preset isolation oxide, thereby effectively reducing electric leakage caused by tunneling.
Fig. 2 shows transfer curves corresponding to drain currents of the N-type tunneling field effect transistor in the present embodiment and the N-type tunneling field effect transistor in the prior art under different gate-source voltages, where the N-type tunneling field effect transistor in the present embodiment is used in the simulation diagram, and the isolation region has a height of 50nm and a width of 2 nm. As can be seen from fig. 2, the N-type TFET with the optimized device structure has greatly reduced bipolar effect and greatly reduced leakage current.
Referring to fig. 3, a second embodiment of the present invention provides a method for manufacturing an N-type tunneling field effect transistor, including the following steps:
s301: forming a channel region, an isolation region, a P-type source region and an N-type drain region on a semiconductor substrate, wherein the isolation region is filled with a preset isolation oxide, and the P-type source region is provided with a P+Type doping, the N type drain region has N+A channel region, an N-type drain region, an isolation region arranged at the region of the drain junction between the channel region and the N-type drain region for isolating electrons between the N-type drain region and the channel regionPreventing tunneling from occurring at a region where the drain-body junction is located;
s302: and sequentially forming a gate oxide layer and a grid electrode on the channel region, wherein the isolation region is overlapped with the gate oxide layer.
Specifically, in this embodiment, a drawing layout of the N-type tunneling field effect transistor in this embodiment is drawn first. The method can be drawn by professional chip drawing simulation software, such as: TCAD, drawing a layout including a semiconductor substrate, a channel region, a P-type source region, an N-type drain region, a grid oxide layer and an isolation region, wherein the channel region, the P-type source region, the N-type drain region, the grid oxide layer and the isolation region are positioned on the semiconductor substrate, the P-type source region and the N-type drain region are respectively positioned on the first side and the second side of the channel region, the grid is positioned on the third side of the channel region, the grid and the channel region are the grid oxide layer, the isolation region is positioned in a region where a. The size, shape, and other parameters of each region may be set according to specific needs, and the application is not limited herein. The drawn isolation region is located at the junction of the channel region and the N-type drain region, the region where the drain body junction is located can be determined through simulation software, and then the isolation region is arranged in the region, the drain body junction cannot be blocked by the isolation region, so that the area of the isolation region is smaller than that of the region where the drain body junction is located, and the isolation region is arranged in a region which is easy to penetrate through and is close to the gate oxide layer.
And after the drawing layout is drawn, actually manufacturing the N-type tunneling field effect transistor according to the size and the composition structure of each region of the N-type tunneling field effect transistor in the drawing layout. First, through step 301, according to the instruction of drawing the layout, a semiconductor substrate is formed, as described in the first embodiment, the semiconductor substrate may be an intrinsic doped semiconductor substrate or a lightly doped semiconductor substrate, and if the semiconductor substrate is a lightly doped semiconductor substrate, the doping type may be the same as the P-type source region and has P+And (4) carrying out type doping. The material of the semiconductor substrate may be bulk silicon (bulk Si), bulk germanium (bulk Ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or other compound semiconductor substrates, and in a specific implementation process, the material of the semiconductor substrate may be set according to actual needs, which is not limited in this application. In this embodiment, a semiconductor with an intrinsic doped silicon substrate is selectedA substrate.
Further, in step S301, P is formed on the semiconductor substrate according to the instruction of the drawing layout-Type or N-A channel region doped type. First, a channel region pattern is formed on a semiconductor substrate by photoetching, and then, a large-angle high-energy injection P is adopted-Type or N-The type doping element forms a channel region, the doping is light doping, P-Type doping or N-The concentration range of the type doping is e15/cm3～e17/cm3The implantation energy is 100 to 350keV, the implantation angle is 50 to 60 degrees, the length of the channel region is the length indicated in the drawing layout, and the range is 10nm to 10 um.
Next, in step S301, according to the instruction of the drawing layout, an isolation region filled with a preset isolation oxide is disposed in a region where a drain junction between the channel region and the N-type drain region is located, where the isolation region is used to isolate electrons between the N-type drain region and the channel region from tunneling. Specifically, the region where the drain body junction is located can be determined through multiple experimental tests, the region where the drain body junction is located is generally located in a junction region of the channel region and the N-type drain region, and the region where the drain body junction is located can be determined through the experimental tests. The area where the drain body junction is formed is patterned on the semiconductor substrate by photolithography, and then, a predetermined isolation oxide is inserted into the area, such as: silicon dioxide or aluminum oxide (Al2O3) after insertion of a predetermined isolation oxide, forms the isolation regions. In a specific implementation process, the isolation region may be configured as a rectangular region, and the width and the height of the rectangular region are related to other parameters of the mold, specifically, the width of the isolation region is to ensure that no oxide tunneling occurs, and the height of the isolation region is to ensure that all regions where tunneling may occur at the drain junction are isolated. In the specific implementation process, the shape and the size of the isolation region can be set according to the actual situation, and the application is not limited herein.
Therefore, even if the absolute value of the leakage voltage is larger or the grid voltage is negative, the isolation region is filled with the preset oxide isolation, electrons between the isolation N-type drain region and the channel region are subjected to tunneling in the region where the drain junction is located, the tunneling leakage of the drain junction is eliminated fundamentally, and the leakage current of the N-type tunneling field effect transistor is reduced. In the specific implementation process, the shape and the size of the isolation region can be set according to the actual situation, and the application is not limited herein.
Next, a P-type source region is formed on the semiconductor substrate by step S301. Firstly, a P-type source region pattern is formed on a first side of a channel region on a semiconductor substrate through photoetching, and then P is implanted by adopting a middle angle+The type doping element forms a P-type doped source region, P+The concentration range of the type doping is e19/cm3～e21/cm3The implantation energy is 50 to 300keV and the implantation angle is 20 to 40 degrees.
Next, an N-type drain region is formed on the semiconductor substrate by step S301. Firstly, an N-type drain region pattern is formed on the second side of a channel region on a semiconductor substrate through photoetching, and then N is implanted by adopting a middle angle+Type doping element forming N-type drain region, N+The concentration range of the type doping is e19/cm3～e21/cm3The implantation energy is 40 to 100keV and the implantation angle is 0 to 10 degrees. The P-type source region and the N-type drain region are respectively positioned at two sides of the channel region.
Further, a gate oxide layer and a gate electrode are sequentially formed on the top of the channel region by step S302. Specifically, a gate oxide layer may be formed on a semiconductor substrate by using an atomic layer deposition process, the gate oxide layer overlaps with the isolation region, the gate oxide layer may be made of any one or a combination of several of HfO2, Al2O3, ZrO2, and the like, the thickness of the gate oxide layer may be set to 1nm to 10nm, and the material and the thickness of the gate oxide layer may be set according to actual needs in a specific implementation process, which is not limited herein. After the gate oxide layer is arranged, a gate electrode is formed on the gate oxide layer by adopting an atomic layer deposition process. Further, in this embodiment, the gate is a metal-based gate electrode layer, for example, including a simple metal, or an alloy of these metals, and a conductive nitride or a conductive oxide of these metals, where the metals may include: co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc. The metal in the gate may also be doped with C, F, N, O, B, P, As elements to adjust the work function of the metal. In a specific implementation process, the material of the gate may be set according to actual conditions, and the application is not limited herein.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. An N-type tunneling field effect transistor, comprising:
a semiconductor substrate;
a channel region formed on the semiconductor substrate;
a P-type source region formed on the semiconductor substrate and located at a first side of the channel region, the P-type source region having P+Type doping;
an N-type drain region formed on the semiconductor substrate and located on a second side of the channel region opposite to the first side, the N-type drain region having N+Type doping;
the grid electrode is arranged on the third side of the channel region, and a grid oxide layer is arranged between the grid electrode and the channel region;
the isolation region is arranged at the channel region and the region where the drain body junction between the N-type drain regions is located, the isolation region is filled with preset isolation oxide, the isolation region and the gate oxide layer are overlapped and connected, the area of the isolation region is smaller than that of the region where the drain body junction is located, and the isolation region is used for isolating the N-type drain regions from electrons between the channel regions and avoiding tunneling at the region where the drain body junction is located.
2. The N-type tunneling field effect transistor of claim 1, wherein the predetermined isolation oxide comprises silicon dioxide and/or aluminum oxide.
3. The N-type tunneling field effect transistor of claim 1, wherein the channel region has N-Type doping or P-Type doping with a concentration range of e15/cm3～e17/cm3。
4. The N-type tunneling field effect transistor of claim 1, wherein the P-type source region is P-type+The concentration range of the type doping is e19/cm3～e21/cm3。
5. The N-type tunneling field effect transistor of claim 1, wherein the N of the N-type drain region+The concentration range of the type doping is e19/cm3～e21/cm3。
6. The N-type tunneling field effect transistor of claim 1, wherein the gate oxide layer has a thickness in the range of 1nm to 10 nm.
7. The N-type tunneling field effect transistor of claim 1, wherein the length of the channel region ranges from 10nm to 10 um.
8. The N-type tunneling field effect transistor of claim 1, wherein the material of the semiconductor substrate comprises any one or more of bulk silicon, bulk germanium, silicon-on-insulator, and germanium-on-insulator.
9. A method for manufacturing an N-type tunneling field effect transistor is characterized by comprising the following steps:
forming a channel region, an isolation region, a P-type source region and an N-type drain region on a semiconductor substrate, wherein the isolation region is filled with a preset isolation oxide, and the P-type source region is provided with a P+Type doping, the N type drain region has N+The isolation region is arranged in a region where a drain body junction between the channel region and the N-type drain region is located, and is used for isolating electrons between the N-type drain region and the channel region and avoiding tunneling in the region where the drain body junction is located;
and sequentially forming a gate oxide layer and a grid electrode on the channel region, wherein the isolation region is overlapped and connected with the gate oxide layer, and the area of the isolation region is smaller than that of the region where the drain junction is located.
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| CN106935651A (en) * | 2015-12-29 | 2017-07-07 | 台湾积体电路制造股份有限公司 | Transistor unit |
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| Title |
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| A Tunnel Dielectric-Based Tunnel FET;Zhijiong Luo et al;《IEEE ELECTRON DEVICE LETTERS》;20150930;第36卷(第9期);全文 * |
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