CN108807391A - Flash memory and forming method thereof - Google Patents
Flash memory and forming method thereof Download PDFInfo
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- CN108807391A CN108807391A CN201810516679.8A CN201810516679A CN108807391A CN 108807391 A CN108807391 A CN 108807391A CN 201810516679 A CN201810516679 A CN 201810516679A CN 108807391 A CN108807391 A CN 108807391A
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Abstract
A kind of flash memory and forming method thereof, flash memory includes：Semiconductor substrate, semiconductor substrate include virtual storage and lead district, and lead district includes the first lead district, the second lead district, lead bonding pad and source lead area, and the width of lead bonding pad is more than the width of the first lead district and the width more than the second lead district；Source region in semiconductor substrate scratching area and in source lead area；Erasing grid on semiconductor substrate scratching area, erasing grid are located in the source region of scratching area and do not extend to lead district；Floating gate structure on semiconductor substrate section control zone, floating gate structure are located at erasing grid in the both sides of second direction；The control gate structure of control gate structure on semiconductor substrate control zone, the first lead district, the second lead district and lead bonding pad, control zone is also located in floating gate structure；Control gate plug positioned at the control grid structural top surface of lead bonding pad.The performance of the flash memory is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of flash memory and forming method thereof.
Background technology
Flash memory is a kind of important device in IC products.Flash memory is mainly characterized by being not added with
The information of storage can be kept in the case of voltage for a long time.Flash memory has integrated level height, faster access speed and is easy to
The advantages that erasing, thus be widely used.
Flash memory is divided into two types：Gatestack (stack gate) flash memory and divide grid (split gate) fast
Flash memory.Gatestack flash memory has floating boom and the control gate positioned at the top of floating boom.Gatestack flash memory existed
The problem of erasing.Unlike gatestack flash memory, Split-gate flash memory is formed in the side of floating boom as erasing grid
The wordline of pole.Split-gate flash memory can effectively avoid erasure effect.
However, the performance of existing Split-gate flash memory is poor.
Invention content
Problems solved by the invention is to provide a kind of flash memory and forming method thereof, to improve the property of flash memory
Energy.
To solve the above problems, the present invention provides a kind of flash memory, including：Semiconductor substrate, the semiconductor lining
Bottom includes virtual storage and lead district, and the lead district is abutted with virtual storage in a first direction, the virtual storage
Including controlling scratching area, the control scratching area includes scratching area and is located at the control zone of scratching area both sides in a second direction, the
Two directions are vertical with first direction, and the lead district includes the first lead district, the second lead district, lead bonding pad and source lead
Area, the first lead district and the control zone of scratching area side abut in a first direction, the control of the second lead district and the scratching area other side
Area processed abuts in a first direction, and source lead area abuts in a first direction with scratching area, lead bonding pad extend in a second direction and
It is connect respectively with the first lead district and the second lead district, the first lead district, the second lead district and lead bonding pad surround source lead
Area, the width of lead bonding pad in a first direction are more than the first lead district width in a second direction and are more than the second lead
The width of area in a second direction；Source region in semiconductor substrate scratching area and in source lead area；Positioned at semiconductor substrate
Erasing grid on scratching area, the erasing grid are located in the source region of scratching area and do not extend to lead district；Positioned at semiconductor substrate
Floating gate structure on the control zone of part, and floating gate structure is located at erasing grid in the both sides of second direction, floating gate knot
Structure does not extend to lead district；Control on semiconductor substrate control zone, the first lead district, the second lead district and lead bonding pad
Controlling grid structural, and the control gate structure of control zone is also located in floating gate structure；Control gate plug, the control gate plug
Positioned at the top surface of the control gate structure of lead bonding pad.
Optionally, the width of first lead district in a second direction is equal to the width of the second lead district in a second direction
Degree, and the width of the first lead district in a second direction is equal to the width of each control zone in a second direction；The lead connection
The width of area in a first direction is 1.5 times~3 times of the width of the first lead district in a second direction, and lead bonding pad is the
Width on one direction is 1.5 times~3 times of the width of the second lead district in a second direction.
Optionally, the control gate structure includes：Control grid structural body, control gate top protective layer and control gate every
Absciss layer, the control grid structural body is located at semiconductor substrate control zone, the first lead district, the second lead district are connected with lead
Qu Shang, and the control gate structure of control zone is also located in floating gate structure, the control grid structural body of control zone is second
The width in direction is less than floating gate structure in the width of second direction, and control gate top protective layer is located at the control grid knot of control zone
The top surface of structure ontology, and control gate top protective layer does not cover the control of the first lead district, the second lead district and lead bonding pad
The top surface of controlling grid structural ontology, the control gate spacer are located at the side wall of the control grid structural body；It is described
Control gate plug is located at the top surface of the control grid structural body of lead bonding pad.
Optionally, the top surface of the floating gate structure is recessed；The top edge direction of the floating gate structure
The side for wiping grid has tip.
Optionally, further include：Source plug in the source region in the source lead area, the source plug and source lead area
Source region is electrically connected；Wiping between the erasing grid and the source region of scratching area and between erasing grid and floating gate structure
Except separation layer；The virtual storage further includes wordline bitline regions, and the wordline bitline regions are located at control scratching area the
The both sides in two directions；The flash memory further includes：It is located at erasing grid, floating gate structure and control gate structure both sides
Word line structure on wordline bitline regions；Positioned at word line structure, erasing grid and the semiconductor substrate wordline for controlling gate structure both sides
Drain region in bitline regions.
The present invention also provides a kind of forming methods of flash memory, including：Semiconductor substrate, the semiconductor lining are provided
Bottom includes virtual storage and lead district, and the lead district is abutted with virtual storage in a first direction, the virtual storage
Including controlling scratching area, the control scratching area includes scratching area and is located at the control zone of scratching area both sides in a second direction, the
Two directions are vertical with first direction, and the lead district includes the first lead district, the second lead district, lead bonding pad and source lead
Area, the first lead district and the control zone of scratching area side abut in a first direction, the control of the second lead district and the scratching area other side
Area processed abuts in a first direction, and source lead area abuts in a first direction with scratching area, lead bonding pad extend in a second direction and
It is connect respectively with the first lead district and the second lead district, the first lead district, the second lead district and lead bonding pad surround source lead
Area, the width of lead bonding pad in a first direction are more than the first lead district width in a second direction and are more than the second lead
The width of area in a second direction；Form the source region being located in semiconductor substrate scratching area and in source lead area；It is formed and is located at half
Erasing grid on conductor substrate scratching area, the erasing grid are located in the source region of scratching area and do not extend to lead district；Form position
In the floating gate structure on semiconductor substrate section control zone, and floating gate structure is located at erasing grid the two of second direction
Side, floating gate structure do not extend to lead district；Formed positioned at semiconductor substrate control zone, the first lead district, the second lead district and
Control gate structure on lead bonding pad, and the control gate structure of control zone is also located in floating gate structure；Connect in lead
The top surface for connecing the control gate structure in area forms control gate plug.
Optionally, the virtual storage further includes wordline bitline regions, and the wordline bitline regions are located at control erasing
Area is in the both sides of second direction；Formed the floating gate structure, control gate structure, source region and wipe grid method include：?
On the scratching area and source lead area and part of semiconductor substrate controls and forms floating gate structural membrane on scratching area, and positioned at control
Floating gate structural membrane on scratching area processed also extends on the wordline bitline regions of semiconductor substrate；It leads in floating gate structural membrane and partly
Dielectric layer is formed in body substrate, and there is the first opening, the first opening to draw positioned at control zone, the first lead district, second in dielectric layer
In line area and lead bonding pad and do not extend on scratching area, source lead area and wordline bitline regions；It is formed in the first opening just
Begin control gate structure, and initial gate structure includes controlling grid structural body and positioned at the entire top of control grid structural body
The initial control gate top protective layer on portion surface；After forming initial control gate structure, Jie in scratching area and source lead area is removed
The floating gate structural membrane of matter floor and scratching area and source lead area forms the second opening in the dielectric layer；In the second open bottom
Semiconductor substrate scratching area and source lead area in form source region；After forming source region, erasing grid are formed in the second opening；It is formed
After wiping grid, the dielectric layer and the first lead district, the second lead district, lead bonding pad and source lead of removal wordline bitline regions
The dielectric layer of lead district around area；The dielectric layer and the first lead district, the second lead district, lead for removing wordline bitline regions connect
It connects around area and source lead area after the dielectric layer of lead district, the floating gate structural membrane of removal wordline bitline regions makes the floating of control zone
Gate structure film forms floating gate structure；After the floating gate structural membrane for removing wordline bitline regions, the erasing in source lead area is removed
Grid；After removing the erasing grid in source lead area, the initial control on the first lead district of removal, the second lead district and lead bonding pad
Grid top protective layer makes the initial control gate top protective layer of control zone form control gate top protective layer, and makes initially to control grid knot
It is configured to control gate structure.
Optionally, further include：Wordline knot is formed on the wordline bitline regions of initially control gate structure and erasing grid both sides
Structure；During forming word line structure, the erasing grid in source lead area are removed；It is described after forming the control gate structure
Word line structure is located on the wordline bitline regions of control gate structure, floating gate structure and erasing grid both sides.
Optionally, further include：It is formed in the first opening before initial control gate structure, the first open bottom is floated
Gate structure film performs etching, and keeps the floating gate structure film surface of the first open bottom recessed；After forming floating gate structure,
The side of the top edge of the floating gate structure towards erasing grid has tip.
Optionally, the initial gate structure further includes being located at the control gate spacer of control grid structural body side wall；
After forming erasing grid, controlling has control gate spacer between grid structural body and erasing grid；The shape of the flash memory
Further include at method：It is described second opening in formed erasing grid before, second opening side wall and bottom formed erasing every
Absciss layer；After forming the erasing grid, between erasing grid and the source region of scratching area and between erasing grid and floating gate structure
With erasing separation layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
In the flash memory that technical solution of the present invention provides, the lead district includes lead bonding pad, lead bonding pad
Extend in a second direction and is connect respectively with the first lead district and the second lead district, the width of lead bonding pad in a first direction
More than the first lead district width in a second direction and it is more than the width of the second lead district in a second direction, so that draw
The width of the control gate structure of line bonding pad is more than the width of the control gate structure of the first lead district and is more than the second lead
The width of the control gate structure in area.Since the width of the control gate structure of lead bonding pad is larger, and control gate plug position
In on the control gate structure of lead bonding pad, so that control gate plug is easy the control gate structure with lead bonding pad
Alignment.Since the width of width and the second lead district in a second direction of the first lead district in a second direction is smaller, because
This makes between control gate structure and the control gate structure of the second lead district in consecutive storage unit of the first lead district
There are sufficient space, the control grid knot of the control gate structure and the second lead district in consecutive storage unit of the first lead district
Structure is not easy short circuit.To sum up, the performance of flash memory is improved.
Further, the side of the top edge of the floating gate structure towards erasing grid has tip, in this way when erasing grid
When carrying out erasing operation, which can reduce the channel voltage of tunneling effect so that electronics is easier from floating gate structure tunnel
It wears to erasing grid, improves efficiency of erasing.
In the forming method for the flash memory that technical solution of the present invention provides, the lead district includes lead bonding pad,
Lead bonding pad extends and is connect respectively with the first lead district and the second lead district in a second direction, and lead bonding pad is in first party
Upward width is more than the first lead district width in a second direction and is more than the width of the second lead district in a second direction,
In this way so that the width of the control gate structure of lead bonding pad is larger, and control gate plug is located at the control gate of lead bonding pad
In the structure of pole, so that control gate plug is easy to be aligned with the control gate structure of lead bonding pad.Due to the first lead district
The width of width and the second lead district in a second direction in a second direction is smaller, so that the control of the first lead district
There are sufficient space, the first lead between the control gate structure of the second lead district in controlling grid structural and consecutive storage unit
The control gate structure in area and the control gate structure of the second lead district in consecutive storage unit are not easy short circuit.To sum up, it improves
The performance of flash memory.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of flash memory；
Fig. 2 to Figure 26 is the structural schematic diagram of flash memory forming process in one embodiment of the invention.
Specific implementation mode
As described in background, the performance for the flash memory that the prior art is formed is poor.
A kind of flash memory, referring to FIG. 1, including：Semiconductor substrate 100, the semiconductor substrate 100 include effective
X1 and virtual storage M is abutted in a first direction by memory block M and lead district N, the lead district N, and the virtual storage M includes
Scratching area is controlled, the control scratching area includes scratching area and Y1 is located at the control zone of scratching area both sides in a second direction, and second
Direction Y1 is vertical with first direction X1, and the lead district N includes the first lead district, the second lead district and source lead area, and first draws
X1 is abutted in a first direction for the control zone of line area and scratching area side, and the control zone of the second lead district and the scratching area other side is the
One direction X1 is abutted, and X1 is abutted in a first direction with scratching area in source lead area, and source lead area is located at the first lead district and second
Between lead district；Source region 130 in 100 scratching area of semiconductor substrate and in source lead area；In the source region of scratching area
Erasing grid 120, the erasing grid 120 do not extend to lead district N；Floating boom on 100 part control zone of semiconductor substrate
Pole structure (not shown), and floating gate structure is located at erasing grid in the both sides of second direction Y1, floating gate structure does not extend
To lead district N；Control gate structure 140 in 100 control zone of semiconductor substrate, the first lead district, the second lead district, and
The control gate structure 140 of control zone is also located in floating gate structure；It is located at the control of the first lead district and the second lead district
Control gate plug (not shown) on controlling grid structural 140.
With the continuous reduction of the characteristic size of flash memory, the characteristic size of each component subtracts in flash memory
It is small.It is used to form source plug in the source lead area, in order to enable the source region in source plug and source lead area can be aligned, usually
The size design of source lead area in a second direction is more than the size of scratching area in a second direction, is caused in this way adjacent
Storage unit in, the distance between the first adjacent lead district and the second lead district between adjacent control zone away from
From smaller.Secondly, in order to enable control gate plug can be aligned with the control gate structure of the first lead district and the second lead district,
Therefore the width of the control gate structure of the first lead district of design and the second lead district is more than the control gate structure of control zone
Width.
However, due in adjacent storage unit, the distance between the first adjacent lead district and the second lead district phase
It is smaller for the distance between adjacent control zone, and the width of the control gate structure of the first lead district and the second lead district is big
In the width of the control gate structure of control zone, therefore cause the control gate structure of the first lead district to adjacent storage unit
In the second lead district control gate structure between insufficient space, control gate structure to adjacent of the first lead district deposit
Short circuit occurs for the control gate structure of the second lead district in storage unit.
On this basis, the present invention provides a kind of flash memory, including：Semiconductor substrate, semiconductor substrate include having
Memory block and lead district are imitated, lead district includes the first lead district, the second lead district, lead bonding pad and source lead area, and lead connects
The width for meeting area is more than the width of the first lead district and the width more than the second lead district；It is neutralized positioned at semiconductor substrate scratching area
Source region in source lead area；Erasing grid on semiconductor substrate scratching area, erasing grid are located in the source region of scratching area and not
Extend to lead district；Floating gate structure on semiconductor substrate section control zone, floating gate structure are located at erasing grid
In the both sides of second direction；Control on semiconductor substrate control zone, the first lead district, the second lead district and lead bonding pad
The control gate structure of controlling grid structural, control zone is also located in floating gate structure；Control grid knot positioned at lead bonding pad
The control gate plug of structure top surface.The performance of the flash memory is improved.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 26 is the structural schematic diagram of flash memory forming process in one embodiment of the invention.
With reference to figure 2, semiconductor substrate 200 is provided, the semiconductor substrate 200 includes virtual storage A and lead district B,
X and virtual storage A is abutted the lead district B in a first direction, and the virtual storage A includes control scratching area A1, described
Control scratching area A1 includes scratching area A11 and Y is located at the control zone A12 of the both sides scratching area A11, second direction Y in a second direction
Vertical with first direction X, the lead district B includes the first lead district B1, the second lead district B2, lead bonding pad B3 and source lead
The control zone A12 X adjoinings in a first direction of area B4, the first lead district B1 and the sides scratching area A11, the second lead district B2 and erasing
X is abutted the control zone A12 of the area other sides A11 in a first direction, and X is abutted source lead area B4 and scratching area A11 in a first direction, is drawn
Y extends and is connect respectively with the first lead district B1 and the second lead district B2 line bonding pad B3 in a second direction, the first lead district B1,
Second lead district B2 and lead bonding pad B3 surround source lead area B4, and width of the lead bonding pad B3 in a first direction on X is more than
Width of the first lead district B1 on second direction Y and it is more than width of the second lead district B2 on second direction Y.
The material of the semiconductor substrate 200 can be silicon, germanium or SiGe.The semiconductor substrate 200 can be with
It is silicon-on-insulator (SOI), germanium on insulator (GeOI) or germanium on insulator SiClx (SiGeOI).It is described in the present embodiment
The material of semiconductor substrate 200 is monocrystalline silicon.
The extending direction of the scratching area A11 and control zone A12 is each parallel to first direction X.
Width of the first lead district B1 on second direction Y is equal to width of the second lead district B2 on second direction Y
Degree, and width of the first lead district B1 on second direction Y is equal to width of each control zone A12 on second direction Y；It is described to draw
The width on X is 1.5 times~3 times of width of the first lead district B1 on second direction Y to line bonding pad B3 in a first direction；Institute
It is 1.5 times~the 3 of width of the second lead district B2 on second direction Y to state width of the lead bonding pad B3 in a first direction on X
Times.
Width of the lead bonding pad B3 in a first direction on X defines the control gate structure of follow-up lead bonding pad B3
Width on X in a first direction.Width of the first lead district B1 on second direction Y defines the control of follow-up first lead district B1
Width of the gate structure on second direction Y, width of the second lead district B2 on second direction Y define follow-up second lead district
Width of the control gate structure of B2 on second direction Y.
The virtual storage A further includes wordline bitline regions A2, and wordline bitline regions A2 is located at control scratching area A1 and exists
The both sides of second direction Y.The wordline bitline regions A2 is between adjacent control scratching area A1.
The source lead area B4 is discrete with the first lead district B1, the second lead district B2 and lead bonding pad B3 respectively.
It should be noted that virtual storage A includes the storage unit of multiple arrangements of Y in a second direction, each storage is single
Member includes the scratching area A11 and part wordline bitline regions between two adjacent control zone A12, adjacent control zone A12
A2.And lead bonding pad B3 connect and refers to the first lead district B1 and the second lead district B2 respectively：Lead bonding pad B3 with it is same
The first lead district B1 in one storage unit and the second lead district B2 connections, and adjacent first in adjacent storage unit
There is no lead bonding pad B3 between lead district B1 and the second lead district B2.
With the continuous reduction of the characteristic size of flash memory, the characteristic size of each component subtracts in flash memory
It is small.It is used to form source plug on the source lead area B4, in order to enable the source region in subsequent source plug and source lead area B4 can
Alignment, the usually ruler more than the erasing areas A11 on second direction Y of the size design by source lead area B4 on second direction Y
Very little, in this way in adjacent storage unit, the distance between the first adjacent lead district B1 and the second lead district B2 are relative to phase
The distance between adjacent control zone A12 is smaller.
Then, the source region being located in 200 scratching area A11 of semiconductor substrate and in source lead area B4 is formed；It is formed and is located at half
Erasing grid on 200 scratching area A11 of conductor substrate, the erasing grid are located in the source region of scratching area A11 and do not extend to lead
Area；The floating gate structure being located on 200 part control zone A12 of semiconductor substrate is formed, and floating gate structure is located at erasing
Grid do not extend to lead district in the both sides of second direction Y, floating gate structure；Formed positioned at 200 control zone A12 of semiconductor substrate,
Control gate structure on first lead district B1, the second lead district B2 and lead bonding pad B3, and the control grid of control zone A12
Structure is also located in floating gate structure；In lead bonding pad, the top surface of the control gate structure of B3 forms control gate plug.
Lower mask body is introduced to form the floating gate structure, control gate structure, source region and the method for wiping grid.
With reference to figure 3, on the scratching area A11 and source lead area B4 of semiconductor substrate 200 and semiconductor substrate 200
Floating gate structural membrane 210 is formed on the control scratching area A1 of part, and the floating gate structural membrane 210 on control scratching area A1 is also
It extends on the wordline bitline regions A2 of semiconductor substrate 200.
The present embodiment further includes：During forming floating gate structural membrane 210, is formed and be located at part semiconductor substrate
Substrate separation layer (not shown) in 200.The material of the substrate separation layer is silica.
(do not scheme specifically, forming initial FGS floating gate structure film on the virtual storage A and lead district B of semiconductor substrate 200
Show)；Mask layer (not shown) is formed on initial FGS floating gate structure film；The graphical mask layer, initial floating boom knot
Structure film and part semiconductor substrate 200, formed the floating gate structural membrane 210 and in floating gate structural membrane 210 first
Mask layer, is formed simultaneously groove, and the groove is located in the semiconductor substrate 200 around floating gate structural membrane 210；In the ditch
Substrate separation layer is formed in slot；After forming substrate separation layer, first mask layer is removed.The floating gate structural membrane 210 by
Initial FGS floating gate structure film is formed, and first mask layer is formed by mask layer.
In the present embodiment, there is floating gate structural membrane 210 on lead district B, only source lead area B4.
The floating gate structural membrane 210 is including floating gate dielectric film 211 and is located at 211 floating gate electrode film of floating gate dielectric film
212, floating gate dielectric film 211 is located on the scratching area A11 and source lead area B4 of semiconductor substrate 200 and semiconductor substrate 200
Part control scratching area A1 on, and the floating gate dielectric film 211 on control scratching area A1 also extends to semiconductor substrate 200
Wordline bitline regions A2 on.The material of the floating gate dielectric film 211 is silica or high K (K is more than 3.9), the floating gate electrode
The material of film 212 is polysilicon.
Region where the floating gate structural membrane 210 corresponds to the position of active area.
With reference to figure 4, dielectric layer 230 is formed in floating gate structural membrane 210 and semiconductor substrate 200, is had in dielectric layer 230
There are the first opening 231, the first opening 231 to be located at control zone A12, the first lead district B1, the second lead district B2 and lead bonding pad
B3 is upper and does not extend on scratching area A11, source lead area B4 and wordline bitline regions A2.
In the present embodiment, the first opening 231 is only located at control zone A12, the first lead district B1, the second lead district B2 and lead
On the B3 of bonding pad.
The material of the dielectric layer 230 includes silicon nitride.
Go out the substrate separation layer and control zone A12 of control zone A12 in the bottom-exposed of virtual storage A, the first opening 231
Floating gate structural membrane 210；Go out the first lead district B1, the second lead district B2 in the bottom-exposed of lead district B, the first opening 231
With the substrate separation layer of lead bonding pad B3.
In the present embodiment, the first opening 231 is more than the first opening 231 in lead bonding pad B3 along the width of first direction X
In the width of the first lead district B1 Y in a second direction, and more than first opening 231 in the second lead district B2 Y in a second direction
Width.
In the present embodiment, first opening 231 the first lead district B1 in a second direction Y width be equal to first opening 231
In the width of the second lead district B2 Y in a second direction, and equal to the first opening 231 each control zone A12 Y in a second direction width
Degree.
In the present embodiment, is formed in follow-up first opening 231 before initial control gate structure, further include：To first
The floating gate structural membrane 210 of 231 bottoms of being open performs etching, and makes 210 surface of floating gate structural membrane of 231 bottom of the first opening be in
Recess.
In other embodiments, the floating gate structural membrane of the first open bottom is not performed etching, correspondingly, the first opening
The floating gate structure film surface of bottom is planar.
In conjunction with being the schematic diagram of the cutting line A-A1 along Fig. 4 with reference to figure 4 and Fig. 5, Fig. 5, the first 231 bottoms of opening are floated
Gate structure film 210 performs etching, and keeps 210 surface of floating gate structural membrane of 231 bottom of the first opening recessed.
Specifically, the technique performed etching to the floating gate structural membrane 210 of the first 231 bottoms of opening is dry carving technology, ginseng
Number includes：The gas of use includes CF4、O2And N2, CF4Flow be 70sccm~150sccm, O2Flow be 100sccm~
250sccm, N2Flow be 10sccm~30sccm, source radio-frequency power be 350 watts~500 watts, bias voltage be 0 volt, strong room
Pressure is 150mtorr~300mtorr.
It is follow-up since 210 surface of floating gate structural membrane of the first 231 bottoms of opening is recessed in the present embodiment
After forming floating gate structure, the side of top edge towards the erasing grid of floating gate structure has tip.
With reference to figure 6 to Fig. 9, initial control gate structure 240 is formed in first 231 (with reference to figure 4 and Fig. 5) of opening, just
Beginning gate structure 240 includes control grid structural body 241 and the entire top surface positioned at control grid structural body 241
Initial control gate top protective layer 242.
In the present embodiment, the initial control gate structure 240 further includes being located at 241 side wall of control grid structural body
Control gate spacer 243.The material of the control gate spacer 243 and initial control gate top protective layer 242 includes silica.?
It is initial to control gate structure 240 not including control gate spacer 243, correspondingly, subsequent control grid knot in other embodiments
Structure does not include control gate spacer yet.
The initial control gate structure 240 is located at 200 control zone A12 of semiconductor substrate, the first lead district B1, second draws
On line area B2 and lead bonding pad B3, the initial control gate structure 240 of control zone A12 is also located at the floating gate of control zone A12
In structural membrane 210.
In the present embodiment, the initial gate structure 240 that controls is more than initially in lead bonding pad B3 along the width of first direction X
Control gate structure 240 the first lead district B1 Y in a second direction width, and more than initial control gate structure 240 the
The width of two lead district B2 Y in a second direction.
In the present embodiment, it is initial control gate structure 240 be equal in the width of the first lead district B1 Y in a second direction it is initial
Gate structure 240 is controlled in the width of the second lead district B2 Y in a second direction, and the initial control gate equal to each control zone A12
Width of the pole structure 240 on second direction Y.
In conjunction with being schematic diagram on the basis of Fig. 4 with reference to figure 6 and Fig. 7, Fig. 6, Fig. 7 is schematic diagram on the basis of Fig. 5,
The side wall and the top surface of bottom and dielectric layer 230 of first opening 231 form control gate spacer material layer；It is etched back to control
Grid spacer material layer processed is until expose the top surface on floating gate structural membrane 210 surface and dielectric layer 230, in the first opening
231 side wall forms control gate spacer 243.
The technique for forming the control gate spacer material layer is depositing operation, such as plasma activated chemical vapour deposition technique or
Atom layer deposition process.The material of control gate spacer material layer includes silica.
The control gate spacer 243 connects in control zone A12, the first lead district B1, the second lead district B2 and lead respectively
Connect the consistency of thickness on area B3.
In conjunction with being schematic diagram on the basis of Fig. 6 with reference to figure 8 and Fig. 9, Fig. 8, Fig. 9 is schematic diagram on the basis of Fig. 7, shape
After control gate spacer 243, control grid structural body 241, the control gate structure sheet are formed in the first opening 231
The top surface of body 241 is less than the top surface of dielectric layer 230；It is formed in the first opening 231 and is located at control gate structure sheet
The initial control gate top protective layer 242 of the entire top surface of body 241.
Specifically, after forming control gate spacer 243, in the first opening 231 and controls gate spacer 243 and be situated between
Control gate film is formed on matter layer 230, control gate film includes controlling gate dielectric film and the control gate electricity on control gate dielectric film
Pole film, wherein control gate dielectric film is located at the bottom and side wall of the first opening 231 and controls gate spacer 243 and dielectric layer
On 230；Planarization control gate film is until expose the top surface of dielectric layer 230；Later, it is etched back in the first opening 231
Part control gate film forms control grid structural body 241, control gate to reduce the height of control gate film in the first opening 231
Pole structural body 241 includes control gate dielectric layer and the control gate electrode layer on control gate dielectric layer.
The control gate dielectric layer is located at the bottom and side wall of control gate electrode layer.It is described control gate dielectric layer material be
Silica or high K (K is more than 3.9) dielectric layer.The material of the control gate electrode layer is polysilicon.
In the present embodiment, the side wall of the control gate spacer 243 covering control grid structural body 241.Control gate every
There is control gate dielectric layer before absciss layer 243 and control gate electrode layer.
In the present embodiment, based on lead bonding pad B3 in a first direction X width, the first lead district B1 is in second direction
The width of width and each control zone A12 on second direction Y of width, the second lead district B2 on second direction Y on Y it
Between relationship so that the gate structure ontology 241 of formation lead bonding pad B3 along first direction X width be more than gate structure
Ontology 241 the first lead district B1 Y in a second direction width, and more than gate structure ontology 241 on the second edges lead district B2
The width of second direction Y.
In the present embodiment, control gate electrode layer is more than control grid electrode in lead bonding pad B3 along the width of first direction X
Layer the first lead district B1 Y in a second direction width, and more than control gate electrode layer in the second lead district B2 Y in a second direction
Width.
In the present embodiment, gate structure ontology 241 the first lead district B1 in a second direction Y width be equal to gate structure
Ontology 241 the second lead district B2 Y in a second direction width, and equal to gate structure ontology 241 in each control zone A12 along the
The width of two direction Y.Specifically, the width on X is gate structure ontology 241 to the gate structure ontology 241 in a first direction
1.5 times~3 times of width on second direction Y, width of the gate structure ontology 241 in a first direction on X is gate structure
1.5 times of width of the ontology 241 on second direction Y~3 times.
In the present embodiment, control gate electrode layer the first lead district B1 in a second direction Y width be equal to control grid electrode
Layer the second lead district B2 Y in a second direction width, and equal to control gate electrode layer in each control zone A12 Y in a second direction
Width.
The method for forming initial control gate top protective layer 242 includes：Control grid structural body 241 top surface,
And form initial control gate top protective film on control gate spacer 243 and dielectric layer 230；Planarize initial control gate top protection
Film forms initial control gate top protective layer 242 up to exposing dielectric layer 230 and controlling the top surface of gate spacer 243.
The material of the initial control gate top protective layer 242 includes silica.
The control gate spacer 243 also covers the side wall of initial control gate top protective layer 242.
In conjunction with being schematic diagram on the basis of Fig. 8 with reference to figure 10 and Figure 11, Figure 10, Figure 11 is signal on the basis of Fig. 9
Figure after forming initial control gate structure 240, removes scratching area A11 and the dielectric layer 230 on source lead area B4 and erasing
The floating gate structural membrane 210 of area A11 and source lead area B4 form the second opening 232 in dielectric layer 230.
Specifically, after forming initial control gate structure 240, the dielectric layer on scratching area A11 and source lead area B4 is removed
230；After removing the dielectric layer 230 on scratching area A11 and source lead area B4, the floating boom of scratching area A11 and source lead area B4 are removed
Pole structural membrane 210.
In conjunction with being schematic diagram on the basis of Figure 10 with reference to figure 12 and Figure 13, Figure 12, Figure 13 is showing on the basis of Figure 11
It is intended to, source region 250 is formed in the semiconductor substrate 200 scratching area A11 and source lead area B4 of the second 232 bottoms of opening；It is formed
After source region 250, erasing grid 260 are formed in the second opening 232.
The technique for forming source region 250 is ion implantation technology.
In the present embodiment, further include：Before forming erasing grid 260 in second opening 232, in the second opening 232
Side wall and bottom formed erasing separation layer 261；After forming the erasing grid 260, the erasing grid 260 and scratching area A11
There is erasing separation layer 261 between source region 250；After being subsequently formed floating gate structure, wipes and have between grid 260 and floating gate structure
There is erasing separation layer 261.
In the present embodiment, further include：Erasing grid top protective layer 262 is formed in the top surface of erasing grid 260.The erasing
The material of grid top protective layer 262 includes silica.In the present embodiment, the also covering erasing separation layer 261 of erasing grid top protective layer 262
Top surface.
In the present embodiment, the thickness of erasing grid top protective layer 262 is less than the thickness of initial control gate top protective layer 242
Degree.
In conjunction with being schematic diagram on the basis of Figure 12 with reference to figure 14 and Figure 15, Figure 14, Figure 15 is showing on the basis of Figure 13
It is intended to, after forming erasing grid 260, the dielectric layer 230 and the first lead district B1, the second lead district of removal wordline bitline regions A2
The dielectric layer 230 of lead district B around B2, lead bonding pad B3 and source lead area B4.
In conjunction with being schematic diagram on the basis of Figure 14 with reference to figure 16 and Figure 17, Figure 16, Figure 17 is showing on the basis of Figure 15
Be intended to, the dielectric layer 230 and the first lead district B1 of removal wordline bitline regions A2, the second lead district B2, lead bonding pad B3 and
Around source lead area B4 after the dielectric layer 230 of lead district B, the floating gate structural membrane 210 of removal wordline bitline regions A2 makes control zone
The floating gate structural membrane 210 of A12 forms floating gate structure 270.
The floating gate structure 270 is located on the part control zone A12 of semiconductor substrate.The floating gate structure 270 is wrapped
Include floating gate dielectric layer 271 and the floating gate electrode layer 272 on floating gate dielectric layer 271.The material of the floating gate dielectric layer 271 is joined
According to the material of floating gate dielectric film 211, the material of the material reference floating gate electrode film 212 of floating gate electrode layer 272.
After forming floating gate structure 270, the top edge of the floating gate structure 270 has towards 260 side of erasing grid
Tip.Such benefit includes：When wiping the progress erasing operation of grid 260, which can reduce the channel electricity of tunneling effect
Pressure so that electronics is easier, from 270 tunnelling of floating gate structure to erasing grid 260, to improve efficiency of erasing.
After the floating gate structural membrane 210 for removing wordline bitline regions A2, the erasing grid 260 on source lead area B4 are removed.
In conjunction with being schematic diagram on the basis of Figure 16 with reference to figure 18, Figure 19 and Figure 20, Figure 18, Figure 19 is on the basis of Figure 17
Schematic diagram, Figure 20 is the sectional view along cutting line B-B1 in Figure 18, the floating gate structural membrane 210 of removal wordline bitline regions A2
Afterwards, wordline is formed on the initially wordline bitline regions A2 of 260 both sides of control gate structure 240, floating gate structure 270 and erasing grid
Structure 280；During forming word line structure 280, the erasing grid 260 on source lead area B4 are removed.
Specifically, forming word line structure film on virtual storage A and lead district B, the word line structure film covering is initial
Control gate structure 240, erasing grid 260 and erasing grid top protective layer 262；It is formed on the word line structure film of virtual storage A
Second mask layer, and the second mask layer exposes the word line structure film of lead district B；Draw by mask etching removal of the second mask layer
The word line structure film of line area B；Later, the erasing grid top protective layer of source lead area B4 is removed using the second mask layer as mask etching
262, expose the erasing grid 260 of source lead area B4；Later, the second mask layer is removed；After removing the second mask layer, it has been etched back to
The word line structure film of memory block A is imitated until exposing the wordline bitline regions surfaces A2 of semiconductor substrate 200, forms word line structure
280；During being etched back to the word line structure film of virtual storage A, the erasing grid 260 of etching removal source lead area B4 and source
The erasing separation layer 261 of lead district B4 exposes 250 surface of source region of source lead area B4.
It should be noted that since the thickness of erasing grid top protective layer 262 is less than initial control gate top protective layer 242
Thickness, therefore during removing using the second mask layer as mask etching the erasing grid top protective layer 262 of source lead area B4, draw
The thickness of the initial control gate top protective layer 242 of line area B is thinned but will not be completely removed, when etching removal source lead area
After the erasing grid top protective layer 262 of B4,241 top surface of control grid structural body of lead district B also remains with initial control
Grid top protective layer 242, at this point, the thickness of the initial control gate top protective layer 242 of lead district B is less than the initial control of control zone A12
The thickness of grid top processed protective layer 242.
Due to before the erasing grid 260 of etching removal source lead area B4, the control grid structural body 241 of lead district B
Top surface also remains with initial control gate top protective layer 242, and the 241 top table of control grid structural body of control zone A12
There is initial control gate top protective layer 242 in face, therefore the technique for etching the erasing grid 260 of removal source lead area B4 will not be to control gate
Pole structural body 241 causes etching injury.
In conjunction with being schematic diagram on the basis of Figure 18 with reference to figure 21, Figure 22, Figure 23 and Figure 24, Figure 21, Figure 22 is in Figure 19
On the basis of schematic diagram, Figure 23 is schematic diagram on the basis of Figure 20, and Figure 24 is the sectional view of the cutting line C-C1 along Figure 21, is gone
It is first on the first lead district B1 of removal, the second lead district B2 and lead bonding pad B3 after the erasing grid 260 on source lead area B4
Beginning control gate top protective layer 242 makes the initial control gate top protective layer 242 of control zone A12 form control gate top protective layer 292,
And make initially to control the formation control gate structure 290 of gate structure 240.
After the erasing grid 260 on removal source lead area B4, the thickness of the initial control gate top protective layer 242 of lead district B
The thickness of initial control gate top protective layer 242 of the degree less than control zone A12, therefore no mask etching technique removal the can be used
Initial control gate top protective layer 242 on one lead district B1, the second lead district B2 and lead bonding pad B3.
Remove the initial control gate top protective layer 242 on the first lead district B1, the second lead district B2 and lead bonding pad B3
Afterwards, 260 top surface of erasing grid of scratching area A11 also remains with erasing grid top protective layer 262.
The control gate structure 290 is located at 200 control zone A12 of semiconductor substrate, the first lead district B1, the second lead district
On B2 and lead bonding pad B3, the control gate structure 290 of control zone A12 is also located at the floating gate structure 270 of control zone A12
On.
In the present embodiment, the control gate structure 290 includes：Control grid structural body 241, control gate top protective layer
292 and control gate spacer 243, the control grid structural body 241 be located at 200 control zone A12 of semiconductor substrate, first draw
On line area B1, the second lead district B2 and lead bonding pad B3, and the control grid structural body 241 of control zone A12 be also located at it is floating
On gate structure 270, control gate top protective layer 292 is located at the top surface of the control grid structural body 241 of control zone A12,
And control gate top protective layer 292 does not cover the control grid knot of the first lead district B1, the second lead district B2 and lead bonding pad B3
The top surface of structure ontology 241, the control gate spacer 243 are located at the side wall of the control grid structural body 241.
In the present embodiment, control gate structure 290 includes control gate spacer 243, correspondingly, control grid structural body
241 second direction Y width be less than floating gate structure 270 second direction Y width.
In the present embodiment, there is control gate spacer 243 between control grid structural body 241 and erasing grid 260 and wipe
Except separation layer 261, and only there is erasing separation layer 261 between floating gate structure and erasing grid 260, controls gate structure sheet in this way
Body 241 and erasing grid 260 between control gate spacer 243 and erasing separation layer 261 overall thickness, be more than floating gate structure with
The erasing separation layer 261 between grid 260 is wiped, so that resistance between control grid structural body 241 and erasing grid 260 hits
Wear performance raising.
In the present embodiment, there is control gate spacer 243 between control grid structural body 241 and word line structure 280, make
The resistance to sparking between grid structural body 241 and word line structure 280, which must be controlled, to be improved.
In other embodiments, control gate structure does not include control gate spacer, correspondingly, control grid structural body
Second direction width be equal to floating gate structure second direction Y width.
In the present embodiment, control gate structure 290 is more than control grid in lead bonding pad B3 along the width of first direction X
Structure 290 the first lead district B1 Y in a second direction width, and more than control gate structure 290 on the second edges lead district B2
The width of second direction Y.
In the present embodiment, control gate structure 290 the first lead district B1 in a second direction Y width be equal to control grid
Structure 290 is in the width of the second lead district B2 Y in a second direction, and the control gate structure 290 equal to each control zone A12 is the
Width on two direction Y.
After forming control gate structure 290, word line structure 280 is located at erasing grid 260, floating gate structure 270 and control
On the wordline bitline regions A2 of 290 both sides of controlling grid structural.
In the present embodiment, further include：Side wall (not shown) is formed, the side wall is located at the side wall of word line structure 280, described
Side wall is also located at the side wall of the control gate structure 290 of the first lead district B1, the second lead district B2 and lead bonding pad B3.
In the present embodiment, the side wall also extends to the surface of part semiconductor substrate 200, and the side wall is L-shaped.
In the present embodiment, further include：It is formed drain region (not shown), the drain region is located at word line structure 280, erasing grid 260
In the 200 wordline bitline regions A2 of semiconductor substrate of 290 both sides of control gate structure.
Specifically, forming initial sidewall structure, initial sidewall structure is located at the side wall of word line structure 280, the first lead district
The side wall of the initial control gate structure 240 of B1, the second lead district B2 and lead bonding pad B3, initial side wall includes first initial
Side wall and the second initial side wall, the first initial side wall are located at the side wall of word line structure 280, the first lead district B1, the second lead district
The side wall of the initial control gate structure 240 of B2 and lead bonding pad B3, the first initial side wall also extend to part semiconductor lining
The surface at bottom 200, the first initial side wall is L-shaped, and the second side wall is located at the side wall of word line structure 280, the first lead district B1,
The side wall of the initial control gate structure 240 of two lead district B2 and lead bonding pad B3, and on second the first initial side wall of side wall；
Later, in the semiconductor lining of initial sidewall structure, 240 both sides of word line structure 280, erasing grid 260 and initial control gate structure
Drain region is formed in 200 wordline bitline regions A2 of bottom；Later, the first lead district B1, the second lead district B2 and lead bonding pad B3 are removed
On initial control gate top protective layer 242, so that initial control gate top protective layer 242 is formed control gate top protective layer 292, and make just
Begin the control formation control gate structure 290 of gate structure 240；Connect removing the first lead district B1, the second lead district B2 and lead
During connecing the initial control gate top protective layer 242 on area B3, the second side wall is removed, and it is described so that the first initial side wall is formed
Side wall.
The material of the first initial side wall is silicon nitride, and the material of the second initial side wall is silica.
In the present embodiment, the L-shaped benefit of the side wall includes：At holding drain region center between word line structure center
In the case of with certain distance, make the control of the control gate structure and the second lead district in consecutive storage unit of the first lead district
There is more sufficient space filled media material between controlling grid structural, makes on source lead area B4 and around source lead area B4 have relatively to fill
The space filled media material divided.
In conjunction with being schematic diagram on the basis of Figure 23 with reference to figure 25 and Figure 26, Figure 25, Figure 26 is showing on the basis of Figure 24
It is intended to, after forming control gate top protective layer 292, the top surface shape of the control grid structural body 241 of B3 in lead bonding pad
At control gate plug 300.
In the present embodiment, further include：Source plug 310, the source plug 310 are formed in the source region 250 of source lead area B4
It is electrically connected with the source region 250 of source lead area B4.
Correspondingly, the present embodiment also provides a kind of flash memory formed using the above method, 1 to 24 is please referred to Fig.2,
Including：Semiconductor substrate 200, the semiconductor substrate 200 include virtual storage A and lead district B, the lead district B the
One direction X is abutted with virtual storage A, and the virtual storage A includes that control scratching area A1, the control scratching area A1 include
Scratching area A11 and in a second direction Y are located at the control zone A12 of the both sides scratching area A11, and second direction Y is vertical with first direction X,
The lead district B includes the first lead district B1, the second lead district B2, lead bonding pad B3 and source lead area B4, the first lead district
The control zone A12 X adjoinings in a first direction of B1 and the sides scratching area A11, the control of the second lead district B2 and the other sides scratching area A11
X is abutted area A12 processed in a first direction, and X is abutted in a first direction by source lead area B4 and scratching area A11, and lead bonding pad B3 is along the
Two direction Y extend and connect respectively with the first lead district B1 and the second lead district B2, the first lead district B1, the second lead district B2 and
Lead bonding pad B3 surrounds source lead area B4, and width of the lead bonding pad B3 in a first direction on X exists more than the first lead district B1
Width on second direction Y and it is more than width of the second lead district B2 on second direction Y；It is wiped positioned at semiconductor substrate 200
Source region 250 in area A11 and in source lead area B4；Erasing grid 260 on 200 scratching area A11 of semiconductor substrate, the wiping
Except grid 260 are located in the source region 250 of scratching area A11 and do not extend to lead district B；Positioned at 200 part control zone of semiconductor substrate
Floating gate structure 270 on A12, and floating gate structure 270 is located at erasing grid 260 in the both sides of second direction Y, floating gate
Structure 270 does not extend to lead district B；Positioned at 200 control zone A12 of semiconductor substrate, the first lead district B1, the second lead district B2 and
Control gate structure 290 on the B3 of lead bonding pad, and the control gate structure 290 of control zone A12 is also located at floating gate structure
On 270；Control gate plug 300 (with reference to figure 25), the control gate plug 300 are located at the control gate structure of lead bonding pad B3
290 top surface.
Width of the first lead district B1 on second direction Y is equal to width of the second lead district B2 on second direction Y
Degree, and width of the first lead district B1 on second direction Y is equal to width of each control zone A12 on second direction Y；It is described to draw
The width on X is 1.5 times~3 times of width of the first lead district B1 on second direction Y to line bonding pad B3 in a first direction；Institute
It is 1.5 times~the 3 of width of the second lead district B2 on second direction Y to state width of the lead bonding pad B3 in a first direction on X
Times.
The control gate structure 290 includes：Control grid structural body 241, control gate top protective layer 292 and control gate
Separation layer 243, the control grid structural body 241 are located at 200 control zone A12 of semiconductor substrate, the first lead district B1, second
On lead district B2 and lead bonding pad B3, and the control gate structure 290 of control zone A12 is also located in floating gate structure 270, control
The control grid structural body 241 of area A12 processed the width of second direction Y be less than floating gate structure 270 second direction Y width
Degree, control gate top protective layer 292 is located at the top surface of the control grid structural body 241 of control zone A12, and control gate top is protected
Sheath 292 does not cover the top table of the control grid structural body 241 of the first lead district, the second lead district and lead bonding pad
Face, the control gate spacer 243 are located at the side wall of the control grid structural body 241；The control gate plug 300 is located at
The top surface of the control grid structural body 241 of lead bonding pad B3.
The top surface of the floating gate structure 270 is recessed；The top edge direction of the floating gate structure 270 is wiped
Except the side of grid 260 has tip.
The flash further includes：Source plug 310 in the source region 250 of the source lead area B4, the source are inserted
The source region 250 of plug 310 and source lead area B4 is electrically connected；Between erasing grid 260 and the source region 250 of scratching area A11,
And the erasing separation layer 261 between erasing grid 260 and floating gate structure 270.
The virtual storage A further includes wordline bitline regions A2, and the wordline bitline regions A2 is located at control scratching area
A1 is in the both sides of second direction Y；The flash memory further includes：It is located at erasing grid 260, floating gate structure 270 and control
Word line structure 280 on 290 both sides wordline bitline regions A2 of controlling grid structural；Positioned at word line structure 280, erasing grid 260 and control
Drain region in the 200 wordline bitline regions A2 of semiconductor substrate of 290 both sides of gate structure.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of flash memory, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate include virtual storage and lead district, the lead district in a first direction with have
Memory block adjoining is imitated, the virtual storage includes control scratching area, and the control scratching area includes scratching area and along second party
To the control zone positioned at scratching area both sides, second direction is vertical with first direction, and the lead district includes the first lead district, second
Lead district, lead bonding pad and source lead area, the first lead district and the control zone of scratching area side abut in a first direction, and second
Lead district and the control zone of the scratching area other side abut in a first direction, and source lead area abuts in a first direction with scratching area, draws
Line bonding pad extends and is connect respectively with the first lead district and the second lead district in a second direction, the first lead district, the second lead
Area and lead bonding pad surround source lead area, and the width of lead bonding pad in a first direction is more than the first lead district in second party
Upward width and it is more than the width of the second lead district in a second direction；
Source region in semiconductor substrate scratching area and in source lead area；
Erasing grid on semiconductor substrate scratching area, the erasing grid are located in the source region of scratching area and do not extend to lead
Area；
Floating gate structure on semiconductor substrate section control zone, and floating gate structure is located at erasing grid in second party
To both sides, floating gate structure do not extend to lead district；
Control gate structure on semiconductor substrate control zone, the first lead district, the second lead district and lead bonding pad, and
The control gate structure of control zone is also located in floating gate structure；
Control gate plug, the control gate plug are located at the top surface of the control gate structure of lead bonding pad.
2. flash memory according to claim 1, which is characterized in that the width of first lead district in a second direction
Degree is equal to the width of the second lead district in a second direction, and the width of the first lead district in a second direction is equal to each control zone
Width in a second direction；The width of the lead bonding pad in a first direction be the first lead district in a second direction
1.5 times of width~3 times, the width of lead bonding pad in a first direction are the width of the second lead district in a second direction
1.5 times~3 times.
3. flash memory according to claim 1, which is characterized in that the control gate structure includes：Control grid
Structural body, control gate top protective layer and control gate spacer, the control grid structural body are located at semiconductor substrate control
On area, the first lead district, the second lead district and lead bonding pad, and the control gate structure of control zone is also located at floating gate structure
On, the control grid structural body of control zone is less than floating gate structure in the width of second direction, control in the width of second direction
Grid top processed protective layer is located at the top surface of the control grid structural body of control zone, and control gate top protective layer does not cover first
The top surface of lead district, the second lead district and the control of lead bonding pad grid structural body, the control gate spacer position
In the side wall of the control grid structural body；The control gate plug is located at the control grid structural body of lead bonding pad
Top surface.
4. flash memory according to claim 1, which is characterized in that the top surface of the floating gate structure is in recess
Shape；The side of the top edge of the floating gate structure towards erasing grid has tip.
5. flash memory according to claim 1, which is characterized in that further include：Source region positioned at the source lead area
On source plug, the source plug and the source region in source lead area are electrically connected；Positioned at it is described erasing grid and scratching area source region it
Between and erasing grid and floating gate structure between erasing separation layer；
The virtual storage further includes wordline bitline regions, and the wordline bitline regions are located at control scratching area in second direction
Both sides；The flash memory further includes：It is located at erasing grid, floating gate structure and control gate structure both sides wordline position
Word line structure in line area；Positioned at word line structure, erasing grid and the semiconductor substrate wordline bitline regions for controlling gate structure both sides
In drain region.
6. a kind of forming method of flash memory, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes virtual storage and lead district, and the lead district is in a first direction
It is abutted with virtual storage, the virtual storage includes control scratching area, and the control scratching area includes scratching area and along the
Two directions are located at the control zone of scratching area both sides, and second direction is vertical with first direction, the lead district include the first lead district,
Second lead district, lead bonding pad and source lead area, the first lead district and the control zone of scratching area side abut in a first direction,
Second lead district and the control zone of the scratching area other side abut in a first direction, and source lead area and scratching area are adjacent in a first direction
It connects, lead bonding pad extends and connect respectively with the first lead district and the second lead district in a second direction, the first lead district, second
Lead district and lead bonding pad surround source lead area, and the width of lead bonding pad in a first direction is more than the first lead district the
Width on two directions and it is more than the width of the second lead district in a second direction；
Form the source region being located in semiconductor substrate scratching area and in source lead area；
The erasing grid being located on semiconductor substrate scratching area are formed, the erasing grid are located in the source region of scratching area and do not extend to
Lead district；
The floating gate structure being located on semiconductor substrate section control zone is formed, and floating gate structure is located at erasing grid the
The both sides in two directions, floating gate structure do not extend to lead district；
Form the control grid knot being located on semiconductor substrate control zone, the first lead district, the second lead district and lead bonding pad
Structure, and the control gate structure of control zone is also located in floating gate structure；
Control gate plug is formed in the top surface of the control gate structure of lead bonding pad.
7. the forming method of flash memory according to claim 6, which is characterized in that the virtual storage further includes
Wordline bitline regions, the wordline bitline regions are located at control scratching area in the both sides of second direction；
Formed the floating gate structure, control gate structure, source region and wipe grid method include：In scratching area and source lead area
Floating gate structural membrane, and the floating boom on control scratching area are formed on upper and semiconductor substrate part control scratching area
Pole structural membrane also extends on the wordline bitline regions of semiconductor substrate；Medium is formed in floating gate structural membrane and semiconductor substrate
Layer, there is the first opening, the first opening to be located at control zone, the first lead district, the second lead district and lead bonding pad in dielectric layer
Above and do not extend on scratching area, source lead area and wordline bitline regions；Initial control gate structure is formed in the first opening, just
Beginning gate structure includes the initial control for controlling grid structural body and the entire top surface positioned at control grid structural body
Grid top protective layer；After forming initial control gate structure, remove scratching area and dielectric layer in source lead area and scratching area and
The floating gate structural membrane in source lead area forms the second opening in the dielectric layer；It is wiped in the semiconductor substrate of the second open bottom
Source region is formed in area and source lead area；After forming source region, erasing grid are formed in the second opening；After forming erasing grid, word is removed
Jie of lead district around the dielectric layer of line bitline regions and the first lead district, the second lead district, lead bonding pad and source lead area
Matter layer；Remove dielectric layer and the first lead district, the second lead district, lead bonding pad and the source lead area week of wordline bitline regions
After the dielectric layer for enclosing lead district, the floating gate structural membrane of removal wordline bitline regions makes the floating gate structural membrane of control zone be formed floating
Gate structure；After the floating gate structural membrane for removing wordline bitline regions, the erasing grid in source lead area are removed；It removes in source lead area
Erasing grid after, the initial control gate top protective layer in the first lead district of removal, the second lead district and lead bonding pad makes control
The initial control gate top protective layer in area forms control gate top protective layer, and makes initially to control gate structure formation control grid knot
Structure.
8. the forming method of flash memory according to claim 7, which is characterized in that further include：In initial control gate
Word line structure is formed on the wordline bitline regions of pole structure, floating gate structure and erasing grid both sides；In the process for forming word line structure
In, remove the erasing grid in source lead area；After forming the control gate structure, the word line structure is located at control grid knot
On the wordline bitline regions of structure, floating gate structure and erasing grid both sides.
9. the forming method of flash memory according to claim 7, which is characterized in that further include：In the first opening
It is formed before initial control gate structure, the floating gate structural membrane of the first open bottom is performed etching, the first open bottom is made
Floating gate structure film surface it is recessed；After forming floating gate structure, the top edge direction erasing of the floating gate structure
The side of grid has tip.
10. the forming method of flash memory according to claim 7, which is characterized in that the initial gate structure is also
It include the control gate spacer positioned at control grid structural body side wall；After forming erasing grid, grid structural body and wiping are controlled
Gate spacer is controlled except having between grid；
The forming method of the flash memory further includes：Before forming erasing grid in second opening, in the second opening
Side wall and bottom formed erasing separation layer；After forming the erasing grid, between erasing grid and the source region of scratching area and
Wiping between grid and floating gate structure has erasing separation layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810516679.8A CN108807391B (en) | 2018-05-25 | 2018-05-25 | Flash memory and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810516679.8A CN108807391B (en) | 2018-05-25 | 2018-05-25 | Flash memory and forming method thereof |
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| CN108807391A true CN108807391A (en) | 2018-11-13 |
| CN108807391B CN108807391B (en) | 2020-11-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712981A (en) * | 2019-01-02 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN111415937A (en) * | 2020-05-13 | 2020-07-14 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040241942A1 (en) * | 2002-11-05 | 2004-12-02 | Chia-Ta Hsieh | Self-aligned structure with unique erasing gate in split gate flash |
| US20050090057A1 (en) * | 2003-03-13 | 2005-04-28 | Chih-Wei Hung | Method of fabricating a flash memory cell |
| JP2014203898A (en) * | 2013-04-02 | 2014-10-27 | ルネサスエレクトロニクス株式会社 | Semiconductor storage device and manufacturing method of the same |
| US20150187646A1 (en) * | 2011-09-30 | 2015-07-02 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device and semiconductor device |
| US20170062443A1 (en) * | 2015-08-28 | 2017-03-02 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN106960848A (en) * | 2016-01-08 | 2017-07-18 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of separate gate flash memory unit interconnection |
-
2018
- 2018-05-25 CN CN201810516679.8A patent/CN108807391B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040241942A1 (en) * | 2002-11-05 | 2004-12-02 | Chia-Ta Hsieh | Self-aligned structure with unique erasing gate in split gate flash |
| US20050090057A1 (en) * | 2003-03-13 | 2005-04-28 | Chih-Wei Hung | Method of fabricating a flash memory cell |
| US20150187646A1 (en) * | 2011-09-30 | 2015-07-02 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device and semiconductor device |
| JP2014203898A (en) * | 2013-04-02 | 2014-10-27 | ルネサスエレクトロニクス株式会社 | Semiconductor storage device and manufacturing method of the same |
| US20170062443A1 (en) * | 2015-08-28 | 2017-03-02 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN106960848A (en) * | 2016-01-08 | 2017-07-18 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of separate gate flash memory unit interconnection |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712981A (en) * | 2019-01-02 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN109712981B (en) * | 2019-01-02 | 2020-08-25 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN111415937A (en) * | 2020-05-13 | 2020-07-14 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN111415937B (en) * | 2020-05-13 | 2023-04-25 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
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