CN108804508A - A kind of method and system of storage input picture - Google Patents
A kind of method and system of storage input picture Download PDFInfo
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- CN108804508A CN108804508A CN201810344898.2A CN201810344898A CN108804508A CN 108804508 A CN108804508 A CN 108804508A CN 201810344898 A CN201810344898 A CN 201810344898A CN 108804508 A CN108804508 A CN 108804508A
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- input picture
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
Abstract
The present invention provides a kind of method and system of storage input picture.The present invention describes distributes one or more frame buffers in memory.Invention further describes multiple access units that input picture is divided into multiple subsets corresponding to input picture, and in frame buffer in multiple access units each access unit distribution main portion and secondary part, the secondary part of wherein at least one in frame buffer not sequentially status after its respective main portion.Invention also describes be compressed into access unit to have compressed access unit, it will each compress in access unit storage to respective main portion, it, will be in the remainder storage to respective secondary part that access unit compressed and if the size for having compressed access unit is more than the size of main portion.The invention enables the access units of compression stored in memory can be effectively completed access.
Description
Prioity claim
This application claims the priority applied as follows：Entitled " Memory Access were proposed on 04 25th, 2017
No. 62/489,588 U.S. of Efficiency Optimization for Frame Buffer Compression " faces
When patent application and on October 18th, 2017 propose entitled " Distributed Access Unit for Frame
The 15/786th, No. 908 U.S. Provisional Patent Application of Buffer Compression ", entirety are incorporated by reference this
Wen Zhong.
Technical field
And more specifically the disclosed embodiment of the present invention is related to memory technology, is related to a kind of storage input picture
Method and system.
Background technology
Background description provided herein is used as generally showing the purpose of present disclosure.Sign inventor's at present
Action had both been included in the content of the work described in the background technique part, had been not to be regarded as when being also contained in application
The various aspects of the prior art, these are both indefinite or are not considered the prior art of the present invention with implying that.
Electronic equipment, such as computer system may include one or more memories.In one example, electronics is set
Standby includes a component, such as the central processing unit (central positioned at the ic core on piece different from memory
Processing unit, CPU), memory is accessed by Memory Controller.By CPU access memory can CPU with
Heavy data traffic is generated between memory.
Invention content
In view of this, the present invention provides a kind of method and system of storage input picture, deposited with effectively completing access
The compression access unit stored in reservoir.
The aspect of the present invention provides a kind of method stored in input picture to memory.This method may include：It is depositing
One or more frame buffers are distributed in reservoir；Input picture is divided into multiple visits of multiple subsets corresponding to input picture
It asks unit, and main portion and secondary part is distributed to each access unit in multiple access units in frame buffer, wherein extremely
Few one secondary part in frame buffer not sequentially status after its respective main portion；Multiple access units are compressed into more
It is a to have compressed access unit；And will each compress in access unit in storage to respective main portion, and if pressed
The size of contracting access unit is more than the size of main portion, then stores the remainder for having compressed access unit to respective pair portion
In point.
The aspect of the present invention also provides a kind of system for storing input picture.This system includes memory, memory
Distributor and Memory Controller.Memory has one or more frame buffers；Memory distribution device is defeated for receiving
Enter image, distributes frame buffer in memory to store input picture, input picture is divided into multiple corresponding to input figure
Multiple access units of multiple subsets of picture, and main portion and secondary part are distributed to each access unit in frame buffer,
In at least one secondary part in frame buffer not sequentially status after its respective main portion；And Memory Controller is used
In the multiple instruction in response to memory distribution device, will each compress in access unit storage to respective main portion, and
And if the size for having compressed access unit is more than the size of main portion, the remainder storage for having compressed access unit is arrived
In respective pair part.
The optional aspect of the present invention can provide a kind of non-transitory computer-readable medium, be stored with computer-readable finger
It enables, when processing circuit executes computer-readable instruction, processing circuit executes a method, and this method includes：Divide in memory
With one or more frame buffers；
Input picture is divided into multiple access units of multiple subsets corresponding to input picture, and in frame buffer
Main portion and secondary part are distributed to each access unit in multiple access units, the secondary part of wherein at least one is in frame buffer
In not sequentially status after its respective main portion；Multiple access units are compressed into and multiple have compressed access unit；It will be every
It is a to have compressed in access unit storage to respective main portion, and if the size for having compressed access unit is more than main portion
Size, then will be in the remainder storage to respective secondary part that compress access unit.
The present invention is compressed by giving each access unit to distribute main portion and secondary part in memory in access unit
Later, access unit storage will have been compressed to main portion, in the case where the size of main portion is less than and has compressed access unit, also
The remainder for having compressed access unit is stored to secondary part so that compressed access unit and effectively completed access.
Description of the drawings
It will be described in detail in conjunction with following attached drawing to being provided as exemplary various embodiments of the present invention, wherein
The identical element of identical symbolic indication, and wherein：
Fig. 1 is the example block diagram of storage system according to the ... of the embodiment of the present invention；
Fig. 2 is example data structure according to the ... of the embodiment of the present invention；
Fig. 3 is three exemplary superblocks in three frame buffers according to the ... of the embodiment of the present invention；
Fig. 4 is three exemplary superblocks in three frame buffers according to the ... of the embodiment of the present invention；
Fig. 5 is two exemplary superblocks in two frame buffers according to the ... of the embodiment of the present invention；
Fig. 6 is optional frame buffer example according to the ... of the embodiment of the present invention；
Fig. 7 is the flow chart for describing exemplary flow according to the ... of the embodiment of the present invention.
Specific implementation mode
Fig. 1 shows the example block diagram of storage system 100 according to the ... of the embodiment of the present invention.As shown, storage
Device system 100 may include memory distribution device 110, Memory Controller 120 and memory 130.Memory 130 can wrap
Include frame buffer 131.Storage system 100 is used to input picture being divided into one or more access units, and will each
Compression access unit (compressed access unit) stores being distributed into frame buffer 131 and is used for respective visit
Ask the main portion (main portion) of unit and secondary part (secondary portion).
Storage system 100 can be any suitable system for storing data.In one embodiment, memory
System 100 is electronic equipment, such as desktop computer, tablet computer, smart mobile phone, wearable device, intelligence TV, video camera, camera shooting
Video recorder (camcorder), media player etc..In an example embodiment, storage system 100 can also include other
Component accesses the data stored in memory 130.For example, other assemblies may include CPU 141, image processing unit
(graphics processing unit, GPU) 142, it media engine 143, display circuit 144, image processor 145, regards
Frequency codec 146 etc..
In one embodiment, memory 130 can have and be demarcated by memory based on page size or channel segmentation
Memory block (memory block) sequence that line (memory boundary) is separated, for example, every 32 bytes, 64 words
At section, 128 bytes, 256 bytes, 512 byte 1K bytes, 2K bytes or 4K bytes.Between two adjacent lines of demarcation of access
The a certain number of data stored in memory block in accessing across two memory blocks in memory line of demarcation than separating
The data of the identical quantity of storage are more effective.Therefore, when the initial address of data is aligned with memory line of demarcation, memory
Another component that data in 130 can be stored by system 100 effectively accesses.It is to deposit that memory line of demarcation, which is formed in address,
At the multiple of reservoir block size.In one embodiment, memory block size can accommodate a certain number of data, can be
It is ordered with single or several precharge with the read/write command that happens suddenly between memory 130 and the other assemblies of other storage systems 100
It enables and the sequence form of activation command is transmitted quickly even with low-speed communications.Memory block size can be based on memory 130 and access memory 130
Storage system 100 other assemblies characteristic and selected, such as page size and memory 130 channel segmentation, and
The framework and operation mode of the other assemblies of the storage system 100 of memory 130 and access memory 130.
Memory distribution device 110 is for receiving input picture and being divided into one or more access units.Storage
Device distributor 110 is additionally operable to the part of memory 130 distributing to input picture, such as frame buffer 131, and in frame buffer
In device 131 two memory portions, i.e. main portion and secondary part are distributed to each access unit.In one example, frame buffer
The initial address of device 131 can be aligned with memory line of demarcation, for example, 0 byte.Memory distribution device 110 is every for compressing
A access unit, and access unit storage will have each been compressed to respective main portion, if having compressed the size of access unit
More than the size of main portion, then its respective secondary part is arrived into the remainder storage for having compressed access unit.Implement at one
In example, memory distribution device 100 can be integrated in any component for accessing the data stored in memory 130, example
Such as the one or more components of storage system 100 comprising CPU 141, GPU142, media engine 143, display circuit
144, image processor 145, Video Codec 146 etc..
In one embodiment, main portion can have the initial address being aligned with memory line of demarcation and be memory block
One times of size or more times of size.Therefore, being stored in the data of main portion can be efficiently accessed.Optionally, work as principal part
When the size divided is less than memory block size, each main portion can be located in respective memory block, and one or more main
Partial initial address can be aligned with one or more memory lines of demarcation.
The size of secondary part can be a part for memory block size.Therefore, two or more secondary part
It can be grouped together, and be stored independently of its respective main portion.Be less than when the size for having compressed access unit or
Equal to main portion size when, having compressed access unit can be stored in inside main portion completely, without using secondary part.
In this way, because main portion can be efficiently accessed, it is possible to effectively complete access and compress access unit.
In another embodiment, at least one of secondary part is not to be located successively in its respective master in frame buffer
After part, this include main portion have be more than its respectively pair part address opposite sequence.
Memory Controller 120 is used to manage the memory access from memory distribution device 110 to memory 130.It deposits
Memory controller 120 can be used for receiving the request for coming from memory distribution device 110, will compress access unit storage
To respective main portion in the frame buffer 131 of memory 130 and secondary part.Based on these requests, Memory Controller 120 can
It is ordered with being sent to memory 130 with instruction, access unit storage will have been compressed to respective main portion in frame buffer 131
With secondary part.Memory Controller 120 can be used for dispatching and caching these requests etc..
Memory 130 can be any suitable equipment for storing data.In one embodiment, memory 130
Including dynamic RAM (dynamic random access memory, DRAM) type memory module, for example,
Double data rate synchronous dram (double data rate synchronous DRAM, DDR SDRAM), double data rate are double
Synchronous dram (double data rate two synchronous DRAM, DDR2 SDRAM), double data rate three synchronize
DRAM (double data rate three synchronous DRAM, DDR3SDRAM), four synchronous dram of double data rate
(double data rate four synchronous DRAM, DDR4SDRAM), low-power DDR SDRAM (low power
DDR SDRAM, LPDDR SDRAM) etc..
In one embodiment, storage system 100 can be system on chip (system-on chip, SOC), wherein institute
There is component to be located on monolithic integrated optical circuit (integrated circuit, IC) chip.In addition, such as CPU 141, GPU 142,
Media engine 143, display circuit 144, image processor 145 and Video Codec 146 other assemblies can also include
In identical monolithic IC chip.Optionally, the component in storage system 100 can be distributed across several IC.For example, memory
Distributor 110, Memory Controller 120, memory 130 and storage system 100 other assemblies can be located at multiple IC
On chip.In addition, memory distribution device 110 can be integrated in any group of the data stored in access memory 130
In part, for example, storage system 100 one or more components comprising it is CPU 141, GPU 142, media engine 143, aobvious
Show circuit 144, image processor 145, Video Codec 146 etc..
During operation, input picture can be received by memory distribution device 110.Memory distribution device 110 can be with
Input picture is divided into one or more access units.In addition, memory distribution device 110 can be by the portion of memory 130
Point, such as frame buffer 131, distribute to input picture.Two memory portions, i.e. main portion and secondary part, are assigned to frame
Each access unit in buffer 131.Under the instruction of memory distribution device 110, Memory Controller 120 can will
It compresses access unit storage and arrives its respective main portion, and the secondary part depending on dimensional conditions.Main portion can have
The initial address being aligned with memory line of demarcation and one times or more times of the size for memory block size.The size of secondary part
It can be a part for memory block size.Therefore, two or more secondary part can be grouped together, and solely
Its respective main portion is stood on to be stored.When the size for having compressed access unit is less than or equal to the size of main portion,
Compression access unit can be stored in inside main portion completely, without using secondary part.In this way, visit can be effectively completed
It asks and has compressed access unit.
Fig. 2 is example data structure 200 according to the ... of the embodiment of the present invention, and it illustrates be divided into the defeated of access unit
Enter image 210, frame buffer 231A and frame buffer 231B.As shown, input picture 210 can be divided into the visit of N × M
Ask cell array.Inside the array, the size of access unit depends on the quantity of pixel and pixel position in this access unit
Deep (pixel bit-depth).Pixel locating depth is the digit of the pixel for designated color, such as 10 or 12, point
It Dui Yingyu not 1024 colors or 4049 colors.In one example, the quantity of pixel can depend in access unit
Compression method used in memory distribution device 110, such as the size of compression unit depend on being operated with which compression method.
For example, the size of compression unit can be 4 × 4 pixels, 8 × 8 pixels, 16 × 4 pixels, 16 × 8 pixels, 16 × 16 pixels etc..
Access unit can have one or more compression units.
Frame buffer 231A shows the example frame buffer architecture for storing input picture.Frame buffer can be
Memory has addressable position for storing data.Addressable position in memory can be combined into have and deposit
The memory block of reservoir block size.As described above, memory block size can be based on memory 130 and access memory 130
The characteristic of the other assemblies of storage system 100 and selected, such as page size and memory 130 channel segmentation, Yi Jicun
The framework and operation mode of the other assemblies of the storage system 100 of reservoir 130 and access memory 130.In one example,
Memory block size can be selected as 32 bytes, 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1K bytes, 2K bytes,
4K bytes etc..For example, memory 130 can be DDR3SDRAM equipment, and retrieved in data from memory 130.Memory block
Size is data volume, can be retrieved from memory 130 in the single read cycle.Specifically, when data-bus width and prominent
When hair length (burst length) is respectively 64 (i.e. 8 bytes) and 4, memory block size can be 32 bytes.Another
In example, memory block size can be determined by the 142 cache memory line of CPU 141 or GPU of access memory
For 64 bytes or 128 bytes etc..In the figure 2 example, memory block size is 64 bytes, and therefore in frame buffer 231A
In frame buffer 231B, 250 (1) -250 (n) of memory line of demarcation is located at 0 byte, 64 bytes, 128 bytes, 192 bytes etc.
Place.
Main portion and secondary part can be assigned to each access unit.In one embodiment, the size of main portion can
With depending on the compressibility of input picture, compression method, memory block size etc..In addition, in one embodiment, main portion
Size can be equal to the size of access unit with the summation of the size of secondary part.Similarly, the size of main portion and secondary part
Size ratio can depend on input picture compressibility, compression method, memory block size etc..For example, when accessing
When unit can be compressed into smaller szie, smaller main portion has compressed access unit to store enough, and respective pair
Part can remain sky so that the ratio smaller of the size of main portion and the size of secondary part.For example, the size of main portion with
The ratio of the size of secondary part can be 2,4 or 8 etc..
In addition, main portion can have the initial address that is aligned with memory line of demarcation and to store the multiple of block size
Size so that being stored in the data of main portion can be efficiently accessed.In the figure 2 example, main portion 221 (1) -221 (3)
Size can be selected to the storage block size with 64 bytes, and the initial address of main portion 221 (1) -221 (3) point
It is not aligned with memory line of demarcation 250 (1) -250 (3).The size of respective pair part 241 (1) -241 (3) can be selected to
Less than 64 bytes, such as 32 bytes.
Frame buffer 231B is shown has compressed showing when access unit 261-263 is stored when of various sizes
Example.Its respective main portion 221 (1) -221 (3) and secondary part 241 can be stored in by having compressed access unit 261-263
(1)-241(3).In the figure 2 example, the size for having compressed access unit 261 is less than the memory block size of 64 bytes.Cause
This, having compressed access unit 261 can have been stored in main portion 221 (1), and secondary part 241 (1) remains sky.It has pressed
The size of contracting access unit 262 is equal to the memory block size of 64 bytes.Therefore, having compressed access unit 262 can be in principal part
Divide in 221 (2) and has been stored, and secondary part 241 (2) remains sky.However, the size for having compressed access unit 263 is more than 64
The memory block size of byte.Therefore, main portion 221 (3) can be inserted by having compressed the first part of access unit 263, and
The second part or remainder for compressing access unit 263 can be stored in secondary part 241 (3).
In various embodiments, the size of the size of access unit, the size of main portion and secondary part can be selected, and
Constant is remained for input picture.On the other hand, multiple input image, for example, video sequence frame, can be by memory
System 100 stores.The size of the size of access unit, the size of main portion and secondary part can be selected for each list
Therefore a input picture can dynamically change from an input picture to another input picture.
Main portion and secondary part can be arranged on according to various layouts in frame buffer 131.Fig. 3-Fig. 5, which is shown, to be shown
Example layout comprising the duplication model of main portion and secondary part in a periodic manner, wherein minimum repetitive unit is superblock.
Therefore, the main portion in frame buffer 131 and secondary part can be with for example, be arranged by sequentially placing superblock adjacent to each other
Row.In one embodiment, the size of superblock can be the multiple of memory block size.
Fig. 3 is three exemplary superblock 341A- in three frame buffer 331A-331C according to the ... of the embodiment of the present invention
341C.Superblock 341A-341C shares identical characteristic, wherein super all secondary parts in the block are combined into secondary part group,
Positioned at the centre of respective superblock.The initial address of main portion is aligned with memory line of demarcation.The size of secondary part group is storage
One times or more times of device block size, and the first secondary part of secondary part group is aligned with memory line of demarcation.
With reference to superblock 341A, access unit is dimensioned to 160 bytes, and memory block is dimensioned to 128
Byte, and main portion and the size of secondary part are respectively arranged to 128 bytes and 32 bytes.As shown, super block models tool
Have including four secondary part (i.e. S0-S3) secondary part group, be inserted in the first principal part grouping (i.e. M0-M1) and the second principal part
It is grouped (i.e. M2-M3) between.The size of superblock 341A is 5 times (i.e. 640 bytes) of memory block size.Superblock 341A's
Memory line of demarcation is located at 0 byte, 128 bytes, 256 bytes, 384 bytes, 512 bytes and 640 bytes, all main portions
M0-M3Initial address be aligned respectively with the memory line of demarcation at 0 byte, 128 bytes, 384 bytes and 512 bytes.It is secondary
Size of the part group with 128 bytes, the first pair part S0It is aligned with the memory line of demarcation positioned at 256 bytes.
With reference to superblock 341B, access unit is dimensioned to 192 bytes, and memory block is dimensioned to 128
Byte, and main portion and the size of secondary part are respectively arranged to 128 bytes and 64 bytes.As shown, super block models tool
Have including four secondary part (i.e. S0-S3) secondary part group, be inserted in the first principal part grouping (i.e. M0-M1) and the second principal part
It is grouped (i.e. M2-M3) between.The size of superblock 341B is 6 times (i.e. 768 bytes) of memory block size.Superblock 341B's
Memory line of demarcation is located at 0 byte, 128 bytes, 256 bytes, 384 bytes, 512 bytes, 640 bytes and 768 bytes, owns
Main portion M0-M3Initial address respectively with the memory line of demarcation at 0 byte, 128 bytes, 512 bytes and 640 bytes
Alignment.Secondary size of the part group with 256 bytes, the first pair part S0It is aligned with the memory line of demarcation positioned at 256 bytes.
With reference to superblock 341C, access unit is dimensioned to 384 bytes, and memory block is dimensioned to 256
Byte, and main portion and the size of secondary part are respectively arranged to 256 bytes and 128 bytes.As shown, super block models tool
Have including two secondary part (i.e. S0-S1) secondary part group, be inserted in the first main portion M0With the second main portion M1Between.
The size of superblock 341C is 3 times (i.e. 768 bytes) of memory block size.The memory line of demarcation of superblock 341C is located at 0
At byte, 256 bytes, 512 bytes and 768 bytes, main portion M0-M1Initial address respectively with the memory point positioned at 0 byte
Boundary line and positioned at 512 byte memory lines of demarcation be aligned.Secondary size of the part group with 256 bytes, the first pair part S0With position
It is aligned in the memory line of demarcation of 256 bytes.
Fig. 4 is three exemplary superblock 441A- in three frame buffer 431A-431C according to the ... of the embodiment of the present invention
441C.Superblock 441A-441C shares identical characteristic, wherein super all secondary parts in the block are combined into secondary part group,
The principal part comprising main portion is followed by be grouped.The initial address of main portion is aligned with memory line of demarcation.The size of secondary part group
It it is one times or more times of memory block size, and the first secondary part of secondary part group is aligned with memory line of demarcation.
With reference to superblock 441A, access unit is dimensioned to 192 bytes, and memory block is dimensioned to 128
Byte, and main portion and the size of secondary part are respectively arranged to 128 bytes and 64 bytes.As shown, super block models
It includes two secondary part (i.e. S that 441A, which has,0-S1) secondary part group, be followed by principal part grouping (i.e. M0-M1).Superblock 441A
Size be memory block size 3 times (i.e. 384 bytes).The memory line of demarcation of superblock 441A is located at 0 byte, 128 words
At section, 256 bytes and 384 bytes, all main portion M0-M1Initial address respectively with positioned at the memory line of demarcation of 0 byte and
It is aligned positioned at the memory line of demarcation of 128 bytes.Secondary size of the part group with 128 bytes, the first pair part S0With positioned at 256
The memory line of demarcation of byte is aligned.
With reference to superblock 441B, access unit is dimensioned to 160 bytes, and memory block is dimensioned to 128
Byte, and main portion and the size of secondary part are respectively arranged to 128 bytes and 32 bytes.As shown, super block models tool
Have including four secondary part (i.e. S0-S3) secondary part group, be followed by principal part grouping (i.e. M0-M3).The size of superblock 441B
For 5 times (i.e. 640 bytes) of memory block size.The memory line of demarcation of superblock 441B is located at 0 byte, 128 bytes, 256
At byte, 384 bytes, 512 bytes and 640 bytes, all main portion M0-M3Initial address respectively with positioned at 0 byte, 128 words
Memory line of demarcation alignment at section, 256 bytes and 384 bytes.Secondary size of the part group with 256 bytes, the first secondary part
S0It is aligned with the memory line of demarcation at 512 bytes.
With reference to superblock 441C, access unit is dimensioned to 320 bytes, and memory block is dimensioned to 128
Byte, and main portion and the size of secondary part are respectively arranged to 256 bytes and 64 bytes.As shown, super block models tool
Have including two secondary part (i.e. S0-S1) secondary part group, be followed by principal part grouping (i.e. M0-M1).The size of superblock 441C
For 5 times (i.e. 640 bytes) of memory block size.The memory line of demarcation of superblock 441C is located at 0 byte, 128 bytes, 256
At byte, 512 bytes and 640 bytes, all main portion M0-M1Initial address respectively at 0 byte and 256 bytes
Memory line of demarcation is aligned.Secondary size of the part group with 256 bytes, the first pair part S0With the memory positioned at 512 bytes
Line of demarcation is aligned.
Fig. 5 is two exemplary superblock 541A- in two frame buffer 531A-531B according to the ... of the embodiment of the present invention
541B.Superblock 541A-541C shares identical characteristic, and the wherein size (i.e. 128 bytes) of main portion is less than memory block size
(i.e. 256 bytes).It can need to be stored in main portion and secondary part in addition, some have compressed access unit, and some have been compressed
Access unit can have been stored in main portion.In order to allow effectively to access the pressure being stored in main portion and secondary part
Contracting access unit can be contained in corresponding to the secondary part as much as possible of main portion in identical memory block, and excellent
Selection of land, immediately following in respective main portion.For example, in superblock 541A, in its respective memory block, main portion M0Quilt
Its pair part S0It closely follows, main portion M3By its pair part S3It closely follows.
With reference to superblock 541A, access unit is dimensioned to 192 bytes, and memory block is dimensioned to 256
Byte, and main portion and the size of secondary part are respectively arranged to 128 bytes and 64 bytes.As shown, super block models tool
There is secondary part S0, it is followed by each autonomic elements M0, and pair part S3, it is followed by each autonomic elements M3.Superblock 541A's
Size is 3 times (i.e. 768 bytes) of memory block size.The memory line of demarcation of superblock 541A be located at 0 byte, 256 bytes,
At 512 bytes and 768 bytes, three main portion M0、M1And M3Initial address respectively with positioned at 0 byte, 256 bytes and 512 words
Memory line of demarcation alignment at section.Main portion M2It is not aligned with memory line of demarcation, but main portion M2Positioned at 256 bytes with
Inside single memory block between 512 bytes.
With reference to superblock 541B, access unit is dimensioned to 192 bytes, and memory block is dimensioned to 256
Byte, and main portion and the size of secondary part are respectively arranged to 128 bytes and 64 bytes.As shown, super block models tool
It is followed by its main portion M0Secondary part S0, and it is followed by its main portion M1Secondary part S1.The size of superblock 541B is
3 times (i.e. 768 bytes) of memory block size.The memory line of demarcation of superblock 541A is located at 0 byte, 256 bytes, 512 words
At section and 768 bytes, three main portion M0、M1And M2Initial address respectively at 0 byte, 256 bytes and 512 bytes
Memory line of demarcation alignment.Main portion M3It is not aligned with memory line of demarcation, but main portion M3Positioned at 512 bytes and 768 words
Inside single memory block between section.
Fig. 6 shows optional frame buffer example according to the ... of the embodiment of the present invention.By having two groups, i.e. principal part is grouped
With secondary part group, the main portion of frame buffer 631A and frame buffer 631B and secondary part, wherein principal part grouping packet can be arranged
It includes and sequentially places all main portions adjacent to each other, and secondary part group includes sequentially placing all pair portions adjacent to each other
Point.In one embodiment, the size of main portion is one times or more times of memory block size, and the initial address of main portion can be with
It is aligned with memory line of demarcation.Principal part grouping can be placed with to be organized adjacent with secondary part, or can partly be separated with secondary.
As shown in frame buffer 631A, access unit is dimensioned to 80 bytes, and memory block is dimensioned to
64 bytes, and main portion and the size of secondary part are respectively arranged to 64 bytes and 16 bytes.Principal part grouping includes all principal parts
Point.As shown, main portion is placed with mutually adjacent, and there is initial address, and positioned at 0 byte, 64 bytes, 128 words
The continuous memory line of demarcation of section, 192 bytes, 256 bytes etc. is aligned.Secondary part group includes all secondary parts.First is secondary
Part S0Can have the initial address that is aligned with memory line of demarcation, for example, with the memory line of demarcation at 512 bytes
Alignment.
As shown in frame buffer 631B, access unit is dimensioned to 160 bytes, and memory block is dimensioned to
128 bytes, and main portion and the size of secondary part are respectively arranged to 128 bytes and 32 bytes.Principal part grouping includes all masters
Part.As shown, main portion is placed with mutually adjacent, and there is initial address, and positioned at 0 byte, 128 bytes, 256
The continuous memory line of demarcation of byte, 384 bytes, 512 bytes etc. is aligned.Secondary part group includes all secondary parts.First
Secondary part S0There can be the initial address being aligned with memory line of demarcation, such as demarcate with the memory at 4096 bytes
Line is aligned.
In superblock and frame buffer as shown in figures 3 to 6, at least one secondary part is not that sequence is located at it respectively
Main portion after.
In one embodiment, the initial address of superblock and frame buffer can demarcate with the memory of memory 130
Line is aligned, such as at 0 byte as shown in figures 3 to 6.
Although exemplary superblock and frame buffer are as shown in figures 3 to 6, it should be understood that in order to meet different storages
Device uses scene, and the deformation of the deformation of super block models, position of superblock in frame memory etc. is possible.
During operation, when main portion and secondary part are placed on according to layout in frame buffer 131, such as such as Fig. 3-
It is laid out shown in Fig. 6, having compressed access unit can be stored in respective main portion.For example, having compressed access unit
It can be stored in respective main portion, and if desired, be stored in respective secondary part.List is accessed when having compressed
When the size of member is equal to or less than the size of each autonomic elements, respective principal part can be stored in completely by having compressed access unit
In point, and corresponding secondary part can remain sky.
Fig. 7 shows the flow chart for describing exemplary flow 700 according to the ... of the embodiment of the present invention.In one example, it flows
Journey 700 is executed by the storage system 100 in Fig. 1.Flow starts from step S701 and proceeds to step S710.
In step S710, input picture is divided into one or more access unit, such as N × M as shown in Figure 2
The access unit of array.In one example, memory distribution device 110 is used to input picture being divided into the access list of array
Member.Input picture can be video frame, photographs, graph image, animated image etc..Such as video frame can be that video compiles solution
Reference frame used in code device 146.Subsequent flow proceeds to step S720.
In step S720, a frame buffer is distributed in memory.In one example, memory distribution device 110
For distributing frame buffer 131 in memory 130.The size of frame buffer is equal to or more than the size of input picture.?
In one embodiment, the initial address of frame buffer can be aligned with memory line of demarcation, such as the memory boundary at 0 byte
Line.
In step S730, in frame buffer to each access unit distribute two memory portions, i.e., main portion and
Secondary part.In one example, memory distribution device is used to distribute main portion to each access unit in frame buffer 131
With secondary part.In one embodiment, the size of main portion can be equal to the ruler of access unit with the summation of the size of secondary part
It is very little, for example, can be the size of unpressed access unit.In one embodiment, the size of main portion can depend on defeated
Enter compressibility, compression method, the memory block size etc. of image.In addition, in one embodiment, size and the pair portion of main portion
The ratio for the size divided can depend on compressibility, the compression method etc. of input picture.For example, when access unit can be compressed
When at smaller szie, smaller main portion is sufficiently used for storage and has compressed access unit, and respectively secondary part can remain sky,
Make the ratio smaller of the size and the size of secondary part of primary part.
Further, in one embodiment, main portion can have the initial address that is aligned with memory line of demarcation and
For one times or more times of size of memory block size so that the data stored in main portion can be efficiently accessed.
Optionally, when the size of main portion is less than memory block size, each main portion can be located at respective storage
Within device block, and one or more main portions can have the initial address being aligned with one or more memory lines of demarcation.
In one embodiment, the size of secondary part can be a part for memory block size.Therefore, two or two
A above secondary part can be grouped together as one or more secondary part groups, and separately be carried out with its respective main portion
Storage.Further, in one embodiment, the first secondary part in each respective secondary part group can have and memory
The initial address of line of demarcation alignment.
In another embodiment, in frame buffer, at least one secondary part is not sequentially to be located at its each autonomic elements
Later.
Main portion and secondary part can be arranged according to different layouts in frame buffer, such as in frame buffer 131.?
In one embodiment, layout may include the duplication model of superblock, and wherein superblock is that the minimum repetition in frame buffer is single
Member.Therefore, the main portion in frame buffer and secondary part can be with for example, be arranged by sequentially placing superblock adjacent to each other
Row.The size of superblock can be configured to the multiple of memory block size.
In one embodiment, the initial address of super main portion in the block is aligned with memory line of demarcation.In superblock
Secondary part can be combined into one or more secondary parts groups, size is the multiple of memory block size.Each pair part
The first secondary part in group can be aligned with memory line of demarcation.Some exemplary superblocks such as Fig. 3 with the above characteristics and
Shown in Fig. 4.
In another embodiment, superblock can have one or more main portions, size to be less than memory block size.
Some exemplary superblocks are as shown in Figure 5.For example, respective main portion is closely followed (for example, Fig. 5's is super in secondary part as much as possible
S in grade block 541A0It is followed by M0, and S3It is followed by M3).In another example each main portion is fully located in identical memory block.
In one embodiment, layout does not include the duplication model of superblock.On the contrary, by with principal part grouping and pair portion
Grouping can arrange the main portion in frame buffer and secondary part, such as example as shown in FIG. 6.For example, principal part grouping includes
Main portion with the initial address being aligned with continuous memory line of demarcation.Secondary part group includes mutual adjacent secondary part.
First secondary part of secondary part group can be aligned with memory line of demarcation.
In step S740, access unit can be compressed into and compress access unit, deposited with access with reducing memory
The bandwidth requirement of data transmission between another equipment of reservoir.For example, in storage system 100, memory 130 can be located at
On the chip different from memory distribution device 110, memory distribution device 110 is for compressing access unit to reduce memory
The bandwidth requirement of data transmission between 130 and memory distribution device 110.Lossless compression method and compression method can be with
For compressing access unit.Lossless compression method can protect the quality of initial data, and compression method may be implemented more
More compressions.Compression method can be general compression method, method for compressing image or video-frequency compression method etc..For example, pressure
Contracting method may include run length coding, RLC (run-length encoding), the algorithm based on dictionary, Hoffman codings, contracting
Smallization (deflation), coloration sub-sampling, discrete cosine transform etc..
In step S750, the size of access unit will be compressed and be compared with the size of main portion.In an example
In, memory distribution device 110 is for having compressed the size of access unit and the size of main portion.If having compressed access
The size of unit is more than in the size of main portion, then flow proceeds to step S770.Otherwise, flow proceeds to step S760.
In step S760, it can will compress access unit and be completely stored in respective main portion, be because having compressed
The size of access unit is less than the size in or equal to main portion.In one example, Memory Controller 120 is for responding
Access unit storage, which will have been compressed, in the instruction of memory distribution device 110 arrives its respective main portion.
When the size for having compressed access unit is more than the size of main portion, flow proceeds to step S770.In step
In S770, the first part for having compressed access unit can be stored to each autonomic elements.Compressed access unit first
The size divided can be identical as the size of main portion, and inserts each autonomic elements.In one example, Memory Controller 120
Its respective master is arrived into the first part's storage for having compressed access unit for the instruction in response to memory distribution device 110
Part.
In step S780, the second part for having compressed access unit or remainder can be stored to respective pair portion
Point.Therefore, when the size for having compressed access unit is more than the size of main portion, it can will compress access unit and be stored separately
To each autonomic elements and secondary part.In one example, Memory Controller 120 is used in response to memory distribution device 110
Instruction and the remainder storage of access unit will have been compressed to respective secondary part.
Before the step S799 that flow proceeds to that flow terminates, step can be repeated to all access units
S740- steps S780.In one example, memory distribution device 110 and Memory Controller 120 are for repeating step
S740- step S780, for all access units in input picture.
In various embodiments, the size of the size of access unit, the size of main portion and secondary part can be selected, and
Constant is remained for input picture.On the other hand, multiple input image, for example, video sequence frame, can be by memory
To store.The size of the size of access unit, the size of main portion and secondary part can be selected for each individually defeated
Enter image, therefore, can dynamically change from an input picture to another input picture.
In the various examples, the function of memory distribution device 110 or memory distribution device 110 can use hardware,
Software and combinations thereof is realized.In one example, memory distribution device 110 is realized within hardware, such as processing circuit, firmly
Part may include discrete component, integrated circuit, application specific integrated circuit (application-specific integrated
One or more of circuit, ASIC) etc..In another example, the function of memory distribution can be with including being stored in meter
The software or firmware of the instruction of the readable non-transient storage media of calculation machine is realized, when these instructions are executed by processing circuit,
So that processing circuit executes respective function.
Various aspects of the invention are described as exemplary specific embodiment due to having been combined being suggested for the present invention,
These exemplary replacement, modification and variation can be made.Therefore, embodiment illustrated here is used as illustrative purpose, but does not have to
In limitation.Without departing from the scope of the claims, it can make a change.
Claims (20)
1. a kind of method of storage input picture, which is characterized in that in the input picture storage to memory, including：
One or more frame buffers are distributed in the memory；
The input picture is divided into multiple access units of multiple subsets corresponding to the input picture, and in the frame
In buffer in multiple access units each access unit distribution main portion and secondary part, pair portion described in wherein at least one
Point in the frame buffer not sequentially status after its respective main portion；
The multiple access unit is compressed into and multiple has compressed access unit；And
It will each compress in access unit in storage to respective main portion, and if the ruler for having compressed access unit
The very little size more than the main portion, then will be in the remainder storage that compress access unit to respective secondary part.
2. the method for storage input picture as described in claim 1, which is characterized in that the memory, which has by being located at, is
The a series of memory block that multiple memory lines of demarcation at multiple addresses of the multiple of memory block size are separated, and
And characteristic of the memory block size based on the memory and access the characteristic of multiple equipment of the memory and true
It is fixed.
3. the method for storage input picture as described in claim 2, which is characterized in that the size of each main portion is described
One times or more times of memory block size, and the initial address of each main portion is aligned with memory line of demarcation respectively.
4. the method for storage input picture as described in claim 2, which is characterized in that the size of each main portion is described
A part for memory block size, and each main portion is located at the inside of respective memory block.
5. the method for storage input picture as described in claim 2, which is characterized in that the size of each pair part is described
A part for memory block size, and multiple secondary parts are combined into one or more secondary part groups.
6. the method for storage input picture as described in claim 5, which is characterized in that one or more of pair parts group
Size be one times or more times of the memory block size, the initial address of the first secondary part of each secondary part group
It is aligned with memory line of demarcation.
7. the method for storage input picture as described in claim 2, which is characterized in that
Multiple main portions and secondary part are arranged with preset model, with form that size is the memory block size one times or
More times of superblock；And the multiple main portion in the frame buffer and the multiple secondary part pass through sequence and place phase
Mutually adjacent multiple superblocks arrange.
8. the method for storage input picture as described in claim 2, which is characterized in that the memory block size is selected
For 32 bytes, 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1K bytes, 2K bytes or 4K bytes.
9. the method for storage input picture as described in claim 1, which is characterized in that the input picture is static image
Or video frame.
10. a kind of system of storage input picture, which is characterized in that including：
Memory has one or more frame buffers；
It is described to store to distribute frame buffer for receiving the input picture in the memory for memory distribution device
The input picture is divided into multiple access units of multiple multiple subsets corresponding to the input picture by input picture,
And main portion and secondary part are distributed to each access unit in the frame buffer, secondary part is in institute described in wherein at least one
State in frame buffer not sequentially status after its respective main portion；And
Memory Controller will each compress access unit for the multiple instruction in response to the memory distribution device
It stores in respective main portion, and if the size for having compressed access unit is more than the size of the main portion,
It will be in the remainder storage that access unit compressed to respective secondary part.
11. such as the system of the storage input picture in claim 10, which is characterized in that the memory has a series of deposit
Reservoir block, the memory block by multiple memory lines of demarcation positioned at multiple addresses of the multiple for memory block size every
It opens, also, the characteristic of multiple devices of characteristic of the memory block size based on the memory and the access memory
And it determines.
12. such as the system of the storage input picture in claim 11, which is characterized in that the memory distribution device is used for will
Be sized to the memory block size one times of each main portion or more times, and by the initial address of each main portion
It is aligned with memory line of demarcation.
13. such as the system of the storage input picture in claim 11, which is characterized in that the memory distribution device is used for will
The part for being sized to the memory block size of each main portion, and each main portion is placed on respective memory
The inside of block.
14. such as the system of the storage input picture in claim 11, which is characterized in that the memory distribution device is used for will
The part for being sized to the memory block size of each pair part, and multiple secondary parts are combined into one or more
Secondary part group.
15. such as the system of the storage input picture in claim 14, which is characterized in that the memory distribution device is for selecting
The size for selecting one or more secondary part groups is one times or more times of the memory block size, and will each secondary part
The initial address of the first secondary part of group is aligned with memory line of demarcation.
16. such as the system of the storage input picture in claim 11, which is characterized in that the memory distribution device be used for
Preset model arranges multiple main portions and secondary part, with the super of form that size is the memory block size one times or more times
Grade block, and mutually adjacent multiple superblocks are placed in the frame buffer.
17. such as the system of the storage input picture in claim 11, which is characterized in that the memory distribution device is for true
The fixed memory block size is 32 bytes, 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1K bytes, 2K bytes or 4K
Byte.
18. such as the system of the storage input picture in claim 10, which is characterized in that the memory is located at and the storage
The different ic core on piece of device distributor.
19. such as the system of the storage input picture in claim 10, which is characterized in that the memory distribution device is integrated
In Video Codec.
20. a kind of non-transitory computer-readable medium, which is characterized in that be stored with computer-readable instruction, held in processing circuit
When the row computer-readable instruction, the processing circuit executes a method, the method includes：
One or more frame buffers are distributed in the memory；
The input picture is divided into multiple access units of multiple subsets corresponding to the input picture, and in the frame
In buffer in multiple access units each access unit distribution main portion and secondary part, pair portion described in wherein at least one
Point in the frame buffer not sequentially status after its respective main portion；
The multiple access unit is compressed into and multiple has compressed access unit；
It will each compress in access unit storage to respective main portion, and if the size for having compressed access unit
It, then will be in the remainder storage that compress access unit to respective secondary part more than the size of the main portion.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762489588P | 2017-04-25 | 2017-04-25 | |
| US62/489,588 | 2017-04-25 | ||
| US15/786,908 | 2017-10-18 | ||
| US15/786,908 US20180107616A1 (en) | 2016-10-18 | 2017-10-18 | Method and device for storing an image into a memory |
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| Publication Number | Publication Date |
|---|---|
| CN108804508A true CN108804508A (en) | 2018-11-13 |
| CN108804508B CN108804508B (en) | 2022-06-07 |
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| CN201810344898.2A Active CN108804508B (en) | 2017-04-25 | 2018-04-17 | Method and system for storing input image |
| CN201810373709.4A Expired - Fee Related CN108833922B (en) | 2017-04-25 | 2018-04-24 | Method for accessing frame buffer, method and device for processing access unit |
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| US4772956A (en) * | 1987-06-02 | 1988-09-20 | Eastman Kodak Company | Dual block still video compander processor |
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| US7106909B2 (en) * | 2001-12-25 | 2006-09-12 | Canon Kabushiki Kaisha | Method and apparatus for encoding image data in accordance with a target data size |
| CN101212680B (en) * | 2006-12-30 | 2011-03-23 | 扬智科技股份有限公司 | Image data storage access method and system |
| US20140219361A1 (en) * | 2013-02-01 | 2014-08-07 | Samplify Systems, Inc. | Image data encoding for access by raster and by macroblock |
| CN105472442B (en) * | 2015-12-01 | 2018-10-23 | 上海交通大学 | Compressibility is cached outside a kind of piece for ultra high-definition frame rate up-conversion |
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2018
- 2018-04-17 CN CN201810344898.2A patent/CN108804508B/en active Active
- 2018-04-18 TW TW107113191A patent/TW201839714A/en unknown
- 2018-04-24 CN CN201810373709.4A patent/CN108833922B/en not_active Expired - Fee Related
- 2018-04-24 TW TW107113842A patent/TW201840177A/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US4772956A (en) * | 1987-06-02 | 1988-09-20 | Eastman Kodak Company | Dual block still video compander processor |
| GB2457262A (en) * | 2008-02-08 | 2009-08-12 | Linear Algebra Technologies | Compression / decompression of data blocks, applicable to video reference frames |
| CN101499097A (en) * | 2009-03-16 | 2009-08-05 | 浙江工商大学 | Hash table based data stream frequent pattern internal memory compression and storage method |
| CN102740074A (en) * | 2012-06-05 | 2012-10-17 | 沙基昌 | Video data compressing/decompressing method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201840177A (en) | 2018-11-01 |
| CN108804508B (en) | 2022-06-07 |
| TW201839714A (en) | 2018-11-01 |
| CN108833922A (en) | 2018-11-16 |
| CN108833922B (en) | 2020-12-18 |
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