CN108737296B

CN108737296B - Data transmission method, device and network equipment

Info

Publication number: CN108737296B
Application number: CN201710889139.XA
Authority: CN
Inventors: 郭道荣
Original assignee: Hangzhou H3C Technologies Co Ltd
Current assignee: Hangzhou H3C Technologies Co Ltd
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2020-12-04
Anticipated expiration: 2037-09-27
Also published as: CN108737296A; WO2019062656A1; JP2020535739A; EP3675439B1; JP6978596B2; EP3675439A4; US11252111B2; EP3675439A1; US20200267099A1

Abstract

The application provides a data transmission method, a data transmission device and network equipment, wherein the method comprises the following steps: determining an interface board and a logic channel corresponding to first data to be sent; if the logic channel has the capacity of sending the first data, adding header information to the first data to obtain second data, and storing the second data into a buffer area corresponding to the logic channel; the header information comprises an interface board identifier and a logic channel identifier; and reading the second data from the buffer area, acquiring an interface board identifier and a logic channel identifier from the read header information of the second data, removing the read header information of the second data to obtain first data, and sending the obtained first data to an interface board corresponding to the interface board identifier. By the technical scheme, the problem that the rate of the main control board is not matched with that of the interface board can be solved, and the problem of packet loss of the interface board is avoided.

Description

Data transmission method, device and network equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to a data transmission method, an apparatus, and a network device.

Background

The network device (such as a router, a switch, etc.) generally includes a main control board and an interface board, and the main control board is connected to the interface board through an ethernet interface, because the transmission rate of the ethernet interface is very fast, such as the transmission rate of the GE level, by using the ethernet interface, the occupation of a Central Processing Unit (CPU) can be reduced, the concurrency of a multi-core CPU is improved, and the main control board does not become a performance bottleneck.

However, the interface board is connected to other devices through non-ethernet interfaces (e.g., an E1 interface, a T1 interface, an asynchronous serial port, a synchronous serial port, an AM (Analog Modem) interface, etc.), and the transmission rate of the non-ethernet interfaces is relatively slow, e.g., 100M-level transmission rate, so that the rate at which the main control board sends data to the interface board is severely mismatched with the rate at which the interface board sends data to other devices, and thus after the interface board receives a large amount of data through the ethernet interfaces, only a small amount of data is sent through the non-ethernet interfaces, resulting in packet loss.

Disclosure of Invention

The application provides a data transmission method, which comprises the following steps:

determining an interface board and a logic channel corresponding to first data to be sent; if the logic channel has the capacity of sending the first data, adding header information to the first data to obtain second data, and storing the second data to a buffer area corresponding to the logic channel; wherein, the header information includes an interface board identifier of the interface board and a logic channel identifier of the logic channel;

and reading the second data from the buffer area, acquiring an interface board identifier and a logic channel identifier from the read header information of the second data, removing the read header information of the second data to obtain first data, and sending the obtained first data to an interface board corresponding to the interface board identifier.

After determining the interface board and the logic channel corresponding to the first data to be sent, the method further includes:

acquiring the length of the residual resource of the logic channel; if the length of the residual resource is greater than or equal to the length of first data, determining that the logic channel has the capacity of sending the first data;

if the logical channel has the capacity of sending the first data, updating the length of the residual resource of the logical channel to be the difference value between the length of the current residual resource and the length of the first data;

after the reading of the second data from the buffer, the method further includes: and updating the residual resource length of the logic channel corresponding to the buffer area to be the sum of the current residual resource length and the length of the first data.

The logic channel corresponds to a sending window, and the length of the sending window is the same as that of a buffer zone corresponding to the logic channel; the parameters of the sending window comprise a window starting position, a window ending position and a window occupying position; the length between the window occupation position and the window ending position is the length of the residual resource of the logic channel;

updating the length of the remaining resource of the logical channel to the difference between the current length of the remaining resource and the length of the first data, including: moving the window occupation position to the direction of the window ending position by a specified length;

updating the remaining resource length of the logical channel corresponding to the buffer to the sum of the current remaining resource length and the length of the first data, including: moving the window occupation position to the direction of the window starting position by a specified length; or, moving the window starting position to the direction of the window occupying position by a specified length, and moving the window ending position to the moving direction of the window starting position by the specified length;

wherein the specified length is a length of the first data.

The process of sending the obtained first data to the interface board corresponding to the interface board identifier includes:

acquiring a first rate used when the interface board sends first data through the logic channel;

determining a second rate used when first data is sent to the interface board according to the first rate;

sending the obtained first data to an interface board corresponding to the interface board identification based on a second rate;

wherein the second rate is less than the first rate.

The process of determining a second rate used when sending the first data to the interface board according to the first rate specifically includes:

determining a forwarding mode of the interface board according to the characteristic data, and processing the first data through the forwarding mode to obtain third data with a first speed; and in the process of obtaining the third data of the first rate, determining the rate of the first data for processing, and determining the determined rate as the second rate.

The present application provides a data transmission apparatus, the apparatus comprising:

the determining module is used for determining an interface board and a logic channel corresponding to first data to be sent;

the processing module is used for adding header information to the first data to obtain second data when the logic channel has the capacity of sending the first data; wherein, the header information includes an interface board identifier of the interface board and a logic channel identifier of the logic channel;

the storage module is used for storing the second data to a buffer area corresponding to the logic channel;

the reading module is used for reading the second data from the buffer area, acquiring an interface board identifier and a logic channel identifier from the read header information of the second data, and removing the read header information of the second data to obtain first data;

and the sending module is used for sending the obtained first data to the interface board corresponding to the interface board identifier.

The determining module is further configured to obtain a remaining resource length of the logic channel after determining an interface board and a logic channel corresponding to first data to be sent; if the length of the residual resource is larger than or equal to the length of first data, determining that the logic channel has the capacity of sending the first data;

the processing module is further configured to update the length of the remaining resource of the logical channel to a difference between the current length of the remaining resource and the length of the first data when the logical channel has the capability of sending the first data; and after the reading module reads the second data from the buffer area, updating the remaining resource length of the logic channel corresponding to the buffer area to the sum of the current remaining resource length and the length of the first data.

the processing module is specifically configured to, in a process of updating the remaining resource length of the logical channel to a difference between the current remaining resource length and the length of the first data, move the window occupation position by a specified length in a direction of the window end position;

in the process of updating the remaining resource length of the logic channel corresponding to the buffer area to the sum of the current remaining resource length and the length of the first data, moving the window occupation position to the direction of the window starting position by a specified length; or, moving the window starting position to the direction of the window occupying position by a specified length, and moving the window ending position to the moving direction of the window starting position by the specified length;

wherein the specified length is a length of the first data.

The sending module is specifically configured to, in a process of sending the obtained first data to an interface board corresponding to the interface board identifier, obtain a first rate used when the interface board sends the first data through the logic channel; determining a second rate used when first data is sent to the interface board according to the first rate; sending the obtained first data to an interface board corresponding to the interface board identification based on the second rate;

wherein the second rate is less than the first rate.

The sending module is specifically configured to, in a process of determining a second rate used when sending first data to the interface board according to the first rate, determine a forwarding manner of the interface board according to feature data, and process the first data in the forwarding manner to obtain third data at the first rate; and in the process of obtaining the third data of the first rate, determining the rate of the first data for processing, and determining the determined rate as the second rate.

The present application provides a network device, the network device comprising:

the first speed limiting device is used for determining an interface board and a logic channel corresponding to first data to be sent; if the logic channel has the capacity of sending the first data, adding header information to the first data to obtain second data, and sending the second data to a second speed limiting device; wherein, the header information includes an interface board identifier of the interface board and a logic channel identifier of the logic channel;

the second speed limiting device is used for acquiring a logical channel identifier from header information of second data after the second data are received, and storing the second data into a buffer area corresponding to the logical channel identifier;

Based on the above technical solution, in the embodiment Of the present application, a plurality Of logic channels may share the processing capability Of the same main control board, and may store data in the buffer corresponding to each logic channel, and send the data in the buffer through the logic channel, so as to solve the problem Of rate mismatch between the main control board and the interface board, avoid the problem Of packet loss Of the interface board, and meet QOS (Quality Of Service) requirements.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments of the present application or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings of the embodiments of the present application.

FIG. 1 is a flow chart of a data transmission method in one embodiment of the present application;

FIG. 2 is a schematic diagram of a network device according to an embodiment of the present application;

FIGS. 3A and 3B are schematic diagrams of a basic information table in one embodiment of the present application;

3C-3F are schematic diagrams of window management in one embodiment of the present application;

FIGS. 4A and 4B are schematic diagrams of message formats in an embodiment of the present application;

FIG. 5 is a block diagram of a data transfer device according to an embodiment of the present application;

fig. 6 is a hardware configuration diagram of a network device according to an embodiment of the present application.

Detailed Description

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein is meant to encompass any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Depending on the context, moreover, the word "if" as used may be interpreted as "at … …" or "when … …" or "in response to a determination".

The embodiment of the application provides a data transmission method, which can be applied to network equipment, wherein the network equipment can comprise one or more main control boards and one or more interface boards. The main control board may be connected to the Interface board through an ethernet Interface, a PCIE (Peripheral Component Interconnect Express, high-speed Peripheral Component Interconnect standard), a Serial Peripheral Interface (SPI 4), and the like, and the Interface board may be connected to other devices through an E1 Interface, a T1 Interface, an asynchronous Serial port, a synchronous Serial port, an AM Interface, and the like. In a normal situation, the data transmission rate between the main control board and the interface board is greater than the data transmission rate between the interface board and other devices.

Fig. 1 is a schematic flow chart of a data transmission method proposed in the embodiment of the present application.

Step 101, determining an interface board and a logic channel corresponding to first data to be sent; if the logical channel has the capability of sending the first data, header information is added to the first data to obtain second data (the first data to which the header information is added may be referred to as second data for distinguishing from the first data), and the second data is stored in a buffer corresponding to the logical channel. The header information may include, but is not limited to, an interface board identifier of the interface board and a logical channel identifier of the logical channel, which is not limited thereto.

In an example, the process for "determining an interface board and a logical channel corresponding to first data to be transmitted" may include, but is not limited to: for first data to be sent, a forwarding table may be queried through destination address information (e.g., a destination IP address and/or a destination MAC address) of the first data to obtain an outgoing interface corresponding to the destination address information, where the outgoing interface corresponds to an interface board and a logical channel, where the interface board is an interface board corresponding to the first data, and the logical channel is a logical channel corresponding to the first data.

In an example, after determining the interface board and the logical channel corresponding to the first data to be sent, it may also be determined whether the logical channel has a capability of sending the first data. If yes, executing the steps of adding header information to the first data to obtain second data, and the like; if not, the first data is not sent any more, but the first data is stored in the memory, and when the logic channel has the capacity of sending the first data, the first data is read from the memory, and steps of adding header information to the first data to obtain second data are executed.

In one example, to determine whether the logical channel has the capability of sending the first data, the following method may be used: acquiring the length of the residual resource of the logic channel; if the length of the residual resource is larger than or equal to the length of first data, determining that the logic channel has the capacity of sending the first data; and if the length of the residual resource is smaller than the length of the first data, determining that the logic channel does not have the capacity of sending the first data.

Further, if the logical channel has the capability of sending the first data, the remaining resource length of the logical channel may be updated to the difference between the current remaining resource length and the length of the first data.

In one example, the process of "adding header information to the first data to obtain the second data" may include, but is not limited to, the following ways: an interface board identifier (i.e., a unique identifier of the interface board) corresponding to the interface board is determined, and a logical channel identifier (i.e., a unique identifier of the logical channel) of the logical channel is determined. Then, add header information to the first data, where the header information may include, but is not limited to, the interface board identifier and the logical channel identifier, and the first data added with the header information may be referred to as second data.

In one example, the process of "storing the second data to the buffer corresponding to the logical channel" may include, but is not limited to, the following: there may be a buffer for each logical channel, so that after the second data is obtained, the second data may be stored in the buffer for the logical channel.

Of course, in practical applications, a plurality of logical channels may also correspond to the same buffer, and therefore, after obtaining the second data, the second data may also be stored in the buffer corresponding to the logical channel.

Step 102, reading second data from the buffer, obtaining an interface board identifier and a logic channel identifier from the read header information of the second data, removing the read header information of the second data to obtain first data, and sending the obtained first data to an interface board corresponding to the interface board identifier.

In an example, after the second data is read from the buffer, the remaining resource length of the logical channel corresponding to the buffer may be updated to the sum of the current remaining resource length and the length of the first data.

In an example, to determine whether the logical channel has the capability of sending the first data, the buffer of the logical channel may also be implemented by using a window mechanism, based on which the logical channel may correspond to a sending window, and the length of the sending window is the same as the length of the buffer corresponding to the logical channel. Also, the parameters of the sending window may include, but are not limited to, a window start position, a window end position, a window occupied position; the length between the window starting position and the window ending position is the length of the sending window; the length between the window occupation position and the window ending position is the remaining resource length of the logical channel.

Based on this, the "updating the remaining resource length of the logical channel to the difference between the current remaining resource length and the length of the first data" may include: moving the window occupation position to the direction of the window ending position by a specified length; in addition, the "updating the remaining resource length of the logical channel corresponding to the buffer to the sum of the current remaining resource length and the length of the first data" may include, but is not limited to: moving the window occupying position to the direction of the window starting position by a specified length; or, the window start position is moved to the direction of the window occupation position by a specified length, and the window end position is moved to the moving direction of the window start position by a specified length. The specified length may be a length of the first data.

In an example, after reading the second data from the buffer, a first position of the second data in the buffer may also be obtained, and a second position of the window start position in the sending window is determined according to the first position; then, the window start position may also be moved to a second position in the transmission window, and the window end position may be moved according to the length of the movement of the window start position.

In an example, for the process of "acquiring the interface board identifier and the logical channel identifier from the header information of the second data and removing the header information of the second data", since the header information of the second data includes the interface board identifier and the logical channel identifier, the interface board identifier and the logical channel identifier may be acquired from the header information of the second data, and the header information of the second data may be removed, so as to obtain the first data.

In an example, the process of "sending the first data to the interface board corresponding to the interface board identifier" may include: acquiring a first rate used when the interface board sends first data through the logic channel, and determining a second rate used when the interface board sends the first data according to the first rate; sending the first data to an interface board corresponding to the interface board identification based on the second rate; the second rate is less than the first rate.

In one example, the process for determining the second rate used when sending the first data to the interface board according to the first rate may include, but is not limited to, the following ways: determining a forwarding mode of the interface board according to the characteristic data, and processing the first data through the forwarding mode to obtain third data with the first rate; and in the process of obtaining the third data of the first rate, determining the rate of the first data to be processed, and determining the determined rate as the second rate.

In an example, before "determining the forwarding manner of the interface board according to the feature data", the method may further include the following steps: the pre-configured basic information table may be queried according to the logical channel identifier to obtain a feature type identifier corresponding to the logical channel identifier, and then, feature data corresponding to the feature type identifier may be obtained. The basic information table is used for recording the corresponding relation between the logical channel identification and the characteristic type identification.

Based on the above technical solution, in the embodiment Of the present application, a plurality Of logic channels may share the processing capability Of the same main control board, and may store data in the buffer corresponding to each logic channel, and may send data in the buffer through the logic channel, so as to solve the problem Of rate mismatch between the main control board and the interface board, avoid the problem Of packet loss Of the interface board, and meet QOS (Quality Of Service) requirements.

The above scheme is described in detail below with reference to specific application scenarios. Referring to fig. 2, a networking schematic diagram of the application scenario is shown, and fig. 2 illustrates, by taking the main control board 210, the interface board 231, and the interface board 232 as an example, in an actual application, the number of the interface boards may be more. In fig. 2, the first speed limiting device 212 is a newly added unit in the main control board 210, and the second speed limiting device 220 is also a newly added unit.

The second speed limiting device 220 may be disposed in the main control board, and each main control board is disposed with one second speed limiting device 220; or, the second speed limiting device 220 may also be deployed in an interface board, and each interface board is deployed with one second speed limiting device 220; alternatively, the second speed limiting device 220 may also be deployed separately, instead of being deployed in the main control board or the interface board, and the example of separately deploying one second speed limiting device 220 is illustrated in fig. 2.

The first speed limiting device 212 is a newly added unit in the main control board 210, and may be a hardware device, which is not limited to this type. If the second speed limiting device 220 is a unit newly added to the main control board 210 or the interface board, the second speed limiting device 220 may be a hardware device, and if the second speed limiting device 220 is deployed alone, the second speed limiting device 220 may be an independent single board, which is not limited to this type.

The main control board 210 may be connected to the second speed limiter 220 through an ethernet interface, PCIE, SPI4, and the like, and the second speed limiter 220 may be connected to the interface board 231/interface board 232 through an ethernet interface, PCIE, SPI4, and the like. In fig. 2, the main control board 210 is connected to the second speed limiting device 220 via an ethernet interface, and the ethernet controller 213 is used to implement the ethernet interface. In addition, the interface board 231/interface board 232 may be connected to other devices through an E1 interface, a T1 interface, an asynchronous serial port, a synchronous serial port, an AM interface, or the like.

The connection mode of the main control board 210 and the second speed limiting device 220 can be the same as the connection mode of the second speed limiting device 220 and the interface board 231/interface board 232, and the maximum data transmission rate of the main control board 210 and the second speed limiting device 220 is the same as the maximum data transmission rate of the second speed limiting device 220 and the interface board 231/interface board 232, and is greater than the maximum data transmission rate of the interface board 231/interface board 232 and other devices.

Referring to fig. 2, in the main control board 210, a processor 211(CPU) may be connected to a first speed limiting device 212 through a bus, and the first speed limiting device 212 may be connected to an ethernet controller 213 through the bus.

Referring to fig. 2, the main control board 210 may also create a logical channel, which is a transmission channel of data, for example, when the data trend is: when the CPU, the first speed limiting device 212, the ethernet controller 213, the second speed limiting device 220, and the output interface on the interface board 231/interface board 232 are connected, the logical channel may be a logical channel for "the CPU, the first speed limiting device 212, the ethernet controller 213, the second speed limiting device 220, and the output interface on the interface board 231/interface board 232", that is, the logical channel may pass through the above-mentioned devices.

In fig. 2, although the logical channel is labeled on the interface board, it does not mean that the logical channel is located on the interface board, but only the output interface of the logical channel is located on the interface board. The output interface of the logical channel may be an E1 interface, a T1 interface, an asynchronous serial port, a synchronous serial port, an AM interface, etc., which is not limited.

The output interface of the logical channel may be a logical interface or a physical interface. Different logical channels can occupy different physical interfaces, different logical channels can share the same physical interface, and one logical channel can also occupy a plurality of physical interfaces. For example, logical channel 241 occupies physical interface 1 and physical interface 2, logical channel 242 occupies physical interface 3, and logical channel 243 and logical channel 244 share physical interface 4, i.e., the data transfer rate of logical channel 241 is the sum of the data transfer rates of physical interface 1 and physical interface 2, the data transfer rate of logical channel 242 is the data transfer rate of physical interface 3, and the sum of the data transfer rates of logical channel 243 and logical channel 244 is the data transfer rate of physical interface 4.

In the process of creating a logic channel, the main control board 210 may also allocate a buffer area for each logic channel, and establish a corresponding relationship between the logic channel and the buffer area. Referring to FIG. 2, the logic channel 241 corresponds to the buffer 251, the logic channel 242 corresponds to the buffer 252, the logic channel 243 corresponds to the buffer 253, and the logic channel 244 corresponds to the buffer 254. For data that needs to be sent through the logical channel 241, the data is buffered in the buffer 251, then the data is read from the buffer 251, and finally the data is sent through the logical channel 241. For data that needs to be sent through the logical channel 242, the data is buffered in the buffer 252, then the data is read from the buffer 252, and finally the data is sent through the logical channel 242. And so on.

In the process of creating a logical channel, the main control board 210 may create a plurality of logical channels as needed, and the number of the logical channels is not limited, and the logical channel may be a logical channel for "the CPU, the first speed limiting device 212, the ethernet controller 213, the second speed limiting device 220, and the output interface on the interface board 231/232", and is not limited to this, as long as the logical channel can correspond to an output interface (located on the interface board), and the process of sending data through the logical channel is a process of sending data through the output interface.

After the logical channel is created, the main control board 210 may allocate a buffer area for the logical channel, and configure a sending window for the logical channel, where the length of the buffer area is related to the data transmission rate of the output interface corresponding to the logical channel, and the length of the sending window is the same as the length of the buffer area corresponding to the logical channel. For example, when the data transmission rate of the output interface is 56Kbits/s, the length of the buffer and the length of the transmission window are both 56K.

The first speed limiting device 212 may include a basic information table, the contents of which may include but are not limited to: interface board identification, logic channel identification, interface type, window position information, etc. Each logical channel corresponds to a basic information table, and the content of the basic information table can be shown in fig. 3A or fig. 3B, where fig. 3A is an example of a basic information table at an initial time, and fig. 3B is an example of a basic information table at a certain time.

The downlink port number is a downlink port number of the main control board, and the downlink port number is uniformly numbered in the system, and according to the downlink port number, the main control board can know through which downlink port to send data to the interface board.

The ChID is a logical channel identifier, namely the unique identifier of the logical channel. For example, the logical channel identifier may be spliced by a slot number (SlotID), a port number (PortID), and a subchannel number (subchaid) of the interface board. The slot position number occupies the highest 4 positions and can support 16 slot positions; the port number occupies the middle 6 bits and can support 64 ports; the subchannel number occupies the last 12 bits, and supports up to 4096 subchannels. Of course, the logical channel identifier formed by splicing the slot number, the port number, and the sub-channel number is only an example, and is not limited thereto.

The WanType is an interface type, and is a type of an interface corresponding to the logical channel, such as a POS, a CE1, a CPOS, an AsySer (asynchronous serial port), an E1 interface, a T1 interface, an AM interface, and the like, and the interface type is not limited.

The window position information may include WinSize, LeftEdge, RightEdge, TxEdge. LeftEdge is the left edge of the window, which may also be referred to as the window start position. The RightEdge is the right edge of the window and may also be referred to as the window end position. WinSize is the length of the transmission window, such as 128 kbytes (i.e. 0x20000), and this value indicates the maximum length allowed to be transmitted, WinSize is the same as the length of the buffer corresponding to the logical channel, and the length between LeftEdge and RightEdge is WinSize. TxEdge is an edge of currently transmitted data, which may also be referred to as a window occupation position, and when data is transmitted next time, accumulation is started from this position, for example, assuming that LeftEdge is 0, the length of the first data is 64, and after the first data is transmitted, TxEdge is 64; assuming that the length of the second data is 304, after the second data is sent, TxEdge is 368(64+304), and so on; when the TxEdge is between the leftEdge and the rightEdge, the logic channel is indicated to have the capability of transmitting data, and when the TxEdge exceeds the rightEdge, the logic channel is indicated to have no capability of transmitting data.

The second speed limiting device 220 may include a basic information table, the contents of which may include but are not limited to: interface board identification, logic channel identification, interface type, window position information, characteristic type identification, and each logic channel corresponds to a basic information table. The basic information table of the second speed limit device 220 is similar to that of the first speed limit device 212, except that: the basic information table of the second speed limiting device 220 has a plurality of feature type identifiers, where the feature type identifier may be FeatureID, and is used to index the feature table and corresponds to the FeatureID of the feature table, and further details of other contents of the basic information table are not described here.

In the application scenario, the data transmission method provided in the embodiment of the present application may include:

step a, after receiving first data to be sent, the first speed limiting device 212 determines an interface board and a logic channel corresponding to the first data. Specifically, the forwarding table may be queried through destination address information (e.g., a destination IP address and/or a destination MAC address) of the first data, so as to obtain an outgoing interface corresponding to the destination address information, where the outgoing interface corresponds to an interface board and a logical channel, where the interface board is an interface board corresponding to the first data, and the logical channel is a logical channel corresponding to the first data. Of course, the information of the interface board and the logical channel may also be notified by the processor 211, and the determination method is not limited.

Step b, the first speed limiting device 212 judges whether the logic channel has the capability of sending the first data, if so, step c is executed; if not, the first data is not sent, but the first data is stored in the memory, and step c is executed again when the logic channel has the capacity of sending the first data.

When sending data, the first speed limiting device 212 may determine whether the logical channel has the capability of sending the first data according to the window position information in the basic information table and the length of the first data. For example, when the TxEdge is still located between the LeftEdge and the RightEdge after moving the TxEdge to the right by the length of the first data, it indicates that the logical channel has the capability of transmitting the first data; when the TxEdge exceeds the rightEdge after the TxEdge moves to the right by the length of the first data, the logical channel is indicated to have no capability of sending the first data.

Further, when the logic channel has the capability of sending the first data, the first speed limiting device 212 may further adjust the position of the TxEdge according to the length of the first data and the current position of the TxEdge.

As shown in fig. 3C, at initialization, both LeftEdge and TxEdge are 0. As shown in fig. 3D, when 10 kbytes of data are transmitted, the TxEdge becomes 10K. As shown in fig. 3E, when 20 kbytes of data are transmitted, the TxEdge becomes 20K. After receiving the data completion message, if the data completion message indicates that the second speed limiting device 220 has read 12K of data from the buffer, sliding the LeftEdge to the right, for example, sliding 12K, and sliding the RightEdge to the right, for example, sliding 12K, where the schematic diagram after sliding is shown in fig. 3F.

Referring to fig. 4A, which is a schematic diagram of a data completion message, after receiving the data completion message, if the TxEdge in the data completion message is located between the LeftEdge of the window and the TxEdge of the window, sliding the window according to the TxEdge in the data completion message, for example, moving the LeftEdge in the window to the right to the TxEdge in the data completion message, and correspondingly sliding the RightEdge in the window to the right, where the lengths of the slid LeftEdge and RightEdge are WinSize. And if the TxEdge in the data completion message is not positioned between the leftEdge of the window and the TxEdge of the window, discarding the data completion message and not sliding the window any more.

In practical applications, if data is lost when the first speed limiting device 212 sends data to the second speed limiting device 220, and/or if data completion message is lost when the second speed limiting device 220 sends data completion message to the first speed limiting device 212, then: as long as data is successfully sent and a data completion message is successfully sent in the subsequent process, the window can correctly slide, the loss of sending resources can not be caused, and the sending stop caused by packet loss is avoided. For example, since the window occupation position of the nth data implies the length information of the nth-1 data, when the nth-1 data is lost, if a data completion message for the nth data is received, the window is slid according to the TxEdge in the data completion message, not only the sending resource of the nth data is recovered, but also the sending resource of the nth-1 data is recovered; therefore, even if data is lost and/or a data completion message is lost, resources can be correctly recovered.

And c, adding header information to the first data by the first speed limiting device 212 to obtain second data, sending the second data to the Ethernet controller 213, and sending the second data to the second speed limiting device 220 by the Ethernet controller 213.

Specifically, if the logical channel has the capability of sending the first data, the first speed limiter 212 may add header information to the first data to obtain modified data, which is the second data. Fig. 4B is a schematic diagram of the modified second data. The modified second data may then be sent to the ethernet controller 213, and the second data may be sent by the ethernet controller 213 to the second speed limiter 220.

The first speed limiting device 212 adds header information to the first data, which may include, but is not limited to, the following: interface board identification, logic channel identification, interface type, message type, window sending edge and effective load length. Wherein, the window occupation position includes: the window occupation position of the first data packet may be the data packet length of the currently transmitted data; for the window occupation position of the second data packet, the length of the second data packet for sending data can be accumulated for the window occupation position of the first data packet; for the window occupation position of the third data packet, the data packet length of the second sending data and the data packet length of the third sending data can be accumulated for the window occupation position of the first data packet; and so on.

After the first speed limiter 212 transmits the second data to the ethernet controller 213, window information corresponding to the logical channel may be updated, for example, the TxEdge is moved to the right by the length of the first data.

Step d, after receiving the second data, the second speed limiting device 220 parses out the logical channel identifier from the header information of the second data, and buffers the second data in the buffer corresponding to the logical channel identifier.

For example, assuming that the logical channel identifier parsed from the header information of the second data by the second speed limiter 220 is the logical channel 241, the second data may be buffered in the buffer 251 corresponding to the logical channel 241.

And e, when the second data needs to be sent, the second speed limiting device 220 reads the second data from the buffer area corresponding to the logical channel, acquires the interface board identifier and the logical channel identifier from the header information of the second data, removes the header information of the second data to obtain the first data, and sends the first data to the interface board corresponding to the interface board identifier. In addition, the interface board may be further notified to send the first data through the logic channel corresponding to the logic channel identifier, so that the interface board sends the first data through the logic channel corresponding to the logic channel identifier.

For example, the second speed limiter 220 may read the second data from the buffer 251, acquire the interface board 231 and the logic channel 241 from the header information of the second data, remove the header information of the second data to obtain a data, send the first data to the interface board 231, and notify the interface board 231 to send the first data through the logic channel 241, and the interface board 231 may send the first data through the logic channel 241.

After the first data is sent to the interface board, in order to enable the interface board to send the first data through the logical channel, the identifier of the logical channel needs to be notified to the interface board, and the notification mechanism is not limited. For example, the second speed limiting device 220 can directly send the logical channel identifier to the interface board, so that the interface board sends the first data through the logical channel corresponding to the logical channel identifier. Or, the second speed limiting device 220 may send the first data to the interface board through the logic channel corresponding to the logic channel identifier, and after the interface board receives the first data through the logic channel, the first data may be sent through the logic channel.

In the process of sending the first data to the interface board, the second speed limiting device 220 may first obtain a first rate used when the interface board sends the first data through the logic channel, determine a second rate used when the interface board sends the first data according to the first rate, and send the first data to the interface board based on the second rate. Further, in the process of "determining a second rate used when sending the first data to the interface board according to the first rate", the second speed limiting device 220 may determine a forwarding manner of the interface board according to the feature data, and process the first data through the forwarding manner, to obtain third data at the first rate; in obtaining the third data of the first rate, the rate of the first data to be processed may be determined, and the determined rate may be determined as the second rate. The second rate is less than the first rate.

The second speed limiter 220 may further store a feature table, where the feature table is used to record data stream features, and the data stream features may include a feature type identifier (FeatureID) and feature data. The feature type identifier is used for representing the feature of the present type, and the feature data can be queried according to the feature type identifier.

Furthermore, the characteristic data may include, but is not limited to, one or any combination of the following: channel rate (Speed), e.g., 56Kbits/s, 64Kbits/s, etc. The frame Interval (IFG), such as the number of filler characters inserted between frame intervals, may be configured empirically. BlockLen, the block size that sends data to the physical layer chip. PreTxLen, i.e. the amount of advance to transmit data to the physical layer chip.

The second speed limiting device 220 may query the basic information table based on the logical channel identifier of the header information of the second data to obtain a feature type identifier corresponding to the logical channel identifier, and may then query the feature table by using the feature type identifier to obtain feature data corresponding to the feature type identifier. On the basis, the second speed limiter 220 may determine the forwarding manner of the interface board based on the characteristic data.

The forwarding mode is a forwarding mode used when the interface board sends data to the outside, the forwarding modes corresponding to different protocols can be different or the same, and the forwarding mode is related to the type of the protocol. For example, for HDLC (High-level Data Link Control), since HDLC Data frames are separated by a flag sequence, the binary value is 01111110, in a string of Data bits, a bit combination same as the flag field may be generated, and in order to prevent this, and ensure transparent transmission of Data, the forwarding method may be: and a '0' is inserted after 5 '1's by adopting a bit filling technology, so that transparent transmission of data is ensured. Of course, the forwarding method may be other cases, and is not limited to this forwarding method.

After obtaining the forwarding mode of the interface board, the second speed limiting device 220 may perform analog transmission according to the forwarding mode, specifically, process the first data through the forwarding mode to obtain third data with the first rate; in obtaining the third data of the first rate, the rate of the first data to be processed may be determined, and the determined rate may be determined as the second rate. The first rate is the rate at which the interface board actually transmits data, and the second rate is the rate at which the second speed limiter 220 actually transmits data. The process of performing the analog transmission by the second speed limiter 220 according to the transfer method is performed in real time.

The reason why the second speed limiting device 220 adopts analog transmission is as follows: assuming that a first rate used when the interface board sends data through the logical channel is 56Kbits/s, then: if the rate of providing data to the interface board is 56Kbits/s, when the interface board sends data, the interface board firstly processes the data by adopting the above forwarding mode, for example, extra information is added in the data by adopting a bit filling technology, so that the finally sent data by the interface board is larger than 56Kbits/s, for example, 60Kbits/s, that is, the data sent by the interface board overflows, the interface board cannot send the data of 60Kbits/s, and only the data of 56Kbits/s can be sent out, thereby causing partial data loss.

For the above discovery, the second speed limiting device 220 first obtains a first rate, such as 56Kbits/s, when the interface board sends data through the logic channel. Then, the data is read from the buffer and processed by the above-mentioned forwarding method, for example, adding information to the data by using a bit stuffing technique. In the processing process, when data of 56Kbits/s is generated statistically, the data rate read from the buffer is a second rate, for example, 52Kbits/s, so that the rate of providing data to the interface board by the second speed limiting device 220 is 52 Kbits/s.

In summary, the rate of providing data to the interface board is 52Kbits/s instead of 56Kbits/s, and when the interface board sends data, the interface board processes the data by using the above forwarding method, for example, adding information in the data by using a bit stuffing technique, so that the data finally sent by the interface board is 56Kbits/s, and the data does not overflow, that is, the 56Kbits/s data is sent out, which does not cause data loss, improves the efficiency of the interface board, improves the data transmission quality, implements QOS application, and avoids the problems of voice distortion, unclear image, and the like caused by data loss.

In the process of acquiring the first rate used when the interface board sends data through the logical channel, the first rate, such as a channel rate (Speed) in the feature data, may be acquired from the feature data.

The process of determining the forwarding mode of the interface board according to the feature data and processing the data through the forwarding mode may include, but is not limited to, the following modes: if the feature data includes an interface type (for example, the interface type is recorded in the feature table), determining a forwarding mode of the interface board based on the feature data, and processing the data through the forwarding mode; if the interface type is not included in the feature data (if the interface type is not recorded in the feature table), the forwarding mode of the interface board can be determined based on the feature data and the interface type (obtained from the header information of the data), and the data is processed through the forwarding mode. For example, parameters such as a frame Interval (IFG), a BlockLen, a PreTxLen, and an interface type may be used to determine a forwarding manner of the interface board, and data is processed by the forwarding manner, which is not limited to this process.

In step f, after the second speed limiting device 220 reads the second data from the buffer corresponding to the logical channel, it may also send a data completion message to the first speed limiting device 212, where the data completion message may carry the length of the first data (i.e., the length of the first data after the header information of the second data is removed), and the data completion message may also carry the header information (such as an interface board identifier, a logical channel identifier, an interface type, a message type, a window sending edge, a payload length, etc.), and the header information is the same as the header information of the second data.

Based on the TxEdge, the window sending edge in the header information of the data completion message, that is, the TxEdge, may indicate that the data of the TxEdge has been read from the buffer.

Step g, after receiving the data completion message, the first speed limiting device 212 updates the remaining resource length of the logical channel corresponding to the logical channel identifier to the sum of the current remaining resource length and the length of the first data. For example, the window occupation position is moved to the direction of the window starting position by a specified length; or, the starting position of the window is moved to the direction of the occupied position of the window by a specified length, and the ending position of the window is moved to the moving direction of the starting position of the window by the specified length. Wherein, the specified length is the length of the first data.

Or, the second position of the window start position in the sending window may be determined according to the window sending edge (i.e. the first position of the second data in the buffer), the window start position is moved to the second position in the sending window, and the window end position is moved according to the moving length of the window start position.

Based on the above technical solution, in the embodiment of the present application, a plurality of logic channels may share the processing capability of the same main control board, and may store data in the buffer corresponding to each logic channel, and send the data in the buffer through the logic channel, so as to solve the problem of rate mismatch between the main control board and the interface board, avoid the problem of packet loss of the interface board, and meet QOS requirements. In addition, the accurate speed limit of the interface board can be realized, and the performance of the main control board is improved. For example, the data transmission rate of the logic channel 241 is 56Kbits/s, the data transmission rate of the logic channel 242 is 56Kbits/s, the data transmission rate of the logic channel 243 is 56Kbits/s, and the data transmission rate of the logic channel 244 is 56Kbits/s, so that the data transmission rate of the ethernet controller 213 may be 234Kbits/s instead of 56Kbits/s corresponding to a certain logic channel. The second rate limiting device 220 can store 56Kbits/s data into the buffer 251, 56Kbits/s data into the buffer 252, 56Kbits/s data into the buffer 253, and 56Kbits/s data into the buffer 254. In the data transmission process, the second speed limiting device 220 may transmit the 56Kbits/s data to the logic channel 241, so that the logic channel 241 transmits the 56Kbits/s data, transmit the 56Kbits/s data to the logic channel 242, so that the logic channel 242 transmits the 56Kbits/s data, transmit the 56Kbits/s data to the logic channel 243, so that the logic channel 243 transmits the 56Kbits/s data, and transmit the 56Kbits/s data to the logic channel 244, so that the logic channel 244 transmits the 56Kbits/s data.

Based on the same application concept as the method, the embodiment of the present application further provides a data transmission apparatus, which can be applied to a network device, as shown in fig. 5, and is a structural diagram of the apparatus, the apparatus may include:

a determining module 501, configured to determine an interface board and a logic channel corresponding to first data to be sent;

a processing module 502, configured to add header information to the first data to obtain second data when the logical channel has a capability of sending the first data; wherein, the header information includes an interface board identifier of the interface board and a logic channel identifier of the logic channel;

a storage module 503, configured to store the second data in a buffer corresponding to the logical channel;

a reading module 504, configured to read the second data from the buffer, obtain an interface board identifier and a logic channel identifier from header information of the read second data, and remove the header information of the read second data to obtain first data;

a sending module 505, configured to send the obtained first data to an interface board corresponding to the interface board identifier.

The determining module 501 is further configured to obtain a remaining resource length of the logical channel after determining an interface board and a logical channel corresponding to first data to be sent; if the length of the residual resource is larger than or equal to the length of first data, determining that the logic channel has the capacity of sending the first data;

the processing module 502 is further configured to update the length of the remaining resource of the logical channel to a difference between the current length of the remaining resource and the length of the first data when the logical channel has the capability of sending the first data; and after the reading module reads the second data from the buffer area, updating the remaining resource length of the logic channel corresponding to the buffer area to the sum of the current remaining resource length and the length of the first data.

The logic channel corresponds to a sending window, and the length of the sending window is the same as that of a buffer zone corresponding to the logic channel; the parameters of the sending window comprise a window starting position, a window ending position and a window occupying position; the length between the window occupation position and the window ending position is the length of the residual resource of the logic channel; the processing module 502 is specifically configured to, in the process of updating the remaining resource length of the logical channel to the difference between the current remaining resource length and the length of the first data, move the window occupation position by a specified length in the direction of the window end position;

wherein the specified length is a length of the first data.

The sending module 505 is specifically configured to, in a process of sending the obtained first data to an interface board corresponding to the interface board identifier, obtain a first rate used when the interface board sends the first data through the logic channel; determining a second rate used when first data is sent to the interface board according to the first rate; sending the obtained first data to an interface board corresponding to the interface board identification based on the second rate; wherein the second rate is less than the first rate.

In an example, the sending module 505 is specifically configured to, in a process of determining a second rate used when sending first data to the interface board according to the first rate, determine a forwarding manner of the interface board according to feature data, and process the first data through the forwarding manner to obtain third data at the first rate; and in the process of obtaining the third data of the first rate, determining the rate of the first data for processing, and determining the determined rate as the second rate.

In terms of hardware, the hardware architecture diagram of the network device provided in the embodiment of the present application may specifically refer to fig. 6. The method comprises the following steps: a machine-readable storage medium and a processor, wherein:

a machine-readable storage medium: the instruction code is stored.

A processor: the data transmission operations disclosed in the above examples of the present application are implemented by communicating with a machine-readable storage medium, reading and executing the instruction codes stored in the machine-readable storage medium.

Here, a machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and so forth. For example, the machine-readable storage medium may be: a RAM (random Access Memory), a volatile Memory, a non-volatile Memory, a flash Memory, a storage drive (e.g., a hard drive), a solid state drive, any type of storage disk (e.g., an optical disk, a dvd, etc.), or similar storage medium, or a combination thereof.

In the network device provided in the embodiment of the present application, the network device further includes:

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.

For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Furthermore, these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method of data transmission, the method comprising:

reading second data from the buffer area, acquiring an interface board identifier and a logic channel identifier from the read header information of the second data, removing the read header information of the second data to obtain first data, and sending the obtained first data to an interface board corresponding to the interface board identifier;

wherein a plurality of logical channels are created in advance, and a buffer is allocated for each logical channel.

2. The method of claim 1,

3. The method of claim 2, wherein the logical channel corresponds to a sending window, and the length of the sending window is the same as the length of a buffer corresponding to the logical channel; the parameters of the sending window comprise a window starting position, a window ending position and a window occupying position; the length between the window occupation position and the window ending position is the length of the residual resource of the logic channel;

wherein the specified length is a length of the first data.

4. The method of claim 1,

wherein the second rate is less than the first rate.

5. The method according to claim 4, wherein the determining a second rate used when sending the first data to the interface board according to the first rate specifically comprises:

6. A data transmission apparatus, characterized in that the apparatus comprises:

the sending module is used for sending the obtained first data to an interface board corresponding to the interface board identifier;

7. The apparatus of claim 6,

8. The apparatus of claim 7, wherein the logical channel corresponds to a sending window, and a length of the sending window is the same as a length of a buffer corresponding to the logical channel; the parameters of the sending window comprise a window starting position, a window ending position and a window occupying position; the length between the window occupation position and the window ending position is the length of the residual resource of the logic channel;

wherein the specified length is a length of the first data.

9. The apparatus of claim 6,

wherein the second rate is less than the first rate.

10. The apparatus according to claim 9, wherein the sending module is specifically configured to, in a process of determining a second rate used when sending first data to the interface board according to the first rate, determine a forwarding manner of the interface board according to feature data, and process the first data by the forwarding manner to obtain third data at the first rate; and in the process of obtaining the third data of the first rate, determining the rate of the first data for processing, and determining the determined rate as the second rate.

11. A network device, characterized in that the network device comprises: