CN108735774B - Aluminum-tellurium alloy-based bidirectional gate tube of memory and preparation method thereof - Google Patents
Aluminum-tellurium alloy-based bidirectional gate tube of memory and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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Abstract
The invention discloses a memory bidirectional gate tube based on aluminum-tellurium alloy and a preparation method thereof, wherein the gate tube comprises: a substrate (1); forming a wiring groove above a substrate (1), and depositing a diffusion barrier layer (3), wherein the diffusion barrier layer (3) covers the surface of the whole wiring groove, and a tungsten wiring lower electrode (2) is arranged in the wiring groove and is in contact with the diffusion barrier layer (3); an insulating layer (4) which is provided on an exposed surface of the tungsten wiring lower electrode (2) and is in contact with the tungsten wiring lower electrode (2), two tungsten plugs (5) are provided in the insulating layer (4), and side walls of the two tungsten plugs are covered with a diffusion barrier layer (3), wherein one tungsten plug (5) is covered with a threshold transition layer (6) and is in contact with the wiring lower electrode (2), and the other tungsten plug (5) is covered with an inert metal material and is in contact with the wiring lower electrode (2), forming a lower electrode lead (7); and an upper electrode (8) provided on the threshold value transition layer (6).
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a memory bidirectional gate tube based on aluminum-tellurium alloy and a preparation method thereof.
Background
Resistive Random Access Memory (RRAM) technology is a promising nonvolatile Memory technology, and has the characteristics of simple structure, high density, nonvolatile property, high speed, low power consumption, low cost and the like, so that the RRAM technology has the potential to replace the mainstream flash Memory technology at present.
To implement commercial applications of RRAM, RRAM memory cells must be integrated to form a memory array. One of the mainstream methods is to use a Crossbar array (Crossbar) structure to increase the integration density of the memory. Each cross node in the crisscross array has a memory cell, and binary information is stored in a high impedance state or a low impedance state. The size of memory cell of the crisscross array can be reduced to 4F2. More importantly, the three-dimensional stacking can be conveniently carried out by adopting a cross array structure. After N layers are stacked, the area of the memory unit of the crisscross array structure can be further reduced to 4F2and/N, thereby greatly improving the storage density of the RRAM.
However, due to the characteristics of the crossbar array, it is difficult to avoid the Crosstalk (crossbar) misreading phenomenon, that is, due to the existence of the leakage current, the high-resistance state of the target memory cell is misread as the low-resistance state. This crosstalk phenomenon is more pronounced in 3-dimensional stacked structures. In the past, the method for solving the crosstalk problem in the crisscross array is mainly as follows: a diode (D) with a rectifying characteristic is connected in series with each resistive random access memory cell to form a 1D1R structure. However, due to the single-phase conduction characteristic of the diode, the 1D1R structure is only suitable for a single-pole resistive switching device. Meanwhile, the use of the diode not only increases the process complexity, but also can lead to the increase of the operating voltage and deteriorate the stability of the memory device after the diode is connected in series with the memory cell due to the voltage division effect of the resistance of the diode.
In another method, a non-diode bidirectional gate (Selector) is connected in series with the memory cell to form a 1S1R structure. The bidirectional gate tube (S) is a device whose current-voltage curve is nonlinear, and its resistance values at low voltage and high voltage are very different, often by several orders of magnitude. When the voltage is lower than the threshold voltage (Vth), the gate tube is cut off; and when the threshold voltage (Vth) is higher, the gate tube is conducted. A criss-cross array typically uses a pattern of 1/2Vread voltages to read information. When the read operation is carried out, the voltage on the unselected memory cells is lower (less than Vth, which can be 1/2Vread), the gate tube is in a high-resistance state (off state), and the cross-talk current can be prevented from passing through; and the voltage on the selected memory cell is Vread (greater than Vth), so that the information can be read normally.
In selecting the gate tube, there are two important considerations, namely the drive current and the current-voltage nonlinear ratio, depending on the memory device requirements. To be able to program and erase a selected resistive-switching memory cell, the gate tube should be capable of passing a high drive current. For example, to switch a resistive cell having a device area of 10nm × 10nm, a switching current of 1 μ A is required, and the minimum current density that the gate tube must provide is 1MA/cm2. In addition, the non-linear ratio of current-voltage can be defined as the ratio of the current through the gate at the transition voltage V to the current through the gate at half the transition voltage (V/2), which should reach 1000.
The two-terminal gate tube device reported at present has high current-voltage nonlinear ratio (NL > 10)3) However, it does not achieve sufficient driving current, only 1 × 10-6A (Jeonghwan S., et al. applied Physics Letters 107,113504 (2015)); another two-end gate tube deviceThe on-state drive current is large (about 500 muA), but the current-voltage nonlinear ratio is not high and is only 102Magnitude (Wan Gee K., et al, IEEE/Symposium on VLSI Technology Digest of Technical Papers, 2014).
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an aluminum-tellurium alloy-based memory bidirectional gate tube and a preparation method thereof, so as to achieve the purposes of transmitting high driving current and having high current-voltage nonlinear ratio.
To achieve the above and other objects, the present invention provides a bidirectional gate tube for a memory based on aluminum-tellurium alloy, comprising:
a substrate (1);
forming a wiring groove above the substrate (1), and depositing a diffusion barrier layer (3), wherein the diffusion barrier layer (3) covers the surface of the whole tungsten plug channel, and a wiring lower electrode (2) is arranged in the wiring groove and is in contact with the diffusion barrier layer (3);
an insulating layer (4) which is provided on an exposed surface of the wiring lower electrode (2) and is in contact with the wiring lower electrode (2), two tungsten plugs (5) are provided in the insulating layer (4), and side walls of the two tungsten plugs are covered with a diffusion barrier layer (3), one of the tungsten plugs (5) is covered with a threshold transition layer (6) and is in contact with the wiring lower electrode (2), and the other tungsten plug (5) is covered with an inert metal material and is in contact with the wiring lower electrode (2), forming a lower electrode lead (7);
an upper electrode (8) disposed above the threshold transition layer (6).
Preferably, the wiring lower electrode (2) is formed by the following process: forming a wiring groove above the substrate (1) through photoetching and etching, depositing the diffusion barrier layer (3), filling the groove with deposited tungsten, and finally forming a wiring lower electrode (2) through chemical mechanical polishing.
Preferably, the tungsten plug (5) is formed as follows: forming a tungsten plug hole in the insulating layer (4) by photoetching, depositing the diffusion barrier layer (3), etching the diffusion barrier layer at the bottom of the hole, filling the hole with deposited tungsten, and finally performing chemical mechanical polishing to form a tungsten plug (5).
Preferably, the thickness of the wiring groove diffusion impervious layer (3) ranges from 3nm to 50nm, and the thickness of the tungsten ranges from 50nm to 5000 nm.
Preferably, the thickness range of the tungsten plug hole diffusion impervious layer (3) is 3 nm-50 nm, and the thickness of the tungsten plug (5) is 50 nm-3000 nm.
Preferably, the insulating layer (4) is deposited SiO by adopting a PECVD method2F or C doped SiO for low-k dielectric material2Porous SiO2Or SiOC with a thickness of 50-3000 nm.
Preferably, two tungsten plug holes in the insulating layer (4) are formed after photoetching, dry etching or wet etching, and the diameter of a through hole at the position of the bidirectional gate tube is preferably less than 10 microns.
Preferably, the threshold value transition layer (6) is an aluminum tellurium amorphous alloy film which is obtained by magnetron co-sputtering and has the thickness ranging from 1nm to 100 nm.
Preferably, the thickness of the upper electrode (8) and the lower electrode lead (7) ranges from 10nm to 500 nm.
Preferably, the upper electrode (8) and the lower electrode lead (7) are W or TiN or other inert metal electrodes or combination thereof.
In order to achieve the above object, the present invention further provides a method for preparing a memory bidirectional gate tube based on an aluminum-tellurium alloy, comprising the following steps:
step S1, forming a wiring trench above the substrate by photoetching and etching, depositing a diffusion barrier layer, filling the wiring trench with deposited tungsten, and finally forming a wiring lower electrode by chemical mechanical polishing;
step S2, depositing an insulating layer on the surface of the lower electrode of the wiring by adopting a PECVD method, and forming two tungsten plug holes at corresponding positions in the insulating layer;
step S3, depositing a diffusion barrier layer in the hole of the tungsten plug, etching the diffusion barrier layer at the bottom of the hole, filling the hole of the tungsten plug with PECVD tungsten, and finally polishing to form the tungsten plug.
Step S4, spin-coating photoresist on the silicon chip with the tungsten plug structure, and after baking the photoresist, determining the position and the size of the lower electrode lead by adopting a photoetching development technology;
step S5, depositing a tungsten metal lower electrode lead by adopting a DC magnetron sputtering technology;
step S6, soaking the sample in acetone solution by adopting a stripping technology, dissolving redundant photoresist and removing redundant tungsten metal outside the pattern to prepare a lower electrode lead of the tungsten metal;
step S7, spin-coating photoresist for the second time, and after baking the photoresist, determining the positions and the sizes of the threshold value transition layer and the upper electrode by adopting the photoetching development technology;
step S8, depositing a threshold transition layer by adopting a magnetron co-sputtering technology;
step S9, depositing a tungsten metal upper electrode by adopting a DC magnetron sputtering technology;
and step S10, soaking the sample in acetone solution by adopting a stripping technology, dissolving redundant photoresist and removing redundant photoresist materials, and realizing the imaging of the threshold value transition layer and the upper electrode.
Compared with the prior art, the aluminum-tellurium alloy based memory bidirectional gate tube and the preparation method thereof have the advantages that in the tungsten plug structure, an aluminum-tellurium alloy film is prepared by utilizing a co-sputtering method, and the gate tube device has excellent performance due to the matching of the material and the size of a low-scale device (a tungsten plug with the diameter of 2 mu m); from the material perspective, the aluminum-tellurium alloy film has good uniformity, so that each parameter of the device is very stable, particularly the threshold voltage and the on-off current which are distributed intensively are represented, and the material has a large current-voltage nonlinear ratio (nonlinear-6000), and moreover, the on-state current of the material can reach the milliampere level, and the read and write requirements of a storage unit can be completely met; in terms of device size, the size of the gate tube device in the embodiment of the invention is 2um, and the smaller-sized device can further reduce the probability of short circuit and further reduce the leakage current of the device, so that a higher current-voltage nonlinear ratio can be expected to be obtained. The bidirectional gate tube based on the aluminum-tellurium alloy film can be connected with a resistance change memory unit in series and used for a resistance change memory array, and can also be connected with a phase change memory unit in series and used for a phase change memory array.
Drawings
FIG. 1 is a schematic structural diagram of a two-way gate tube of an aluminum-tellurium alloy-based memory according to the present invention;
FIG. 2 is a flow chart of the steps of a method for manufacturing a bidirectional gate tube of an aluminum-tellurium alloy-based memory according to the present invention;
FIG. 3 shows an Al-Te amorphous alloy film based on the present inventionxTe1-x(x ═ 0.39) current-voltage (I-V) characteristics of a 40nm thick bidirectional gate tube;
FIG. 4 shows an Al-Te-based amorphous alloy thin film Al according to the present inventionxTe1-x(x ═ 0.44) current-voltage (I-V) characteristics of a 40nm thick bidirectional gate tube;
FIG. 5 shows an Al-Te-based amorphous alloy thin film Al according to the present inventionxTe1-x(x ═ 0.44), current-voltage (I-V) characteristic curve of a 25nm thick bidirectional gate tube.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 1 is a schematic structural diagram of a two-way gate tube of a memory based on an Al-Te alloy according to the present invention. As shown in fig. 1, the invention relates to a memory bidirectional gate tube based on aluminum-tellurium alloy, comprising:
a substrate 1, wherein in the specific embodiment of the present invention, the substrate 1 is a silicon wafer with an oxidized surface;
a wiring trench is formed above the substrate and a diffusion barrier layer 3 is deposited, said diffusion barrier layer 3 covering the entire wiring channel surface, a wiring lower electrode 2 is disposed in the wiring channel in contact with the diffusion barrier layer 3. In an embodiment of the present invention, the lower wiring electrode 2 is formed by a standard CMOS process, and specifically, the formation process is as follows: forming a wiring groove above the substrate by photoetching and etching, depositing a diffusion barrier layer Ti/TiN with the thickness range of 3 nm-50 nm, depositing tungsten by PECVD (Plasma Enhanced Chemical Vapor Deposition) to fill the groove, wherein the thickness of the tungsten is 50 nm-5000 nm, and then forming a lower electrode 2 of the wiring by Chemical mechanical polishing;
an insulating layer 4 disposed on the exposed surface of the wiring lower electrode 2 and contacting the wiring lower electrode 2, wherein the insulating layer 4 is formed by depositing SiO by PECVD method2F or C doped SiO for low-k dielectric material2Porous SiO2Or SiOC with a thickness ranging from 50 to 3000nm, two tungsten plugs 5 are disposed in the insulating layer 4, and the sidewalls of the two tungsten plugs are covered by the diffusion barrier layer 3, in the embodiment of the present invention, the thickness of the tungsten plug hole diffusion barrier layer 3 ranges from 3nm to 50nm, preferably, the thickness ranges from 20nm to 50nm, the thickness of the tungsten plugs 5 ranges from 50nm to 3000nm, preferably, the thickness ranges from 300nm to 1000nm, one of the tungsten plugs 5 is covered by the threshold transition layer 6 and is in contact with the wiring lower electrode 2, and the other tungsten plug 5 is covered by the inert metal material and is in contact with the wiring lower electrode 2, so as to form the lower electrode lead 7. In the embodiment of the present invention, the two tungsten plugs 5 are formed by photolithography, dry etching or wet etching, and the diameter of the tungsten plug at the position where the bidirectional gate tube is formed is preferably less than 10 μm.
Preferably, the threshold transition layer 6 is an aluminum (Al) tellurium (Te) amorphous alloy thin film obtained by magnetron co-sputtering, wherein aluminum is produced using DC magnetron sputtering and tellurium is produced using RF sputtering. In practical application, the aluminum-tellurium alloy threshold transition layer can also be prepared by sputtering an aluminum-tellurium alloy target material or by an MOCVD method and the like. In a specific embodiment of the invention, the Al isxTe1-xThe content x of Al atoms in the threshold conversion layer is more than or equal to 33% and less than or equal to 50% (actual experiment value), and leakage of the gate tube is foundThe current decreases with increasing aluminum content. When the Al content is too low (lower than 30%), the material is easy to generate a phase change phenomenon, the threshold voltage basically disappears, and the device cannot limit the leakage current; when the Al content is too high (higher than 60%), the material is not prone to threshold transition, the threshold voltage increases, and after several cycles, the device breaks down directly.
Preferably, the thickness range of the threshold transition layer 6 is 1nm to 100nm (the current experimental thickness is 25nm to 40nm), when the threshold transition layer 6 is too thin, the leakage current increases, and the current selection ratio of the device decreases; when the threshold transition layer is too thick, the threshold voltage of the device is large and the device is difficult to reach an on-state.
And an upper electrode 8 disposed on the threshold transition layer 6, wherein the upper electrode and the lower electrode have a thickness ranging from 30nm to 500nm in the specific embodiment of the present invention. The upper electrode lead and the lower electrode lead can be W, TiN or other inert metal electrodes or combinations thereof.
FIG. 2 is a flow chart of steps of a method for manufacturing a bidirectional gate tube of an aluminum-tellurium alloy-based memory according to the present invention. As shown in fig. 2, the method for preparing the two-way gate tube of the memory based on the aluminum-tellurium alloy comprises the following steps:
step S1, forming a wiring groove above the substrate 1 through photoetching and etching, and depositing a diffusion barrier layer Ti/TiN with the thickness of 3 nm-50 nm; filling the wiring groove with PECVD tungsten, wherein the thickness of the tungsten is 50 nm-5000 nm; and forming a wiring lower electrode by chemical mechanical polishing.
Step S2, depositing SiO on the surface of the electrode under the wiring by PECVD (Plasma Enhanced Chemical Vapor Deposition)2An insulating layer with a thickness of 50-3000 nm, and etching the SiO layer by photolithography and dry etching2Two tungsten plug holes are formed at corresponding positions in the insulating layer.
Step S3, depositing a diffusion barrier layer in the hole of the tungsten plug, etching the diffusion barrier layer at the bottom of the hole by dry etching, depositing tungsten by PECVD to fill the hole of the tungsten plug, and finally performing chemical mechanical polishing to form the tungsten plug, wherein in the embodiment of the invention, the thickness of the diffusion barrier layer of the hole of the tungsten plug is 3nm to 50nm, preferably 20nm to 50nm, the thickness of the tungsten plug is 50nm to 3000nm, preferably 300nm to 1000 nm.
Step S4, spin-coating photoresist on the silicon chip with the tungsten plug structure, and after baking the photoresist, determining the position and the size of the lower electrode lead 7 by adopting a photoetching development technology;
and step S5, depositing the W metal lower electrode lead 7 by adopting a DC magnetron sputtering technology.
Step S6, soaking the sample in acetone solution by adopting a stripping technology, dissolving redundant photoresist and removing redundant W metal outside the pattern to prepare a W metal lower electrode lead 7;
step S7, spin-coating photoresist for the second time, and after baking the photoresist, determining the positions and the sizes of the threshold value transition layer 6 and the upper electrode 8 by adopting the photoetching development technology;
step S8, depositing an aluminum-tellurium amorphous alloy film, i.e., the threshold transition layer 6, by using a magnetron co-sputtering technique, wherein DC magnetron sputtering is used for aluminum, and RF sputtering is used for tellurium. In the embodiment of the invention, pure Al targets and pure Te targets are adopted, and the used sputtering gas is pure Ar gas.
And step S9, depositing the W metal upper electrode 8 by adopting a DC magnetron sputtering technology.
Step S10, a stripping technique is used to soak the sample in acetone solution, dissolve the excess photoresist and remove the excess material on the photoresist, so as to realize the patterning of the threshold transition layer 6 and the upper electrode 8.
The smaller the size of the tungsten plug covered by the threshold switching layer 6 in this embodiment is, the more advantageous the reduction of the leakage current of the bidirectional strobe device is, and the more advantageous the improvement of the current-voltage nonlinearity ratio of the device is.
The invention provides a bidirectional gate tube based on aluminum-tellurium amorphous alloy. Because the aluminum-tellurium amorphous alloy in the device can provide charged traps, when low voltage is applied to the device, current carriers are limited by the traps, and leakage current is reduced; as the external voltage rises, the charged traps are constantly filled; when the voltage value reaches a critical point, the carrier just fills the trap, and the mobility of the carrier increases, so that the current suddenly increases, and the threshold transition occurs. However, this threshold phenomenon is different from the phase transition phenomenon, which is only an electrical transition and does not cause a structural phase transition of the material.
Compared with the prior art, the gate tube based on the aluminum-tellurium alloy does not need to be subjected to an electrical initialization process (namely forming-free), and the threshold voltage (V) of the gate tube isth) Is distributed very intensively, and the gate tube is open-state current Ion(V ═ 0.7V) can reach the milliamp level (1mA), which is sufficient for read and write operations of the memory devices connected in series with it. Current of gate tube at V/2, namely off-state leakage current IoffIs only 1.7 × 10-7A. Thus, the current-voltage nonlinear ratio (defined as I) of the gate deviceon/Ioff) Can reach 5900 and shows excellent switching performance.
Example one
In this embodiment, the threshold transition layer 6 is Al with a thickness of 40nmxTe1-xAn amorphous alloy. The Al atom content in the threshold transition layer 6 is 39%.
In this embodiment, an Al target and a Te target are co-sputtered, and the composition of the threshold transition layer 6 is changed by adjusting the power applied to the Al target and the Te target. The threshold value transition layer 6, namely the components of the aluminum tellurium alloy film, is obtained by measuring with an X-ray photoelectron spectroscopy (XPS) analyzer.
In the embodiment of the present invention, the bidirectional gate device manufactured by the above method is tested by a Keithley 4200 semiconductor parameter tester, and the current-voltage (I-V) characteristics of the device are obtained as shown in fig. 3. During testing, the positive bias and the negative bias are applied to the lower electrode, and the upper electrode is always grounded. The initial resistance of the bidirectional gating device based on the aluminum-tellurium amorphous alloy is in a high resistance state, and is-2.25 multiplied by 106Ω, the gate tube is in off-state. The gating tube does not need an initialization (forming-free) process. Setting appropriate limiting current (I) during testcc1mA) to prevent device breakdown. During testing, a single voltage scanning method is adopted, and the scanning sequence is 0 → 1V; 0 → -1V. From FIG. 3, it can be seen thatWhen the voltage is swept to about +/-0.7V, the current passing through the device is suddenly increased, and when the current reaches the limiting current of 1mA, the gate tube device is converted into an on-state, namely the on-state current I of the deviceonIs 1 mA. At this time, the voltage corresponding to the current jump is called threshold voltage (V)th). Due to the symmetry of the device structure, it can be seen from fig. 3 that the I-V curves from the positive and negative voltage sweeps are substantially symmetrical. When the on-state voltage V is ± 0.7V, the current at V/2 ± 0.35V is the leakage current (I) of the deviceoff). In fig. 3, it can be seen that in this embodiment, the leakage current I of the deviceoffAt 6.1X 10-7A left and right, the current-voltage nonlinear ratio (I) of the deviceon/Ioff) Is 1.6X 103。
Example two
In this embodiment, the threshold transition layer 6 is Al with a thickness of 40nmxTe1-xAn amorphous alloy. The Al atom content in the threshold transition layer 6 is 44%.
In this example, the bidirectional gate device manufactured by the above method was tested by a Keithley 4200 semiconductor parameter tester, and the current-voltage (I-V) characteristics of the device were obtained as shown in fig. 4. During testing, the positive bias and the negative bias are applied to the lower electrode, and the upper electrode is always grounded. The initial resistance of the bidirectional gate tube device based on the aluminum-tellurium amorphous alloy is in a high resistance state, and is 8.81 multiplied by 106Ω, the gate tube is in off-state. The gating tube does not need an initialization (forming-free) process. Setting appropriate limiting current (I) during testcc1mA) to prevent device breakdown. During testing, a single voltage scanning method is adopted, and the scanning sequence is 0 → 1V; 0 → -1V. As can be seen from FIG. 4, when the voltage is swept to about + -0.7V, the current through the device increases suddenly, and when the current reaches the limiting current of 1mA, the gate device transitions to the on-state, i.e., the device on-state current IonIs 1 mA. The voltage corresponding to the sudden change of current is called threshold voltage (V)th). Due to the symmetry of the device structure, it can be seen from fig. 4 that the I-V curves from the positive and negative voltage sweeps are substantially symmetrical. When the on-state voltage V is selected to be +/-0.7VThen, the current at V/2 ═ 0.35V is the leakage current (I) of the deviceoff). In fig. 4, it can be seen that in this embodiment, the leakage current I of the deviceoffAt 1.7X 10-7A left and right, the current-voltage nonlinear ratio (I) of the deviceon/Ioff) Reaches 5.9 multiplied by 103。
The size of the gate tube device in the embodiment of the invention is 2um, if a smaller device size is adopted, the probability of short circuit can be further reduced, and the leakage current of the device can be further reduced, so that a higher current-voltage nonlinear ratio can be expected to be obtained.
EXAMPLE III
In this embodiment, the threshold transition layer 6 is Al with a thickness of 25nmxTe1-xAn amorphous alloy. The Al atom content in the threshold transition layer 6 is 44%.
In this example, a Keithley 4200 semiconductor parameter tester is used to test the bidirectional gate device manufactured by the above method, and the current-voltage (I-V) characteristics of the device are obtained, as shown in fig. 5. During testing, the positive bias and the negative bias are applied to the lower electrode, and the upper electrode is always grounded. The initial resistance of the bidirectional gate tube device based on the aluminum-tellurium amorphous alloy is in a high resistance state, and is-3.33 multiplied by 106Ω, the gate tube is in off-state. The gating tube does not need an initialization (forming-free) process. Since the thickness of the threshold transition layer 5 in this device is only 25nm, a small limiting current (I) is set during the testcc300 μ a) to prevent device breakdown. During testing, a single voltage scanning method is adopted, and the scanning sequence is 0 → 0.8V; 0 → -0.8V. As can be seen from FIG. 5, when the voltage is swept to about + -0.6V, the current through the device suddenly increases and the gate device transitions to an on-state, i.e., the device on-state current Ion300 μ A. The voltage corresponding to the sudden change of current is called threshold voltage (V)th). Due to the symmetry of the device structure, it can be seen from fig. 5 that the I-V curves from the positive and negative voltage sweeps are substantially symmetrical. When the on-state voltage V is ± 0.6V, the current at V/2 ± 0.3V is the leakage current (I) of the deviceoff). In fig. 5, it can be seen that in this embodiment, the device isLeakage current IoffAt 3.0X 10-7A left and right, the current-voltage nonlinear ratio (I) of the deviceon/Ioff) Reaches 1.0 multiplied by 103。
In this example, the device with a 25nm thick threshold transition layer still has stable cycling characteristics. When the size of the device is further reduced, the probability of short circuit of the threshold transition layer can be further reduced, so that the leakage current of the device can be further reduced, and the current-voltage nonlinear ratio of the device can be improved.
Compared with the prior art, the invention has the following advantages:
1) the invention provides a new threshold value transformation material, namely Al, according to the design principle of a bidirectional gate tube devicexTe1-xAmorphous alloy, and adopting symmetrical inert metal electrode to form W/AlxTe1-xA bidirectional gate tube with a/W sandwich structure. Due to charged traps and W/Al in the aluminum tellurium amorphous alloy materialxTe1-xThe combined action of the potential barriers at the interface can effectively suppress the low voltage region (V < | V)th|) bidirectional crosstalk current. When the voltage increases beyond the threshold voltage | VthWhen the bidirectional gate tube device is in an open state, traps in the aluminum-tellurium amorphous alloy material are filled, the mobility of current carriers is obviously improved, the current is suddenly increased, and the bidirectional gate tube device is in the open state. The on-state current (1mA) of the memory cell can meet the read and write operations of the memory cells integrated in series, and the memory cell has low leakage current and high current-voltage nonlinear ratio (5.9 multiplied by 10)3) The cross-talk current in the memory array can be effectively inhibited, and the cross-talk problem in the cross structure is solved.
2) Can be changed by adjusting the threshold valuexTe1-xThe alloy composition and thickness meet the requirements of the performance of the bidirectional gate tube device. As can be derived from fig. 3 and 4, when the threshold transition layer thickness is 40nm, the device performance can be adjusted by changing the Al content of the layer. As the Al content increases (in the range of 33% to 50%), it was found that the leakage current gradually decreases, and the current-voltage nonlinear ratio shows an increasing tendency. When the Al content is constant (fixed at 44%), the thickness of the threshold transition layer increasesWhen the voltage is increased (25nm is increased to 40nm), as shown in fig. 5 and 4, the leakage current is reduced, and the current-voltage nonlinear ratio of the device is increased.
When the size of the device is smaller, the leakage current is smaller, and under the condition that other conditions are not changed, the current-voltage nonlinear ratio of the device is further improved. According to the principle that the aspect ratio of the device is fixed, when the size of the device is reduced, the thickness of the device should be reduced correspondingly. In example 3 (see fig. 5), a device with a 2 μm diameter and a 25nm thick threshold transition layer still has stable cycling characteristics, and it can be predicted that the device will have more excellent performance when the device size is further reduced, such as: higher current selection ratio, stable cycle characteristics, more uniform threshold voltage and leakage current distribution, etc.
3) The bidirectional strobe device has excellent cycle stability and has very uniform distribution of leakage current, threshold voltage and nonlinear ratio. As can be seen from fig. 3 and 4, the threshold voltage is mainly concentrated in the range of 0.7 ± 0.05V; as can be seen from FIG. 5, the threshold voltage is mainly concentrated in the range of 0.6. + -. 0.05V. And the distribution range of the leakage current is also very narrow. Moreover, in the process of preparing the sample, the good product rate is found to be high, which provides possibility for preparing the bidirectional gate tube device on a large scale.
4) Unlike some strobe devices, the device does not require an electrical initialization process, i.e., a forming-free, which not only simplifies the process during reading, but also prevents irreversible damage to the device from the forming process.
5) The preparation method has simple process, all the process procedures are carried out at room temperature, and the method is compatible with the CMOS process and suitable for efficiently preparing the bidirectional strobe device with excellent performance on a large scale.
6) The bidirectional gate tube based on the aluminum-tellurium alloy film has larger on-state current (1mA), so that the bidirectional gate tube can be connected with a resistance change memory unit in series and used for a resistance change memory array, and can also be connected with a phase change memory unit in series and used for a phase change memory array.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (11)
1. A two-way gate tube of memory based on aluminum-tellurium alloy comprises:
a substrate (1);
forming a wiring groove above the substrate (1), and depositing a diffusion barrier layer (3), wherein the diffusion barrier layer (3) covers the surface of the whole wiring groove, and a wiring lower electrode (2) is arranged in the wiring groove and is in contact with the diffusion barrier layer (3);
an insulating layer (4) which is provided on an exposed surface of the wiring lower electrode (2) and is in contact with the wiring lower electrode (2), two tungsten plugs (5) are provided in the insulating layer (4), and side walls of the two tungsten plugs are covered with a diffusion barrier layer (3), one of the tungsten plugs (5) is covered with a threshold transition layer (6) and is in contact with the wiring lower electrode (2), and the other tungsten plug (5) is covered with an inert metal material and is in contact with the wiring lower electrode (2), forming a lower electrode lead (7); an upper electrode (8) disposed above the threshold transition layer (6);
the threshold value transition layer (6) is made of aluminum-tellurium amorphous alloy, and the bidirectional gate tube realizes the function of bidirectional gate through the threshold value transition layer (6);
the memory comprises a plurality of memory units, a plurality of memory units are integrated to form a memory array, the bidirectional gate tube is connected with the memory units in series, and the bidirectional gate tube is used for inhibiting crosstalk current in the memory array.
2. An al-te alloy based memory bidirectional gate tube as claimed in claim 1, wherein the formation process of the wiring bottom electrode (2) is as follows: forming a wiring groove above the substrate (1) through photoetching and etching, depositing the diffusion barrier layer (3), filling the groove with deposited tungsten, and finally forming a wiring lower electrode (2) through chemical mechanical polishing.
3. An al-te alloy based memory bidirectional gate tube as claimed in claim 1, wherein the tungsten plug (5) is formed by the following process: forming a tungsten plug hole in the insulating layer (4) by photoetching, depositing the diffusion barrier layer (3), etching the diffusion barrier layer at the bottom of the hole, then depositing tungsten to fill the hole, and finally performing chemical mechanical polishing to form a tungsten plug (5).
4. The memory bidirectional gate tube based on aluminum-tellurium alloy as claimed in claim 2, characterized in that: the thickness range of the wiring groove diffusion impervious layer (3) is 3 nm-50 nm, and the thickness of tungsten is 50 nm-5000 nm.
5. The memory bidirectional gate tube based on aluminum-tellurium alloy as claimed in claim 3, wherein: the thickness range of the tungsten plug hole diffusion impervious layer (3) is 3 nm-50 nm, and the thickness of the tungsten plug (5) is 50 nm-3000 nm.
6. The memory bidirectional gate tube based on aluminum-tellurium alloy as claimed in claim 3, wherein: the insulating layer (4) is used for depositing SiO by adopting a PECVD method2F or C doped SiO for low-k dielectric material2Porous SiO2Or SiOC with a thickness of 50-3000 nm.
7. The memory bidirectional gate tube based on aluminum-tellurium alloy as claimed in claim 3, wherein: two tungsten plug holes in the insulating layer (4) are formed after photoetching, dry etching or wet etching, and the diameter of a through hole at the position of the bidirectional gate tube is preferably less than 10 microns.
8. The memory bidirectional gate tube based on aluminum-tellurium alloy as claimed in claim 1, wherein: the threshold value transition layer (6) is an aluminum tellurium amorphous alloy film which is obtained by magnetron co-sputtering, and the thickness range of the threshold value transition layer is 1 nm-100 nm.
9. The memory bidirectional gate tube based on aluminum-tellurium alloy as claimed in claim 1, wherein: the thickness ranges of the upper electrode (8) and the lower electrode lead (7) are 10nm-500 nm.
10. The memory bidirectional gate tube based on aluminum-tellurium alloy as claimed in claim 9, wherein: the upper electrode (8) and the lower electrode lead (7) are W or TiN or other inert metal electrodes or a combination thereof.
11. A method for preparing an aluminum-tellurium alloy based memory bidirectional gate tube, which is used for preparing the aluminum-tellurium alloy based memory bidirectional gate tube as claimed in any one of claims 1 to 10, and comprises the following steps:
step S1, forming a wiring trench above the substrate by photoetching and etching, depositing a diffusion barrier layer, filling the wiring trench with deposited tungsten, and finally forming a wiring lower electrode by polishing;
step S2, depositing an insulating layer on the surface of the lower electrode of the wiring, and forming two tungsten plug holes at corresponding positions in the insulating layer;
step S3, depositing a diffusion barrier layer in the hole of the tungsten plug, etching the diffusion barrier layer at the bottom of the hole, filling the hole of the tungsten plug with deposited tungsten, and finally polishing to form the tungsten plug;
step S4, spin-coating photoresist on the silicon chip with the tungsten plug structure, and after baking the photoresist, determining the position and the size of the lower electrode lead;
step S5, depositing a tungsten metal lower electrode lead by adopting a DC magnetron sputtering technology;
step S6, dissolving the redundant photoresist and removing the redundant tungsten metal outside the graph by adopting a stripping technology to prepare a lower electrode lead of the tungsten metal;
step S7, spin-coating photoresist for the second time, and determining the positions and the sizes of the threshold value transition layer and the upper electrode after baking the photoresist;
step S8, depositing a threshold transition layer by adopting a magnetron co-sputtering technology;
step S9, depositing a tungsten metal upper electrode by adopting a DC magnetron sputtering technology;
and step S10, dissolving redundant photoresist and removing redundant photoresist material by adopting a stripping technology, and realizing the imaging of the threshold value transition layer and the upper electrode.
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| US7696077B2 (en) * | 2006-07-14 | 2010-04-13 | Micron Technology, Inc. | Bottom electrode contacts for semiconductor devices and methods of forming same |
| CN103050620A (en) * | 2011-10-11 | 2013-04-17 | 中国科学院上海微系统与信息技术研究所 | Phase-change material for phase-change memory |
| CN106910759A (en) * | 2017-02-22 | 2017-06-30 | 中国科学院微电子研究所 | Selector based on transition metal oxide and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7696077B2 (en) * | 2006-07-14 | 2010-04-13 | Micron Technology, Inc. | Bottom electrode contacts for semiconductor devices and methods of forming same |
| CN103050620A (en) * | 2011-10-11 | 2013-04-17 | 中国科学院上海微系统与信息技术研究所 | Phase-change material for phase-change memory |
| CN106910759A (en) * | 2017-02-22 | 2017-06-30 | 中国科学院微电子研究所 | Selector based on transition metal oxide and preparation method thereof |
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