CN108735774A - Two-way gate tube of a kind of memory based on aluminium tellurium alloy and preparation method thereof - Google Patents
Two-way gate tube of a kind of memory based on aluminium tellurium alloy and preparation method thereof Download PDFInfo
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- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 53
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 50
- 239000004411 aluminium Substances 0.000 title claims abstract description 48
- 229910001215 Te alloy Inorganic materials 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 78
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 78
- 239000010937 tungsten Substances 0.000 claims abstract description 78
- 230000007704 transition Effects 0.000 claims abstract description 45
- 238000009792 diffusion process Methods 0.000 claims abstract description 37
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 239000007769 metal material Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 41
- 238000005516 engineering process Methods 0.000 claims description 21
- 229910000808 amorphous metal alloy Inorganic materials 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 16
- 229910052714 tellurium Inorganic materials 0.000 claims description 16
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 9
- 239000003292 glue Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 238000001035 drying Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 208000005189 Embolism Diseases 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 2
- 238000011049 filling Methods 0.000 claims 1
- 238000003860 storage Methods 0.000 description 12
- 238000012360 testing method Methods 0.000 description 11
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 238000009826 distribution Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- VEMKTZHHVJILDY-UHFFFAOYSA-N resmethrin Chemical compound CC1(C)C(C=C(C)C)C1C(=O)OCC1=COC(CC=2C=CC=CC=2)=C1 VEMKTZHHVJILDY-UHFFFAOYSA-N 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000005404 monopole Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of two-way gate tubes of the memory based on aluminium tellurium alloy and preparation method thereof, which includes：Substrate (1)；Wire laying slot is formed above substrate (1), and deposit diffusion barriers (3), diffusion impervious layer (3) covers whole wire laying slots surface, and electrode (2) is arranged in wire channels under tungsten wiring, is contacted with diffusion impervious layer (3)；Insulating layer (4), it is arranged under tungsten wiring on the surface of electrode (2) exposure, and it is in contact with electrode under tungsten wiring (2), there are two tungsten plugs (5) for setting in insulating layer (4), and the side wall of two tungsten plugs is covered by diffusion impervious layer (3), one of tungsten plug (5) is covered using threshold transitions layer (6) and is in contact with the lower electrode (2) of wiring, another tungsten plug (5) is covered with inert metal material and is contacted with the lower electrode (2) of wiring, forms lower contact conductor (7)；Top electrode (8) is arranged on threshold transitions layer (6).
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly to a kind of two-way choosing of the memory based on aluminium tellurium alloy
Siphunculus and preparation method thereof.
Background technology
Resistance-variable storing device (Resistive Random Access Memory, RRAM) technology is a kind of promising, non-
The memory technology of volatibility, due to its with simple structure and high density, non-volatile, speed is fast, low-power consumption, low cost
The features such as so that its potential flash memory technology instead of current mainstream.
Realize the business application of RRAM, it is necessary to be integrated RRAM storage units to form storage array.Wherein one
The method of a mainstream is exactly to improve the integration density of memory using right-angled intersection array (Crossbar) structure.Right-angled intersection
There are one storage units for each crossover node in array, and binary message is stored as high-impedance state or low resistance state.Cross
The memory cell size of crossed array can be reduced to 4F2.Importantly, can be very convenient using right-angled intersection array structure
Ground carries out three-dimensional stacked.N layer heap poststacks are carried out, the memory cell area of right-angled intersection array structure can more be reduced to 4F2/ N, from
And the storage density of RRAM is significantly increased.
But the characteristics of due to right-angled intersection array itself, it is difficult to avoid crosstalk (Crosstalk) from misreading the generation of phenomenon, i.e.,
Due to the presence of leakage current so that the high-impedance state of Destination Storage Unit is misread as low resistance state.This crosstalk phenomenon is stacked in 3 dimensions
It is more notable in structure.Past, the method for solving cross-interference issue in right-angled intersection array are mainly：In each variable-resistance memory unit
One diode (D) with rectification characteristic of upper series connection, constitutes 1D1R structures.But due to the single-phase on state characteristic of diode,
1D1R structures are only applicable to monopole resistive device.The use of diode simultaneously, not only increases process complexity, and due to two
The partial pressure of pole pipe resistance itself acts on, and after connecting with storage unit, not only results in the increase of operation voltage, and can deteriorate
The stability of memory device.
Still an alternative is that the two-way gate tube (Selector) for a non-diode of connecting in storage unit is constituted
1S1R structures.Two-way gate tube (S) is that a kind of current -voltage curve is nonlinear device, it is at low voltages and high voltages
Different resistive values it is very big, usually have the gap of several orders of magnitude.When voltage is less than threshold voltage (Vth), gate tube is cut
Only；And when higher than threshold voltage (Vth), gate tube conducting.The pattern of right-angled intersection array generally use 1/2Vread voltages
To read information.When implementing read operation, voltage in not selected storage unit is relatively low (to be less than Vth, can be 1/
2Vread), gate tube is in high-impedance state (OFF state), can prevent passing through for crossfire；And in selected storage unit
Voltage be Vread (be more than Vth), can normally read information.
When selecting gate tube, according to the demand of memory device, there are two important points for attention, i.e. driving current and electricity
The non-linear ratio of stream-voltage.In order to the variable-resistance memory unit that programmed and erased is selected, gate tube should have the ability to transmit high
Driving current.For example, a device area to be made to be that the resistive element of 10nm × 10nm changes, the transformation of 1 μ A is needed
Electric current, then the minimum current density that gate tube must provide is 1MA/cm2.In addition, the non-linear ratio of current-voltage can be determined
Justice at shift voltage V by the electric current of gate tube under the shift voltage (V/2) of half by the electric current of gate tube it
Than this ratio should reach 1000.
Although a kind of two end gating tube device reported at present has high current-voltage non-linear ratio
(nonlinearity, NL > 103), but enough driving currents, only 1 × 10 is not achieved in it-6A(Jeonghwan S.,et
al.Applied Physics Letters 107,113504(2015).)；Although another two end gates tube device ON state
Driving current is larger (500 μ A or so), but its current-voltage non-linear ratio is not high, only 102Magnitude (Wan Gee K.,
et al.IEEE/Symposium on VLSI Technology Digest of Technical Papers,2014)。
Invention content
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of depositing based on aluminium tellurium alloy
Two-way gate tube of reservoir and preparation method thereof can not only transmit high driving current to realize, but also have high current-voltage
The purpose of non-linear ratio.
In view of the above and other objects, the present invention proposes a kind of two-way gate tube of the memory based on aluminium tellurium alloy, including：
Substrate (1)；
Wire laying slot is formed above the substrate (1), and deposit diffusion barriers (3), the diffusion impervious layer (3) are covered
Whole tungsten plug channel surfaces have been covered, lower electrode (2) has been connected up and is arranged among the wire channels, with the diffusion impervious layer
(3) it contacts；
Insulating layer (4), be arranged under the wiring electrode (2) exposure surface on, and with electrode (2) under the wiring
It is in contact, there are two tungsten plugs (5) for setting in the insulating layer (4), and the side wall of the two tungsten plugs is by diffusion impervious layer
(3) it covers, one of tungsten plug (5) is covered using threshold transitions layer (6) and is in contact with electrode (2) under the wiring, separately
One tungsten plug (5) is then used inert metal material to cover and is contacted with electrode (2) under the wiring, and lower contact conductor (7) is formed；
Top electrode (8) is arranged on the threshold transitions layer (6).
Preferably, the forming process of electrode (2) is as follows under the wiring：By photoetching, etching above the substrate (1)
Wire laying slot is formed, the diffusion impervious layer (3) is deposited, is then filled up groove using deposits tungsten, finally passes through chemical machinery
Polishing forms the lower electrode (2) of wiring.
Preferably, the forming process of the tungsten plug (5) is as follows：Tungsten bolt is formed in insulating layer (4) by photoetching, etching
Consent hole deposits the diffusion impervious layer (3), etches away the diffusion impervious layer of hole bottom, then utilizes deposits tungsten by hole
It fills up, finally by chemically mechanical polishing, forms tungsten plug (5).
Preferably, thickness range 3nm~50nm of the wire laying slot diffusion impervious layer (3), the tungsten thickness are 50nm
~5000nm.
Preferably, thickness range 3nm~50nm of the tungsten plug hole diffusion impervious layer (3), the tungsten plug (5) are thick
Degree is 50nm~3000nm.
Preferably, the insulating layer (4) realizes deposition SiO using the method for PECVD2, low k dielectric materials mix F's or C
SiO2, porous SiO2Or SiOC, thickness range are 50~3000nm.
Preferably, two tungsten plug holes in the insulating layer (4) are formed after photoetching, dry or wet etch,
The diameter for the through-hole for forming two-way gate tube position is more preferably less than 10 microns.
Preferably, the threshold transitions layer (6) is aluminium tellurium thin film of amorphous alloy, is obtained by magnetic control co-sputtering,
Thickness range is 1nm~100nm.
Preferably, the top electrode (8), lower contact conductor (7) thickness range be 10nm-500nm.
Preferably, the top electrode (8), lower contact conductor (7) are other inert metal electrodes such as W or TiN or combinations thereof.
In order to achieve the above objectives, the present invention also provides a kind of preparation sides of the two-way gate tube of the memory based on aluminium tellurium alloy
Method includes the following steps：
Step S1, it is rectangular at wire laying slot on substrate by photoetching, etching, and deposit diffusion barriers, utilize deposition
Tungsten fills up wire laying slot, finally by chemically mechanical polishing, forms the lower electrode of wiring；
Step S2, using the method for PECVD in above-mentioned wiring lower electrode surface depositing insulating layer, and in the insulating layer
Corresponding position forms two tungsten plug holes；
Step S3, the deposit diffusion barriers in above-mentioned tungsten plug hole, and the diffusion impervious layer of hole bottom is etched away,
Tungsten plug hole is filled up using PECVD tungsten, finally forms tungsten plug by polishing.
Step S4, the spin coating photoresist on the silicon chip of above-mentioned tungsten plug structure are true using photoetching development technology after drying glue
Fix the positions and dimensions of contact conductor；
Step S5, using DC magnetron sputtering techniques, contact conductor under depositing tungsten metal；
Step S6 is dissolved extra photoresist and gone in addition to graphics using lift-off technology sample bubble in acetone soln
Extra tungsten metal prepares tungsten lower metal electrode lead；
Step S7, second of spin coating photoresist after drying glue, using photoetching development technology threshold value transition layer and power on
The positions and dimensions of pole；
Step S8, using magnetic control co-sputtering technology, threshold deposition transition layer；
Step S9, using DC magnetron sputtering techniques, depositing tungsten metal top electrode；
Step S10, using lift-off technology, sample bubble in acetone soln, dissolve extra photoresist and remove it is extra
Glue on material, realize the graphical of the threshold transitions layer and top electrode.
Compared with prior art, two-way gate tube of a kind of memory based on aluminium tellurium alloy of the invention and preparation method thereof exists
In tungsten plug structure, it is prepared for aluminium tellurium alloy film using the method for cosputtering, and due to the device of low scale on the material mating
Part size (tungsten plugs that 2 μm of diameter) is so that the gating tube device has outstanding performance；It is said from material angle, aluminium tellurium alloy
Film uniformity is good so that and each parameter of device is very stable, especially shows threshold voltage and open off-state current that distribution is concentrated, and
And the material has big current-voltage non-linear ratio (nonlinearty~6000), moreover, the ON state current of the material
A milliampere rank can be reached, be fully able to meet the requirement of storage unit reading and writing；For from device size, the present invention is implemented
Gate tube device size in example is 2um, and smaller size of device can further decrease the probability that short circuit occurs, further subtract
Gadget leakage current, to be expected to obtain higher current-voltage non-linear ratio.The present invention's is double based on aluminium tellurium alloy film
It can not only connect to gate tube with variable-resistance memory unit, be used for resistance-change memory array, can also connect with phase-change memory cell,
For in phase change memory array.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of the two-way gate tube of memory based on aluminium tellurium alloy of the invention；
Fig. 2 is a kind of step flow chart of the preparation method of the two-way gate tube of memory based on aluminium tellurium alloy of the invention；
Fig. 3 is that the present invention is based on aluminium tellurium thin film of amorphous alloy AlxTe1-x(x=0.39), thickness is the two-way choosing of 40nm
Current-voltage (I-V) characteristic curve of siphunculus；
Fig. 4 is that the present invention is based on aluminium tellurium thin film of amorphous alloy AlxTe1-x(x=0.44), thickness is the two-way choosing of 40nm
Current-voltage (I-V) characteristic curve of siphunculus；
Fig. 5 is that the present invention is based on aluminium tellurium thin film of amorphous alloy AlxTe1-x(x=0.44), thickness is the two-way choosing of 25nm
Current-voltage (I-V) characteristic curve of siphunculus.
Specific implementation mode
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand the further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under the spirit of the present invention.
Fig. 1 is a kind of structural schematic diagram of the two-way gate tube of memory based on aluminium tellurium alloy of the invention.As shown in Figure 1,
A kind of two-way gate tube of memory based on aluminium tellurium alloy of the invention, including：
Substrate 1, in the specific embodiment of the invention, the substrate 1 is the silicon chip of surface oxidation；
It is rectangular at wire laying slot on substrate, and deposit diffusion barriers 3, the diffusion impervious layer 3 cover whole cloth
Wire channel surface connects up lower electrode 2 and is arranged among wire channels, contacted with diffusion impervious layer 3.In the specific embodiment of the invention
In, electrode 2 is formed using standard CMOS process under the wiring, and specifically, forming process is as follows：By photoetching,
Etching is rectangular at wire laying slot on substrate, and deposit diffusion barriers Ti/TiN, thickness range 3nm~50nm use PECVD
(Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) deposits tungsten will
Groove fills up, and tungsten thickness is 50nm~5000nm, then by chemically mechanical polishing, is formed and connects up lower electrode 2；
Insulating layer 4 is arranged under wiring on the surface of the exposure of electrode 2, and is in contact with electrode 2 under wiring, in this hair
In bright specific embodiment, the insulating layer 4 realizes deposition SiO using the method for PECVD2, low k dielectric materials mix the SiO of F or C2、
Porous SiO2Or SiOC, thickness range are 50~3000nm, setting is there are two tungsten plug 5 in insulating layer 4, and the two tungsten
The side wall of embolism is covered by diffusion impervious layer 3, in the specific embodiment of the invention, the thickness of tungsten plug hole diffusion impervious layer 3
Ranging from 3nm~50nm, preferably, its thickness range is preferably 20nm~50nm, the thickness of tungsten plug 5 be 50nm~
3000nm, preferably, its thickness range is preferably 300nm~1000nm, one of tungsten plug 5 is covered with threshold transitions layer 6
And be in contact with electrode 2 under wiring, another tungsten plug 5 is then covered with inert metal material and is contacted with electrode 2 under wiring, shape
At lower contact conductor 7.In the specific embodiment of the invention, the two tungsten plugs 5 are the shapes after photoetching, dry or wet etch
At the diameter for the tungsten plug for forming two-way gate tube position is more preferably less than 10 microns.
Preferably, the threshold transitions layer 6 is aluminium (Al) tellurium (Te) thin film of amorphous alloy, obtained by magnetic control co-sputtering
It arrives, wherein aluminium is made using DC magnetron sputterings, and tellurium is sputtered using RF and is made.In practical applications, sputtered aluminum can also be passed through
Tellurium alloy target prepares aluminium tellurium alloy threshold transitions layer by MOCVD methods etc..It is described in the specific embodiment of the invention
AlxTe1-xContent x ranging from 33%≤x≤50% (actual experiment value) of Al atoms in threshold transitions layer, and it was found that gating
The leakage current of pipe reduces with the increase of aluminium content.(it is less than 30%) when Al content is very few, material is also easy to produce phase transition phenomena,
Threshold voltage disappears substantially, and device can not limit leakage current；(it is higher than 60%) when Al content is excessive, material is not susceptible to threshold value
Transformation, threshold voltage increase, and after recycling several times, device directly punctures.
Preferably, the thickness range of the threshold transitions layer 6 is 1nm~100nm (experimental thickness 25-40nm at present), when
When threshold transitions layer 6 is too thin, leakage current increases, and the electric current selection of device is than reducing；When threshold transitions layer is too thick, the threshold of device
Threshold voltage is very big, and device is difficult to reach ON state (on-state).
Top electrode 8 is arranged on threshold transitions layer 6, in the specific embodiment of the invention, the top electrode, lower electrode
The thickness range of lead is 30nm-500nm.The top electrode, lower contact conductor can be other inert metals such as W or TiN electricity
Pole or combinations thereof.
Fig. 2 is a kind of step flow chart of the preparation method of the two-way gate tube of memory based on aluminium tellurium alloy of the invention.
As shown in Fig. 2, a kind of preparation method of the two-way gate tube of memory based on aluminium tellurium alloy of the invention, includes the following steps：
Step S1 forms wire laying slot, and deposit diffusion barriers Ti/TiN by photoetching, etching above substrate 1, thick
Degree is 3nm~50nm；Wire laying slot is filled up with PECVD tungsten, tungsten thickness is 50nm~5000nm；By chemically-mechanicapolish polishing,
Form the lower electrode of wiring.
Step S2, using PECVD, (Plasma Enhanced Chemical Vapor Deposition, plasma increase
Extensive chemical vapour deposition process) method above-mentioned wiring lower electrode surface deposit SiO2Insulating layer, thickness are 50~3000nm, and
By the method for photoetching and dry etching in the SiO2Corresponding position forms two tungsten plug holes in insulating layer.
Step S3, the deposit diffusion barriers in above-mentioned tungsten plug hole, and hole bottom is etched away using dry etching method
Tungsten plug hole is filled up using PECVD deposits tungstens, finally forms tungsten bolt by chemically mechanical polishing by the diffusion impervious layer in portion
Plug, in the specific embodiment of the invention, the thickness range of tungsten plug hole diffusion impervious layer is 3nm~50nm, preferably, it is thick
Degree preferably ranges from 20nm~50nm, and tungsten plug thickness is 50nm~3000nm, preferably, its thickness range is preferably 300nm
~1000nm.
Step S4, the spin coating photoresist on the above-mentioned silicon chip for having tungsten plug structure, after drying glue, using photoetching development technology
Determine the positions and dimensions of lower contact conductor 7；
Step S5, using DC magnetron sputtering techniques, deposition W lower metal electrodes lead 7.
Step S6 is dissolved extra photoresist and gone in addition to graphics using lift-off technology sample bubble in acetone soln
Extra W metals prepare W lower metal electrodes lead 7；
Step S7, second of spin coating photoresist, after drying glue, using photoetching development technology threshold value transition layer 6 and upper
The positions and dimensions of electrode 8；
Step S8, using magnetic control co-sputtering technology, deposition of aluminum tellurium thin film of amorphous alloy, i.e. threshold transitions layer 6, wherein aluminium
Using DC magnetron sputterings, tellurium is sputtered using RF.Pure Al targets and pure Te targets, institute are used in the specific embodiment of the invention
It is pure Ar gas with sputter gas.
Step S9, using DC magnetron sputtering techniques, deposition W electrode of metal 8.
Step S10, using lift-off technology, sample bubble in acetone soln, dissolve extra photoresist and remove it is extra
Glue on material, realize the graphical of threshold transitions layer 6 and top electrode 8.
The tungsten plug size that threshold transition layer 6 is covered in the present embodiment is smaller, to reducing the leakage of two-way gating tube device
Electric current is more advantageous, and more advantageous to the current-voltage non-linear ratio for improving the device.
The present invention proposes a kind of two-way gate tube based on aluminium tellurium amorphous alloy.Due to the aluminium tellurium amorphous state in the device
Alloy is capable of providing charged trap so that when applying low-voltage to the device, carrier is limited by trap, reduces electric leakage
Stream；With the raising of external voltage, charged trap is constantly filled；When voltage value reaches a critical point, carrier is just filled out
Full trap, the mobility increase of carrier, so that electric current increases suddenly, has occurred threshold transitions at this time.But this threshold phenomenon
Different from phase transition phenomena, it is a kind of transformation electrically, and there is no the structural phase transitions of generating material.
Compared with prior art, the gate tube based on aluminium tellurium alloy of the present invention need not carry out electric initialization procedure (i.e.
), and its threshold voltage (V forming-freeth) distribution concentrate very much, gate tube ON state current Ion(V=0.7V) energy
Enough reach a milliampere rank (1mA), which is sufficient for the reading and writing operation of memory device connected in series.Gate tube is at V/2
Electric current, that is, OFF leakage current IoffOnly 1.7 × 10-7A.Therefore, the current-voltage non-linear ratio (definition of the gating tube device
For Ion/Ioff) 5900 can be reached, show outstanding switch performance.
Embodiment one
In the present embodiment, the threshold transitions layer 6 is the Al that thickness is 40nmxTe1-xAmorphous alloy.Described
Al atom contents in threshold transitions layer 6 are x=39%.
Cosputtering Al targets and Te targets are used in the present embodiment, and by adjusting being applied to the work(of Al targets and Te targets
Rate changes the ingredient of threshold transitions layer 6.Threshold transitions layer 6, the i.e. component of aluminium tellurium alloy film use x-ray photoelectron spectroscopy
(XPS) analysis-e/or determining obtains.
In the specific embodiment of the invention, above method system is tested using 4200 semiconductor parametric testers of Keithley
The two-way gating tube device obtained, obtains current-voltage (I-V) characteristic of the device, as shown in Figure 3.Positive and negative bias is equal when test
Lower electrode is added to, and top electrode is grounded always.The initial resistance of the two-way gating tube device based on aluminium tellurium amorphous alloy is
High-impedance state ,~2.25 × 106Ω, i.e. gate tube are in OFF state (off-state).The gate tube is without initializing (forming-
Free) process.Limitation electric current (I appropriate is set when testcc=1mA) to prevent device breakdown.Single voltage is used when test
Scanning method, scanning sequency are 0 → 1V；0→-1V.From figure 3, it can be seen that when voltage scanning to ± 0.7V or so, pass through device
Electric current increase suddenly, when electric current reaches limitation electric current 1mA, which is ON state (on-state), i.e. device
Part ON state current IonFor 1mA.Corresponding voltage is known as threshold voltage (V at the current break at this timeth).Due to device architecture
Symmetry, the I-V curve that as can be seen from Figure 3 positive negative sense voltage scanning is obtained is almost symmetry.It is elected to take away state electricity
When pressing V=± 0.7V, then the electric current at V/2=± 0.35V is the leakage current (I of deviceoff).It can obtain in figure 3,
In this embodiment, the leakage current I of the deviceoff6.1 × 10-7A or so, the current-voltage non-linear ratio (I of the deviceon/
Ioff) it is 1.6 × 103。
Embodiment two
In the present embodiment, the threshold transitions layer 6 is the Al that thickness is 40nmxTe1-xAmorphous alloy.The threshold
It is x=44% to be worth the Al atom contents in transition layer 6,
In the present embodiment, using two-way made from 4200 semiconductor parametric testers of the Keithley test above method
Tube device is gated, obtains current-voltage (I-V) characteristic of the device, as shown in Figure 4.Positive and negative bias adds to lower electricity when test
Pole, and top electrode is grounded always.The two-way gating tube device initial resistance based on aluminium tellurium amorphous alloy is high-impedance state ,~
8.81×106Ω, i.e. gate tube are in OFF state (off-state).The gate tube is without initializing (forming-free) process.
Limitation electric current (I appropriate is set when testcc=1mA) to prevent device breakdown.Single voltage scanning method, scanning are used when test
Sequence is 0 → 1V；0→-1V.From fig. 4, it can be seen that when voltage scanning to ± 0.7V or so, it is unexpected by the electric current of device
Increase, when electric current reaches limitation electric current 1mA, which is ON state (on-state), i.e. device ON state current
IonFor 1mA.Corresponding voltage is known as threshold voltage (V at this current breakth).Due to the symmetry of device architecture, from Fig. 4
It can be seen that the I-V curve that positive negative sense voltage scanning is obtained is almost symmetry.It is elected when taking on-state voltage V=± 0.7V,
Electric current at so V/2=± 0.35V is the leakage current (I of deviceoff).It can obtain in Fig. 4, it in this embodiment, should
The leakage current I of deviceoff1.7 × 10-7A or so, the current-voltage non-linear ratio (I of the deviceon/Ioff) reach 5.9 ×
103。
Gate tube device size in the embodiment of the present invention is 2um, if can be further using smaller device size
The probability that short circuit occurs is reduced, device creepage can be further decreased, to be expected to obtain higher current-voltage non-linear
Than.
Embodiment three
In the present embodiment, the threshold transitions layer 6 is the Al that thickness is 25nmxTe1-xAmorphous alloy.Described
Al atom contents in threshold transitions layer 6 are x=44%,
The present embodiment utilizes two-way gate tube made from 4200 semiconductor parametric testers of the Keithley test above method
Device obtains current-voltage (I-V) characteristic of the device, as shown in Figure 5.Positive and negative bias adds to lower electrode when test, and
Top electrode is grounded always.The two-way gating tube device initial resistance based on aluminium tellurium amorphous alloy be high-impedance state ,~3.33 ×
106Ω, i.e. gate tube are in OFF state (off-state).The gate tube is without initializing (forming-free) process.Due to this
The thickness of threshold transitions layer 5 is only 25nm in device, and when test sets smaller limitation electric current (Icc=300 μ A) with preventer
Part punctures.It is 0 → 0.8V that single voltage scanning method, scanning sequency are used when test；0→-0.8V.From fig. 5, it can be seen that when electricity
When pressure scanning extremely ± 0.6V or so, increased suddenly by the electric current of device, which is ON state (on-state),
That is device ON state current IonFor 300 μ A.Corresponding voltage is known as threshold voltage (V at this current breakth).Due to device architecture
Symmetry, the I-V curve that as can be seen from Figure 5 positive negative sense voltage scanning is obtained is almost symmetry.It is elected to take away state
When voltage V=± 0.6V, then the electric current at V/2=± 0.3V is the leakage current (I of deviceoff).It can obtain in Figure 5,
In this embodiment, the leakage current I of the deviceoff3.0 × 10-7A or so, the current-voltage non-linear ratio (I of the deviceon/
Ioff) reach 1.0 × 103。
In the embodiment, thickness, which is the device of 25nm threshold transitions layers, still stable cycle characteristics.When device ruler
It is very little when further decreasing, the probability of short circuit occurs since threshold transitions layer can be further decreased, it is expected to further decrease device
Leakage current, to improve the current-voltage non-linear ratio of device.
Compared with prior art, the present invention has the following advantages：
1) design principle of the invention according to two-way gating tube device, it is proposed that a kind of new threshold transitions material, i.e.,
AlxTe1-xAmorphous alloy, and symmetrical inert metal electrode is used, constitute W/AlxTe1-xThe two-way gating of/W sandwich structures
Pipe.Due to the charged trap and W/Al inside aluminium tellurium amorphous alloy materialxTe1-xThe collective effect of interface potential barrier, Ke Yiyou
Effect ground inhibition low-voltage region (V < | Vth|) two-way crossfire.When voltage increases above threshold voltage | Vth| when, aluminium
Tellurium amorphous alloy material internal trap is filled, and the mobility of carrier significantly improves, and electric current can increase suddenly, two-way at this time
Gating tube device is in ON state.Its ON state current (1mA) disclosure satisfy that the reading and writing operation for integrated storage unit of connecting,
Low leakage current and high current-voltage non-linear ratio (~5.9 × 103) can effectively inhibit the crosstalk in storage array electric
Stream solves the cross-interference issue in criss-cross construction.
It 2) can be by adjusting threshold transitions layer AlxTe1-xThe ingredient and thickness of alloy meets us to two-way gating
The requirement of tube device performance.It can obtain from Fig. 3, Fig. 4, when threshold transitions layer thickness is all 40nm, can be somebody's turn to do by changing
The Al content of layer carrys out the performance of adjusting means.With the increase (within the scope of 33%-50%) of Al content, it is found that leakage current is gradual
Reduce, current-voltage non-linear is than being presented increased trend.When Al content is constant (being fixed on 44%), with threshold transitions layer
The increase (25nm increases to 40nm) of thickness, such as Fig. 5, Fig. 4, it can be deduced that, leakage current reduces therewith, the current-voltage of device
Non-linear ratio increases.
When the size of device is smaller, leakage current is smaller, in the case where other conditions are constant, current-voltage non-linear
Than that can further increase.According to the certain principle of the depth-to-width ratio of device, after device size reduces, thickness also should be corresponding
Reduce.In embodiment 3 (such as Fig. 5), a diameter of 2 μm, thickness, which is the device of 25nm threshold transitions layers, still stable cycle
Characteristic, then it is expected that when device size further decreases, which will possess more excellent performance, such as：It is higher
Electric current selects ratio, stable cycle characteristics, more uniform threshold voltage and electric leakage flow distribution etc..
3) the two-way gating tube device has outstanding cyclical stability, and has very uniform leakage current, threshold value
The distribution of voltage and non-linear ratio.As can be seen that threshold voltage is concentrated mainly on the range of 0.7 ± 0.05V from Fig. 3, Fig. 4
It is interior；From fig. 5, it can be seen that threshold voltage is concentrated mainly on the range of 0.6 ± 0.05V.And the distribution of leakage current nor
It is often narrow.Moreover, in preparing sample, it is found that its yields is very high, this is to prepare the two-way gate tube device on a large scale
Part provides possibility.
4) it is different from certain gating tube devices, which does not need electric initialization procedure, i.e. forming-free, this is not only
The program in reading process has been simplified, forming processes has been also prevented and irreversible damage is caused to device.
5) preparation method selected by the present invention is simple for process, and whole technical process carry out at room temperature, simultaneous with CMOS technology
Hold, is suitble to efficiently large-scale two-way gating tube device of the preparation with excellent in performance.
6) the two-way gate tube based on aluminium tellurium alloy film of the invention is due to larger ON state current (1mA), institute
It can not only be connected with variable-resistance memory unit with it, be used for resistance-change memory array, can also connect, be used for phase-change memory cell
In phase change memory array.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Field technology personnel can without violating the spirit and scope of the present invention, and modifications and changes are made to the above embodiments.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (11)
1. a kind of two-way gate tube of memory based on aluminium tellurium alloy, including：
Substrate (1)；
Wire laying slot is formed above the substrate (1), and deposit diffusion barriers (3), the diffusion impervious layer (3) cover
Whole wire laying slot surfaces connect up lower electrode (2) and are arranged among the wire laying slot, contacted with the diffusion impervious layer (3)；
Insulating layer (4) is arranged under the wiring on the surface of electrode (2) exposure, and connects with electrode (2) under the wiring
It touches, there are two tungsten plugs (5) for setting in the insulating layer (4), and the side wall of the two tungsten plugs is covered by diffusion impervious layer (3)
Lid, one of tungsten plug (5) are covered using threshold transitions layer (6) and are in contact with electrode (2) under the wiring, another tungsten
Embolism (5) is then used inert metal material to cover and is contacted with electrode (2) under the wiring, and lower contact conductor (7) is formed；Top electrode
(8), it is arranged on the threshold transitions layer (6).
2. a kind of two-way gate tube of memory based on aluminium tellurium alloy as described in claim 1, which is characterized in that the wiring
The forming process of lower electrode (2) is as follows：Wire laying slot is formed above the substrate (1) by photoetching, etching, deposits the expansion
It dissipates barrier layer (3), is then filled up groove using deposits tungsten, finally by chemically mechanical polishing, form the lower electrode (2) of wiring.
3. a kind of two-way gate tube of memory based on aluminium tellurium alloy as described in claim 1, which is characterized in that the tungsten bolt
The forming process for filling in (5) is as follows：Tungsten plug hole is formed in insulating layer (4) by photoetching, etching, deposits the diffusion barrier
Layer (3), etches away the diffusion impervious layer of hole bottom, and then deposits tungsten fills up hole, finally by chemically mechanical polishing, shape
At tungsten plug (5).
4. a kind of two-way gate tube of memory based on aluminium tellurium alloy as claimed in claim 2, it is characterised in that：The wiring
Thickness range 3nm~50nm of groove diffusion impervious layer (3), the tungsten thickness are 50nm~5000nm.
5. a kind of two-way gate tube of memory based on aluminium tellurium alloy as claimed in claim 3, it is characterised in that：The tungsten bolt
Thickness range 3nm~50nm of consent hole diffusion impervious layer (3), tungsten plug (5) thickness are 50nm~3000nm.
6. a kind of two-way gate tube of memory based on aluminium tellurium alloy as claimed in claim 3, it is characterised in that：The insulation
Layer (4) realizes deposition SiO using the method for PECVD2, low k dielectric materials mix the SiO of F or C2, porous SiO2Or SiOC, thickness
Ranging from 50~3000nm.
7. a kind of two-way gate tube of memory based on aluminium tellurium alloy as claimed in claim 3, it is characterised in that：The insulation
Two tungsten plug holes in layer (4) are formed after photoetching, dry or wet etch, form the through-hole of two-way gate tube position
Diameter be more preferably less than 10 microns.
8. a kind of two-way gate tube of memory based on aluminium tellurium alloy as described in claim 1, it is characterised in that：The threshold value
Transition layer (6) is aluminium tellurium thin film of amorphous alloy, is obtained by magnetic control co-sputtering, and thickness range is 1nm~100nm.
9. a kind of two-way gate tube of memory based on aluminium tellurium alloy as described in claim 1, it is characterised in that：It is described to power on
Pole (8), lower contact conductor (7) thickness range be 10nm-500nm.
10. a kind of two-way gate tube of memory based on aluminium tellurium alloy as claimed in claim 9, it is characterised in that：On described
Electrode (8), lower contact conductor (7) are W or TiN or other inert metal electrodes or combinations thereof.
11. a kind of preparation method of the two-way gate tube of memory based on aluminium tellurium alloy, includes the following steps：
Step S1, it is rectangular at wire laying slot on substrate by photoetching, etching, and deposit diffusion barriers, utilize deposits tungsten will
Wire laying slot fills up, and finally forms the lower electrode of wiring by polishing；
Step S2, in above-mentioned wiring lower electrode surface depositing insulating layer, and corresponding position forms two tungsten in the insulating layer
Embolism hole；
Step S3, the deposit diffusion barriers in above-mentioned tungsten plug hole, and the diffusion impervious layer of hole bottom is etched away, it utilizes
Deposits tungsten fills up tungsten plug hole, finally forms tungsten plug by polishing.
Step S4, the spin coating photoresist on the silicon chip of above-mentioned tungsten plug structure, after drying glue, determine lower contact conductor position and
Size；
Step S5, using DC magnetron sputtering techniques, contact conductor under depositing tungsten metal；
Step S6 is dissolved extra photoresist and removes tungsten metal extra in addition to graphics, prepared tungsten metal using lift-off technology
Lower contact conductor；
Step S7, second of spin coating photoresist, the positions and dimensions of threshold value transition layer and top electrode after drying glue；
Step S8, using magnetic control co-sputtering technology, threshold deposition transition layer；
Step S9, using DC magnetron sputtering techniques, depositing tungsten metal top electrode；
Step S10 is dissolved extra photoresist and is removed material on extra glue using lift-off technology, realizes that the threshold value turns
Change layer and top electrode it is graphical.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7696077B2 (en) * | 2006-07-14 | 2010-04-13 | Micron Technology, Inc. | Bottom electrode contacts for semiconductor devices and methods of forming same |
| CN103050620A (en) * | 2011-10-11 | 2013-04-17 | 中国科学院上海微系统与信息技术研究所 | Phase-change material for phase-change memory |
| CN106910759A (en) * | 2017-02-22 | 2017-06-30 | 中国科学院微电子研究所 | Transition metal oxide-based selector and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7696077B2 (en) * | 2006-07-14 | 2010-04-13 | Micron Technology, Inc. | Bottom electrode contacts for semiconductor devices and methods of forming same |
| CN103050620A (en) * | 2011-10-11 | 2013-04-17 | 中国科学院上海微系统与信息技术研究所 | Phase-change material for phase-change memory |
| CN106910759A (en) * | 2017-02-22 | 2017-06-30 | 中国科学院微电子研究所 | Transition metal oxide-based selector and preparation method thereof |
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