CN108735696A - The perforation restorative procedure and repair system of three dimensional integrated circuits chip - Google Patents
The perforation restorative procedure and repair system of three dimensional integrated circuits chip Download PDFInfo
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- CN108735696A CN108735696A CN201710275907.2A CN201710275907A CN108735696A CN 108735696 A CN108735696 A CN 108735696A CN 201710275907 A CN201710275907 A CN 201710275907A CN 108735696 A CN108735696 A CN 108735696A
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The present invention provides a kind of the perforation restorative procedure and repair system of three dimensional integrated circuits chip, including：At least layers of chips to communicate with each other is provided；Electrical signal is transmitted using perforation between chip, same electrical signal corresponds to an at least perforation, provides at least one redundancy perforation of good performance；Before manufacture, the switching performance of perforation is tested by test module, stores corresponding restoration information in memory；When chip operation, memory is based on the restoration information and generates control signal, and by logical operation, will be without transmission electrical signal and the good redundancy perforation replacement undesirable perforation of switching performance of switching performance, the former electrical signal of transmission, to realize perforation reparation, reduce redundancy.
Description
Technical field
The present invention relates to IC design technical field more particularly to a kind of perforation reparations of three dimensional integrated circuits chip
Method and repair system.
Background technology
With SoC（System integrated chip）Scale it is increasing, 3DIC（Three dimensional integrated circuits）Since its is higher close
The advantages of degree, higher transmission rate and low-power consumption, is gradually valued by people and studies, and silicon hole（Through
Silicon Via, TSV）The density that technology can be such that chip stacks in three-dimensional is maximum, makes interconnection line between chip most
It is short, appearance and size is minimum, can effectively realize the stacking of this 3DIC, produce structure is more complicated, performance is more powerful, more
Cost-efficient 3DIC.
3DIC usually there will be the very big TSV of quantity, for example, 100 TSV, however due to the factors such as technique span is big,
Yield issues are always the big problem of TSV packaging methods.Such as Fig. 1（a）Shown in, if a signal is transmitted using 1 TSV,
Then the TSV yields of 3DIC are 0.In order to improve yield, many designs transmit an electrical signal to ensure chip using multiple TSV
Between switching performance it is good.For example, such as Fig. 1（b）Shown in, a signal is transmitted using 3 TSV, it is assumed that single TSV's is good
Rate is 99.9%, then it is 99.9999% that the TSV yields of 3DIC, which may be calculated (1-0.001^3) ^100,.However this method needs to compare
Larger chip area places TSV, and increased TSV can make the parasitic load of signal become larger.
Invention content
The purpose of the present invention is to provide the perforation restorative procedures and repair system of three dimensional integrated circuits chip, solve existing
Perforation redundancy in technology, the big technical problem of area occupied.
In order to solve the above technical problem, the present invention provides a kind of perforation restorative procedure of three dimensional integrated circuits chip, packets
It includes：
At least layers of chips to communicate with each other is provided；Electrical signal is transmitted using perforation between chip, same electrical signal corresponds to
In an at least perforation, at least one redundancy perforation of good performance is provided；
Before manufacture, the switching performance of perforation is tested by test module, stores corresponding restoration information in memory；
When chip operation, memory is based on the restoration information and generates control signal, and by logical operation, will be without transmission electricity
It learns signal and the good redundancy perforation of switching performance substitutes the undesirable perforation of switching performance, former electrical signal is transmitted, to realize
Perforation reparation reduces redundancy.
Optionally, reparation circuit is provided, the reparation circuit is connected to perforation of good performance, provides reparation enable signal
In the reparation circuit, the replacement of logical operation control perforation is carried out.
Optionally, perforation module is provided, repairs circuit；
The perforation module includes multichannel perforation circuit, described to include per road perforation circuit：Logical AND gate, the logical AND gate packet
It includes：First end, second end, the first end connection control signal；Enable signal, the logical AND are repaired in the second end connection
The third of door terminates control module；The input terminal of the control module is also connected with input signal, the input signal variation；
The reparation circuit includes：Logical AND gate, the logical AND gate include first end, second end, the first end and described
Enable signal is repaired in second end connection, and the third of the logical AND gate terminates control module, and the input terminal of the control module is also
Connect redundant input signal；Redundant input signal is constant to stablize.
Optionally, every road perforation circuit of the perforation module further includes：Logic sum gate, the first end of the logic sum gate
It is connected to the third end of this branch logical AND gate, second end is connected to the third end of logic sum gate in another way perforation circuit, this
The third end link control module of branch logic sum gate；
The reparation circuit includes：Logic sum gate, the first end of the logic sum gate are connected to the third of this branch logical AND gate
End, second end are connected to the third end of logic sum gate in perforation circuit all the way, the third end connection control of this branch logic sum gate
Module.
Optionally, the perforation is silicon perforation or non-silicon perforation.
Correspondingly, the present invention also provides a kind of perforation repair systems of three dimensional integrated circuits chip, including：
Perforation module repairs circuit；
The perforation module includes multichannel perforation circuit, described to include per road perforation circuit：Logical AND gate, the logical AND gate packet
It includes：First end, second end, the first end connection control signal；Enable signal, the logical AND are repaired in the second end connection
The third of door terminates control module；The input terminal of the control module is also connected with input signal, the input signal variation；
The reparation circuit includes：Logical AND gate, the logical AND gate include first end, second end, the first end and described
Enable signal is repaired in second end connection, and the third of the logical AND gate terminates control module, and the input terminal of the control module is also
Connect redundant input signal；Redundant input signal is constant to stablize.
Optionally, every road perforation circuit of the perforation module further includes：Logic sum gate, the first end of the logic sum gate
It is connected to the third end of this branch logical AND gate, second end is connected to the third end of logic sum gate in another way perforation circuit, this
The third end link control module of branch logic sum gate；
The reparation circuit includes：Logic sum gate, the first end of the logic sum gate are connected to the third of this branch logical AND gate
End, second end are connected to the third end of logic sum gate in perforation circuit all the way, the third end connection control of this branch logic sum gate
Module.
Compared with the existing technology, the perforation restorative procedure of three dimensional integrated circuits chip of the invention and repair system have with
Lower advantageous effect：
In the present invention, at least one redundancy perforation of good performance is provided, the switching performance of perforation, storage are tested by test module
When memory, chip operation, memory is based on the restoration information and generates control signal corresponding restoration information, and by patrolling
Operation is collected, it will be without transmission electrical signal and the good redundancy perforation replacement undesirable perforation of switching performance of switching performance, transmission
Former electrical signal, to realize perforation reparation, reduce redundancy.
Description of the drawings
Fig. 1 is the schematic diagram that perforation transmits signal in the prior art；
Fig. 2 is the flow chart of three dimensional integrated circuits chip perforation restorative procedure in one embodiment of the invention；
Fig. 3 is the structural schematic diagram of three dimensional integrated circuits chip in one embodiment of the invention；
Fig. 4 is the schematic diagram of three dimensional integrated circuits chip perforation repair system in one embodiment of the invention；
Fig. 5 is the schematic diagram of three dimensional integrated circuits chip perforation repair system in another embodiment of the present invention.
Specific implementation mode
Many details are elaborated in the following description in order to fully understand the present invention.But the present invention can be with
Much implement different from other manner described here, those skilled in the art can be without prejudice to intension of the present invention the case where
Under do similar popularization, therefore the present invention is not limited to the specific embodiments disclosed below.
Secondly, the present invention is described in detail using schematic diagram, when describing the embodiments of the present invention, for purposes of illustration only, institute
It is example to state schematic diagram, should not limit the scope of protection of the invention herein.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with attached drawing to the present invention
Three dimensional integrated circuits perforation restorative procedure and repair system be described in detail.
Embodiment one
Refering to what is shown in Fig. 2, the perforation restorative procedure of three dimensional integrated circuits chip provided by the invention, includes the following steps：
Step S1 provides at least layers of chips to communicate with each other, uses perforation to transmit electrical signal between chip, as three in Fig. 3
It includes chip 1 and chip 2 to tie up IC chip, and electrical signal is transmitted using perforation 11 between chip 1 and chip 2
（Signal）, the perforation 11 can be silicon perforation（Through Silicon Via, TSV）Or non-silicon perforation, perforation 11 include
The input/output module being located on chip 1 and chip 2（I/O）And the silicon perforation of connection chip 1 and chip 2（TSV）.
In the present invention, same electrical signal corresponds to an at least perforation.Also, at least one redundancy perforation 12 of good performance is provided, together
Sample, redundancy perforation 12 includes the input/output module for being located at chip 1 and chip 2（I/O）And connect chip 1
With the silicon perforation of chip 2（TSV）.It should be appreciated that the quantity of redundancy perforation 12 can be multiple, and redundancy perforation is connectivity
The good perforation of energy, multiple redundancy perforations can be used for completing the reparation to multiple bad perforations.
Step S2 tests the connectivity of perforation 11, redundancy perforation 12 by test module 20 before encapsulation chip manufacture
Can, whether the switching performance for testing multiple perforations 11 and redundancy perforation 12 is good, judges whether that switching performance is undesirable and passes through
Hole, bad perforation location information, formed restoration information, store corresponding restoration information in memory 30.
Step S3, when encapsulating chip operation, memory 30 is based on the restoration information and generates control signal, and by patrolling
Operation is collected, will be passed without transmission electrical signal and the good replacement of the redundancy perforation 12 undesirable perforation of switching performance of switching performance
The former electrical signal of the defeated undesirable perforation transmission of the switching performance, to realize perforation reparation, reduce redundancy.
Specifically, refering to what is shown in Fig. 4, perforation module 50 is provided, using the transmission electrical signal of perforation module 50 DQ in chip 1
<3.0>, the perforation module 50 includes multichannel perforation circuit, described that a perforation, every road are correspondingly connected with per road perforation circuit
Perforation circuit includes logical AND gate 51 and control module 52, and the logical AND gate 51 includes：First end, second end, described first
End connection control signal rep<3.0>In signal all the way；Enable signal EN_Red, the logic are repaired in the second end connection
Control module 52 is terminated with the third of door 51, the input terminal of the control module 52 is also connected with input signal DQ<3.0>In two
Road signal, the input signal DQ<3.0>For the electrical signal of 2 intermediate conveyor of chip 1 and chip, and input signal DQ<3.0
>For the signal of variation.
Further, it provides and repairs circuit 40, the reparation circuit 40 is connected to perforation of good performance, this is functional
Perforation as the redundancy perforation for replacement, provide and repair enable signal in the reparations circuit 40, progress logical operation control
The replacement of perforation processed.Shown in Fig. 4, the reparation circuit 40 includes logical AND gate 41 and control module 42, described to patrol
Volume include first end, second end with door 41, the first end and the second end, which are all connected with, repairs enable signal EN_Red, described
The third of logical AND gate 41 terminates control module 42, and the input terminal of the control module 42 is also connected with redundant input signal DQ_r,
And redundant input signal DQ_r is constant to stablize.
Test module 20 tests perforation, it is determined whether there are the position of bad perforation and bad perforation, memories
Corresponding control signal rep is generated according to corresponding position signal<3.0>, when encapsulating chip operation, perforation module 50 is read
Control signal rep<3.0>, and the control signal rep exported according to memory 30<3.0>Logical operation is carried out, and reparation makes
Redundancy perforation is substituted bad perforation by energy signal EN_red, and logical operation table is as follows：
| Bad perforation | Control signal（rep<3.0>） | Repair enable signal（EN_red） |
| 0 | 0001 | 1 |
| 1 | 0011 | 1 |
| 2 | 0111 | 1 |
| 3 | 1111 | 1 |
| None | ×××× | 0 |
When there are bad perforation, the perforation that enable signal is effective, and perforation module is repaired according to control signal determination needs is repaired,
It completes to replace according to logical operation.When there is no bad perforations（None）When, reparation enable signal is invalid, without repairing.Most
It is whole, by perforation module and circuit is repaired by input signal DQ<3.0>It is transferred to the TSV_PAD of corresponding branch road, by the TSV_
PAD is transmitted to the input/output module of chip 2（I/O）On, complete signal transmission.
Based on above-mentioned perforation restorative procedure, a kind of perforation reparation system of three dimensional integrated circuits chip is also provided in the present embodiment
System, the repair system include：Perforation module 50 repairs circuit 40.
Refering to what is shown in Fig. 4, the perforation module 50 includes multichannel perforation circuit, it is described to include per road perforation circuit：Logic
With door 51 and control module 52, the logical AND gate 51 includes：First end, second end, the first end connection control signal；Institute
It states second end connection and repairs enable signal, the third of the logical AND gate 51 terminates control module 52；The control module 52
Input terminal is also connected with input signal, the input signal variation.
The reparation circuit 40 includes：Logical AND gate 41 and control module 42, the logical AND gate 41 include first end, the
Two ends, the first end and the second end, which connect, repairs enable signal, and the third of the logical AND gate 41 terminates control module
42, the input terminal of the control module 42 is also connected with redundant input signal；Redundant input signal is constant to stablize.
Embodiment two
The present embodiment provides the perforation repair system of another three dimensional integrated circuits chip, which includes：Perforation module
50 ', circuit 40 ' is repaired.
Refering to what is shown in Fig. 5, the perforation module 50 ' includes multichannel perforation circuit, it is described to include per road perforation circuit：Logic
With door 51 ', control module 52 ' and logic sum gate 53 ', the logical AND gate 51 ' includes：First end, second end, the first end
Connection control signal rep<3.0>；Enable signal, the third terminating logic of the logical AND gate 51 are repaired in the second end connection
An or input terminal of door 52 '；The first end of the logic sum gate 53 ' is connected to the third end of this branch logical AND gate 51, and second
End is connected to the third end of logic sum gate 53 ' in another way perforation circuit（Output end）, the third end of this branch logic sum gate 53 '
Link control module 52 '；The input terminal of the control module 52 ' is also connected with input signal DQ<3.0>, the input signal change
Change.
The reparation circuit 40 ' includes logical AND gate 41 ', control module 42 ' and logic sum gate 43 ', the logical AND gate
41 ' include first end, second end, and the first end is connected with the second end repairs enable signal, the logical AND gate 41 '
The first end of one input terminal of third terminating logic or door 43 ', the logic sum gate 43 ' is connected to this branch logical AND gate 41 '
Third end, second end is connected to the third end of logic sum gate 43 ' in perforation circuit all the way（Output end）, this branch logic sum gate
The input terminal of 43 ' third end link control module 42 ', the control module 42 ' is also connected with redundant input signal DQ_r, redundancy
Input signal is constant to stablize.
The control signal rep that perforation module 50 ' is used to be exported according to memory<3.0>Logical operation is carried out, and according to repairing
Redundancy perforation is substituted bad perforation by multiple enable signal, and logical operation table is as follows：
| Bad perforation | Control signal（rep<3.0>） | Repair enable signal（EN_red） |
| 0 | 0001 | 1 |
| 1 | 0010 | 1 |
| 2 | 0100 | 1 |
| 3 | 1000 | 1 |
| None | ×××× | 0 |
In conclusion in the present invention, at least one redundancy perforation of good performance is provided；Before manufacture, tested by test module
The switching performance of perforation stores corresponding restoration information in memory；When chip operation, memory is based on the restoration information
Control signal is generated, and by logical operation, it will be without transmission electrical signal and switching performance good redundancy perforation replacement company
The undesirable perforation of performance is connect, former electrical signal is transmitted, to realize perforation reparation, reduce redundancy.
Although the invention has been described by way of example and in terms of the preferred embodiments, but it is not for limiting the present invention, any this field
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical solution makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, and according to the present invention
Technical spirit to any simple modifications, equivalents, and modifications made by above example, belong to technical solution of the present invention
Protection domain.
Claims (7)
1. a kind of perforation restorative procedure of three dimensional integrated circuits chip, which is characterized in that including：
At least layers of chips to communicate with each other is provided；Electrical signal is transmitted using perforation between chip, same electrical signal corresponds to
In an at least perforation, at least one redundancy perforation of good performance is provided；
Before manufacture, the switching performance of perforation is tested by test module, stores corresponding restoration information in memory；
When chip operation, memory is based on the restoration information and generates control signal, and by logical operation, will be without transmission electricity
It learns signal and the good redundancy perforation of switching performance substitutes the undesirable perforation of switching performance, former electrical signal is transmitted, to realize
Perforation reparation reduces redundancy.
2. the perforation restorative procedure of three dimensional integrated circuits chip according to claim 1, which is characterized in that provide and repair electricity
Road, the reparation circuit are connected to perforation of good performance, provide and repair enable signal in the reparation circuit, carry out logic fortune
Calculate the replacement of control perforation.
3. the perforation restorative procedure of three dimensional integrated circuits chip according to claim 1, which is characterized in that
Perforation module is provided, repairs circuit；
The perforation module includes multichannel perforation circuit, described to include per road perforation circuit：Logical AND gate, the logical AND gate packet
It includes：First end, second end, the first end connection control signal；Enable signal, the logical AND are repaired in the second end connection
The third of door terminates control module；The input terminal of the control module is also connected with input signal, the input signal variation；
The reparation circuit includes：Logical AND gate, the logical AND gate include first end, second end, the first end and described
Enable signal is repaired in second end connection, and the third of the logical AND gate terminates control module, and the input terminal of the control module is also
Connect redundant input signal；Redundant input signal is constant to stablize.
4. the perforation restorative procedure of three dimensional integrated circuits chip according to claim 3, which is characterized in that the perforation mould
The roads Kuai Mei perforation circuit further includes：Logic sum gate, the first end of the logic sum gate are connected to the of this branch logical AND gate
Three ends, second end are connected to the third end of logic sum gate in another way perforation circuit, the third end connection of this branch logic sum gate
Control module；
The reparation circuit includes：Logic sum gate, the first end of the logic sum gate are connected to the third of this branch logical AND gate
End, second end are connected to the third end of logic sum gate in perforation circuit all the way, the third end connection control of this branch logic sum gate
Module.
5. the perforation restorative procedure of three dimensional integrated circuits chip according to claim 1, which is characterized in that the perforation is
Silicon perforation or non-silicon perforation.
6. a kind of perforation repair system of three dimensional integrated circuits chip, which is characterized in that including：
Perforation module repairs circuit；
The perforation module includes multichannel perforation circuit, described to include per road perforation circuit：Logical AND gate, the logical AND gate packet
It includes：First end, second end, the first end connection control signal；Enable signal, the logical AND are repaired in the second end connection
The third of door terminates control module；The input terminal of the control module is also connected with input signal, the input signal variation；
The reparation circuit includes：Logical AND gate, the logical AND gate include first end, second end, the first end and described
Enable signal is repaired in second end connection, and the third of the logical AND gate terminates control module, and the input terminal of the control module is also
Connect redundant input signal；Redundant input signal is constant to stablize.
7. the perforation repair system of three dimensional integrated circuits chip according to claim 6, which is characterized in that the perforation mould
The roads Kuai Mei perforation circuit further includes：Logic sum gate, the first end of the logic sum gate are connected to the of this branch logical AND gate
Three ends, second end are connected to the third end of logic sum gate in another way perforation circuit, the third end connection of this branch logic sum gate
Control module；
The reparation circuit includes：Logic sum gate, the first end of the logic sum gate are connected to the third of this branch logical AND gate
End, second end are connected to the third end of logic sum gate in perforation circuit all the way, the third end connection control of this branch logic sum gate
Module.
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|---|---|---|---|
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| US20020053937A1 (en) * | 2000-06-21 | 2002-05-09 | Alan Lloyd | Selective modification of clock pulses |
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| US20110128072A1 (en) * | 2009-11-30 | 2011-06-02 | Hynix Semiconductor Inc. | Repair circuit and semiconductor apparatus including the same |
| US20150185274A1 (en) * | 2013-12-26 | 2015-07-02 | National Tsing Hua University | Apparatus of Three-Dimensional Integrated-Circuit Chip Using Fault-Tolerant Test Through-Silicon-Via |
| CN207558780U (en) * | 2017-04-25 | 2018-06-29 | 格科微电子（上海）有限公司 | The perforation repair system of three dimensional integrated circuits chip |
| CN209804604U (en) * | 2018-12-29 | 2019-12-17 | 格科微电子（上海）有限公司 | repair system for three-dimensional integrated circuit chip |
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- 2017-04-25 CN CN201710275907.2A patent/CN108735696A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020053937A1 (en) * | 2000-06-21 | 2002-05-09 | Alan Lloyd | Selective modification of clock pulses |
| US20100060310A1 (en) * | 2008-09-10 | 2010-03-11 | Qualcomm Incorporated | Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects |
| US20110128072A1 (en) * | 2009-11-30 | 2011-06-02 | Hynix Semiconductor Inc. | Repair circuit and semiconductor apparatus including the same |
| US20150185274A1 (en) * | 2013-12-26 | 2015-07-02 | National Tsing Hua University | Apparatus of Three-Dimensional Integrated-Circuit Chip Using Fault-Tolerant Test Through-Silicon-Via |
| CN207558780U (en) * | 2017-04-25 | 2018-06-29 | 格科微电子（上海）有限公司 | The perforation repair system of three dimensional integrated circuits chip |
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