CN108733572A - A kind of adjustment method and its system, relevant device of image-signal processor - Google Patents
A kind of adjustment method and its system, relevant device of image-signal processor Download PDFInfo
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Abstract
The application provides a kind of adjustment method and its system, relevant device of image-signal processor, the system includes terminal, FPGA boards and image-signal processor, image-signal processor includes the ISP module of multiple concatenations, wherein, initial Bayer image sequences are sent to first ISP module of concatenation by terminal for obtaining initial Bayer image sequences；Itself treated the Bayer image sequence for receiving that each ISP module sends, and the Bayer image sequences received are preserved；Each ISP module, for carrying out corresponding picture signal processing operation to the Bayer image sequences received, and treated that Bayer image sequences are sent to terminal by itself, in this way, each ISP module can treated that Bayer image sequences are sent to terminal by itself, therefore, the debugging difficulty of image-signal processor can be reduced, and then shortens the development cycle of image-signal processor.
Description
Technical field
This application involves the adjustment method of technical field of image processing more particularly to a kind of image-signal processor and its it is
System, relevant device.
Background technology
In practical application, camera mainly obtains image information by sensor, and the image of sensor output is believed
Breath be need just people is supplied to watch after image-signal processor is handled, or be input in NI Vision Builder for Automated Inspection into
Row storage, since the application places of camera are than wide, and function, performance of the different application places to image-signal processor
Requirement it is different, so how rapidly to develop adapt to different application scene image-signal processor be badly in need of solve
The problem of.
Usually, the development procedure of image-signal processor is first to obtain some original Bayer image sequences from sensor
Row, then write picture signal Processing Algorithm program, and authentication image signal processing in terminal using matlab, C or C++
Algorithm writes Verilog VHDL generations to the picture signal treatment effects of Bayer image sequences again on software after the completion of verification
Code carries out functional simulation, and emulation reuses corresponding FPGA developing instruments after completing and the code file write is compiled into camera
Program after compiling is finally downloaded to and carries out actual test inside the camera developed based on FPGA by workable program.
Specifically, Bayer image sequences collected to camera, by image-signal processor to these Bayer images
Sequence carries out picture signal processing, and finally, by camera, by treated, Bayer image sequences are sent to terminal, and terminal preserves simultaneously
Show these Bayer image sequences, and then these Bayer image sequences shown according to terminal by developer analyze image
The picture signal treatment effect of signal processor.In practical application, image-signal processor generally all includes multiple carry out images
The picture signal of signal processing handles (Image Signal Processing, ISP) module, and each ISP module can be right
Bayer image sequences carry out a type of picture signal processing operation, therefore, a large amount of centre that when test will produce in fact
Image Bayer image sequences, the picture signal that these Bayer image sequences analyze developer image-signal processor are handled
Effect is very helpful, but since camera only supports USB or gigabit network interface, even and if USB3.0 interfaces also only have 5Gbps
Bandwidth, bandwidth is smaller, and no normal direction terminal transmission carries out a large amount of intermediate Bayer figures generated in picture signal processing procedure
As sequence, therefore, the debugging of image-signal processor is will increase compared with difficulty, and then extend the exploitation week of image-signal processor
Phase.
Invention content
The embodiment of the present application provides a kind of adjustment method and its system of image-signal processor, relevant device and system,
It is more difficult to solve debugging in the prior art to image-signal processor, and then extend the development cycle of image-signal processor
The problem of.
In a first aspect, a kind of debugging system of image-signal processor provided by the embodiments of the present application, including terminal, FPGA
Board and image-signal processor, and image-signal processor includes the ISP module of multiple concatenations, wherein：
Initial Bayer image sequences are sent to the of concatenation by terminal for obtaining initial Bayer image sequences
One ISP module；Itself treated Bayer image sequence for receiving that each ISP module sends by bus, and to receiving
Bayer image sequences are preserved；
Each ISP module, for carrying out corresponding picture signal processing operation to the Bayer image sequences received, and
By itself, treated that Bayer image sequences are sent to terminal.
In practical application, image-signal processor is made of multiple ISP modules, and image-signal processor is to initial
Each ISP module will produce a large amount of intermediate Bayer image sequences when Bayer image sequences carry out picture signal processing, in these
Between Bayer image sequences be the important references information for analyzing image signal processing effect, but due to the supported band of camera interface
Wide smaller, these intermediate Bayer image sequences can not be transferred to terminal by camera, therefore can increase the survey of image-signal processor
Difficulty is tried, and then extends the development cycle of image-signal processor, and in above system, departing from camera, by means of FPGA
Board debugs image-signal processor, and data transfer bandwidth between FPGA boards and terminal is no longer limited, each
ISP module can by itself, treated that Bayer image sequences are sent to terminal, therefore, it is possible to reduce image-signal processor
Debugging difficulty, and then shorten image-signal processor development cycle.
In first test and in the ISP module in needing deletion FPGA boards, the ISP module of above-mentioned multiple concatenations is equal
It is arranged in FPGA boards.
And when the ISP module in FPGA boards to be adjusted or the increase ISP module in FPGA boards, then it needs at end
Increase the ISP module of bridge joint in end, which can be concatenated with the ISP module in FPGA boards, to change Bayer figures
As the transmission path of sequence, to the picture signal treatment effect of the image-signal processor after being adjusted, this
In the case of, there are the settings of at least one ISP module in the ISP module of above-mentioned multiple concatenations in the terminal, remaining ISP module is still
It is arranged in FPGA boards.
Under a kind of possible embodiment, terminal is connected with FPGA boards by bus, and the bandwidth of the bus is more than
Setting value, at this point, the ISP module being arranged in FPGA boards can be by the bus by itself treated Bayer image sequence
Row are sent to terminal.
Under a kind of possible embodiment, terminal is specifically used for：Initial Bayer image sequences are obtained from external camera
Row, or initial Bayer image sequences are obtained from local Bayer image libraries, in this way, as long as can provide
The equipment of Bayer image sequences all can be used as the source device of Bayer image sequences in this system, it is desirable that and it is relatively low, therefore, system
Availability is more preferable, also, even external camera, and requirement of the system to camera is also only to provide Bayer image sequences, in this way,
Complete machine need not be researched and developed, therefore, the debugging difficulty of image-signal processor can be further decreased.
Second aspect, a kind of adjustment method of image-signal processor provided by the embodiments of the present application, including：
Terminal obtains initial Bayer image sequences, and initial Bayer image sequences are sent to picture signal processing
First ISP module in the ISP module of multiple concatenations in device；
Each ISP module in image-signal processor carries out corresponding image letter to the Bayer image sequences received
Number processing operation, and treated that Bayer image sequences are sent to terminal by itself；
Terminal receives itself treated Bayer image sequence that each ISP module in image-signal processor is sent, and
The Bayer image sequences received are preserved.
Under a kind of possible embodiment, the ISP module of multiple concatenations in image-signal processor is arranged at
In FPGA boards.
It is at least one in the ISP module of multiple concatenations in image-signal processor under a kind of possible embodiment
ISP module is arranged in the terminal, remaining ISP module is arranged in FPGA boards.
Under a kind of possible embodiment, terminal is connected with FPGA boards by bus, and the bandwidth of the bus is more than
Setting value, by itself, treated that Bayer image sequences are sent to end by the bus for the ISP module being arranged in FPGA boards
End.
Under a kind of possible embodiment, terminal obtains initial Bayer image sequences, specifically includes：
Initial Bayer image sequences are obtained from external camera, or are obtained initially from local Bayer image libraries
Bayer image sequences.
The third aspect, the embodiment of the present application provide a kind of image-signal processor, which includes multiple
The ISP module of concatenation, wherein：
Each ISP module, for carrying out corresponding picture signal processing operation to the Bayer image sequences received, and
By itself, treated that Bayer image sequences are sent to terminal.
Under a kind of possible embodiment, the ISP module of multiple concatenations is arranged in FPGA boards.
Under a kind of possible embodiment, at least one ISP module is arranged in terminal in the ISP module of multiple concatenations
In, remaining ISP module is arranged in FPGA boards.
Under a kind of possible embodiment, terminal is connected with FPGA boards by bus, and the bandwidth of the bus is more than
Setting value, by itself, treated that Bayer image sequences are sent to end by the bus for the ISP module being arranged in FPGA boards
End.
Fourth aspect, a kind of terminal provided by the embodiments of the present application, including：
Acquisition module, for obtaining initial Bayer image sequences；
Sending module, for initial Bayer image sequences to be sent to multiple concatenations in image-signal processor
First ISP module in ISP module；
Memory module, itself for receiving that each ISP module sends treated Bayer image sequences, and to receiving
Bayer image sequences preserved.
5th aspect, the embodiment of the present application provide a kind of FPGA boards, which includes any of the above-described kind of image letter
Number processor.
In addition, technique effect caused by any design method can be found in first aspect in second aspect to the 5th aspect
Technique effect caused by middle difference realization method, details are not described herein again.
These aspects or other aspects of the application can more straightforward in the following description.
Description of the drawings
Fig. 1 is the schematic diagram of the debugging system of image-signal processor provided by the embodiments of the present application；
Fig. 2 is the schematic diagram of the debugging system of another image-signal processor provided by the embodiments of the present application；
Fig. 3 provides the schematic diagram of the function of a certain ISP module in adjustment image-signal processor for the embodiment of the present application；
Fig. 4 is the flow chart of the adjustment method of image-signal processor provided by the embodiments of the present application；
Fig. 5 is the schematic diagram of image-signal processor provided by the embodiments of the present application；
Fig. 6 is the schematic diagram of terminal provided by the embodiments of the present application；
Fig. 7 is the schematic diagram of another terminal provided by the embodiments of the present application；
Fig. 8 is the schematic diagram of FPGA boards provided by the embodiments of the present application.
Specific implementation mode
In order to reduce the debugging difficulty of image-signal processor, shorten the development cycle of image-signal processor, the application
Embodiment provides a kind of adjustment method of image-signal processor, apparatus and system.
Usually, image-signal processor is developed using FPGA developing instruments, in the prior art, is developing figure
As after signal processor, needing the picture signal by the camera test image signal processor using FPGA exploitations to handle effect
Fruit, but since the supported bandwidth of camera is smaller, finally obtained Bayer image sequences can only be sent to terminal, exploit person
During member is unable to get intermediate treatment therefore generated a large amount of Bayer image sequences are unfavorable for picture signal processing
Device is debugged, and in the embodiment of the present application, the test carrier of image-signal processor is replaced by the camera developed using FPGA
FPGA boards are changed to, the data transfer bandwidth between terminal and FPGA boards is no longer limited, each ISP moulds in image-signal processor
Block can will return to terminal from a large amount of Bayer image sequences generated when picture signal processing, therefore, can drop
The debugging difficulty of low image-signal processor, and then shorten the development cycle of image-signal processor.
Also, the performance requirement for the FPGA boards in the prior art, being attached with itself due to camera pair is also relatively high,
So the hardware cost of test is also relatively high, and in the embodiment of the present application, come at picture signal using FPGA boards as carrier
Reason device is debugged, as long as FPGA boards have the bus interface for meeting bandwidth requirement, to the performance requirement of FPGA boards
Want much lower, so, the optional range of FPGA boards is wider, in this way, the type selecting difficulty of the FPGA boards of development phase can be reduced,
In addition, in the case of meeting use condition at the same time, can also be selected to this lower FPGA board, with further decrease exploitation at
This.
The embodiment of the present application is described in detail with reference to the accompanying drawings of the specification.
In practical application, after writing and having verified the picture signal treatment effect of image-signal processor, it can pass through
FPGA tools corresponding with FPGA boards by the Program transformation write be can programming program, and then by program burn writing in FPGA plates
In card, in this way, the picture signal treatment effect of image-signal processor can be debugged by means of FPGA boards.
Embodiment one
The schematic diagram of the debugging system of image-signal processor provided by the embodiments of the present application is shown referring to Fig. 1, Fig. 1,
Including terminal, FPGA boards and image-signal processor, wherein terminal includes processor, and image-signal processor includes multiple
The ISP module of (being n in Fig. 1, n is integer) concatenation, and the ISP module of this n concatenation is placed in FPGA boards, each
ISP module is used to carry out a kind of picture signal processing operation, wherein：
Terminal is sent to concatenation for obtaining initial Bayer image sequences, and by initial Bayer image sequences
First ISP module, and itself for receiving that each ISP module sends treated Bayer image sequences, and to receiving
These Bayer image sequences preserved.
When it is implemented, terminal can obtain initial Bayer image sequences from external camera, it can also be from local
Initial Bayer image sequences are obtained in Bayer image libraries.
Each ISP module, for carrying out corresponding picture signal processing operation to the Bayer image sequences received, and
By itself, treated that Bayer image sequences are sent to terminal.
When it is implemented, since the sequence that ISP module handles Bayer image sequences is different, the function of each ISP module
Different, specifically, first ISP module is used to carry out the initial Bayer image sequences received from terminal corresponding
Picture signal processing, and treated that Bayer image sequences are sent to next ISP module and terminal by itself；Except first
Each ISP module a and except the last one, for being carried out to the Bayer image sequences received from a upper ISP module
Corresponding picture signal processing operation, and treated that Bayer image sequences are sent to next ISP module and end by itself
End；The last one ISP module, for carrying out corresponding image letter to the Bayer image sequences received from a upper ISP module
Number processing operation, and treated that Bayer image sequences are sent to terminal by itself.
In practical application, terminal can show the Bayer image sequences finally received to developer, i.e., at picture signal
The finally obtained Bayer image sequences of device are managed, because the Bayer image sequences can intuitively reflect image-signal processor
Picture signal treatment effect, developer may be used also if it is considered to the treatment effect of finally obtained Bayer image sequences is undesirable
Treated to recall each ISP module preserved in terminal Bayer image sequences, and then analyze these Bayer image sequences
Determine the adjustment mode to image-signal processor.
Mode one：It adjusts any ISP module in FPGA boards or increases ISP module.
Here, ISP module to be adjusted and ISP module to be increased can be referred to as target ISP module, are embodied
When, ISP module to be adjusted be developer according to each ISP module preserved in terminal treated Bayer image sequences into
Row determines, but ISP module to be increased i.e. but developer is according to each ISP module preserved in terminal treated Bayer
What image sequence determined, it can also be what developer determined according to other demands of image-signal processor.
Further, after determining target ISP module, developer can utilize software-programming languages in the terminal,
Such as matlab, C or C++, writes the corresponding picture signal Processing Algorithm program of target ISP module and preserve, the picture signal
Processing Algorithm program realizes the picture signal processing function of target ISP module, therefore, is considered as being added to mesh in the terminal
ISP module is marked, later, developer can configure initial Bayer image sequences target ISP module in the terminal and FPGA plates
Pass order breath in card between related ISP module, after the completion of configuration, is again handled initial Bayer image sequences,
It can check the picture signal treatment effect of image-signal processor after adjusting.
In this way, not being adjusted to related ISP module in image-signal processor not instead of directly, first with software programming
Language realizes the corresponding picture signal Processing Algorithm of target ISP module in the terminal, later, changes the original of Bayer image sequences
Beginning transmission path, make path between the ISP module chosen in its target ISP module that can be in the terminal and FPGA according to setting into
Row transmits, also, the Bayer image sequences that each ISP module being transferred to receives itself are handled, and by itself
Treated, and Bayer image sequences pass to terminal, so the Bayer image sequences finally shown from terminal can be intuitively
Picture signal treatment effect to after this adjustment, because what is utilized is true Bayer image sequences, that assesses is accurate
Property higher, debugging effect is also more accurate.
Mode two：Delete any ISP module in FPGA boards.
If needing to delete any ISP module in FPGA boards when it is implemented, developer determines, can directly configure
Pass order of the initial Bayer image sequences in FPGA boards between remaining ISP module, later, initial Bayer image sequences
Row can skip the ISP module for needing to delete according to the pass order of configuration, be carried out between remaining ISP module only in FPGA boards
It transmits, also, the Bayer image sequences that each ISP module being transferred to receives itself are handled, and will be in certainly
Bayer image sequences after reason pass to terminal, so the Bayer image sequences finally shown from terminal can be intuitive to see
The picture signal treatment effect of image-signal processor after certain ISP module is deleted, later, is handled according to the picture signal after adjustment
Effect determines whether that the corresponding ISP module of the deletion, debud mode are more reasonable again.
No matter which kind of above-mentioned debud mode, if when it is implemented, developer think this time adjust picture signal processing
Effect is still not good enough, can also continue in the manner described above one or mode two be adjusted, until adjustment after image letter
Number treatment effect carries out actual adjustment to FPGA boards again after reaching desired effects.
Specifically, developer can utilize specified programming language to write target program such as Verilog or VHDL, should
Target program realizes the picture signal processing function of each ISP module in image-signal processor when reaching desired effects, so
Afterwards, recycle corresponding with FPGA boards FPGA developing instruments by target program be compiled into can the program of programming finally can journey
The debugging to image-signal processor is completed in sequence programming in FPGA boards, in this way, the effect in determining debugging reaches expected
After effect, then the available target program of FPGA boards is write, can avoid writing Verilog VHDL codes repeatedly and being emulated
Operation, therefore the debugging difficulty of image-signal processor can be further decreased, shorten the development cycle of image-signal processor.
Particularly, when the corresponding picture signal Processing Algorithm of ISP module to be increased is more complicated, compared to existing skill
Art, aforesaid way can more show the advantage for reducing and writing Verilog VHDL code operations back and forth.
In addition, when it is implemented, terminal and FPGA boards can be more than the bus (external bus) of setting value by bandwidth
It is connected, at this point, terminal and FPGA boards all have bus interface, such as PCIe bus interface, in this way, between terminal and FPGA boards
It can be attached by PCIe buses, the bandwidth of PCIe buses is up to 20Gbps, it is ensured that have foot between terminal and FPGA boards
Enough bandwidth carry out a large amount of intermediate Bayer image sequences caused by each ISP module in image signal transmission processor, at this point,
The ISP module in FPGA boards is arranged can by itself, treated that Bayer image sequences are sent to terminal by the bus；
And when certain ISP module in image-signal processor is arranged in the terminal, these ISP modules then can be directly by terminal
Treated that Bayer image sequences issue terminal by itself for portion's bus.
As shown in Fig. 2, be the schematic diagram for the debugging system that the application implements the another image-signal processor provided, including
Terminal, FPGA boards and image-signal processor, wherein include PCIe drivings, acquisition module, debugging module and display in terminal
Module, terminal are also circumscribed with camera, are connected by USB or gigabit network interface between terminal and camera；Image-signal processor
Including PCIe interface management module, control module, ISP module 1, ISP module 2, ISP module 3 ... ISP module n, each ISP
Module is for carrying out a type of picture signal processing operation, at this point, this n ISP module is respectively positioned in FPGA boards, and
It is connected by PCIe buses between FPGA boards and terminal, the bandwidth of PCIe buses may be up to 20Gbps, there are enough bandwidth
Transmit a large amount of intermediate Bayer image sequences caused by each ISP module of FPGA board kinds.
Assuming that ISP module 1 is used to carry out black-level correction to image sequence, ISP module 2 is for adjusting the bright of image sequence
Degree, ISP module 3 are used to adjust contrasts of saturation degree ... the ISP module n of image sequence for adjusting image sequence.
When it is implemented, there are mainly two types of operating modes for above-mentioned debugging system, one is debugging efforts pattern, another kind is
Cooperative work of software and hardware pattern is below introduced both operating modes respectively.
Camera can acquire initial Bayer image sequences 0 in real time, and acquisition module can obtain Bayer image sequences from camera
0, and driven using PCIe and Bayer image sequences 0 are sent to PCIe interface management module.
Assuming that pass order when initial is：ISP module 1->ISP module 2->ISP module 3 ... ISP module n, then
Under debugging efforts pattern, the Bayer image sequences 0 received can be sent to ISP module 1 by PCIe interface management module, by
ISP module 1 carries out black-level correction to every Bayer images in Bayer image sequences 0, and later, ISP module 1 can be by itself
Treated, and Bayer image sequences 1 are sent to debugging module by PCIe buses, by debugging module to Bayer image sequences 1 into
Row preserves, meanwhile, ISP module 1 can treated that Bayer image sequences 1 are sent to ISP module 2 by itself, right by ISP module 2
Every Bayer images in Bayer image sequences 1 carry out brightness adjustment, and similarly, ISP module 2 can treated by itself
Bayer image sequences 2 are sent to debugging module by PCIe buses, are preserved to Bayer image sequences 2 by debugging module,
ISP module 2 can also by itself, treated that Bayer image sequences 2 are sent to ISP module 3, by ISP module 3 to Bayer images
The saturation degree of every Bayer images is adjusted in sequence 2 ... ISP module n, can when receiving Bayer image sequence n-1
Be adjusted to obtain Bayer image sequences n to the contrast of every Bayer images in Bayer image sequences n-1, i.e., it is final
Bayer image sequences, and Bayer image sequences n is sent to PCIe interface management module, PCIe interface management module will
Bayer image sequences n is sent to display module, is shown to the Bayer images in Bayer image sequences n by display module.
When it is implemented, debugging module is when receiving each ISP module treated Bayer image sequences, it can
It will be shown on corresponding position, it is contrasted with the Bayer image sequences shown with display module, facilitates developer true
The place being adjusted is needed calmly.If developer thinks that the picture signal treatment effect of Bayer image sequences n does not reach the phase
It hopes effect, then can analyze the Bayer image sequence 1~Bayer image sequences n-1 stored in debugging module, it is determined whether need
Adjust, increase newly or delete some ISP module.
For adjusting certain ISP module, as shown in figure 3, for the ISP module 3 in adjustment Fig. 2 provided by the embodiments of the present application
Schematic diagram, need adjust ISP module 3 when, developer can first program in the terminal realize ISP module 3 ' function, ISP
Module 3 ' is the optimization to 3 function of ISP module, an ISP module 3 ' is increased in the terminal in this way, being equivalent to, at this point, image
At least one ISP module of signal processor is located in terminal, and then, the reconfigurable Bayer image sequences of developer 0 exist
Pass order between 1~n of ISP module 3 ' and ISP module, at this point, pass order is ISP module 1->ISP module 2->ISP
Module 3 ' ... ISP module n, so cooperative work of software and hardware model validation adjustment after image-signal processor image information
Treatment effect.
Referring to Fig. 3, under cooperative work of software and hardware pattern, Bayer images that PCIe interface management module can will receive
Sequence 0 is sent to ISP module 1, and black level school is carried out to every Bayer images in Bayer image sequences 0 by ISP module 1
Just, later, ISP module 1 can treated that Bayer image sequences 1 are sent to debugging module by PCIe buses by itself, by adjusting
Die trial block preserves Bayer image sequences 1, meanwhile, ISP module 1 can treated that Bayer image sequences 1 are sent out by itself
ISP module 2 is given, brightness adjustment is carried out to every Bayer images in Bayer image sequences 1 by ISP module 2, similarly,
ISP module 2 can treated that Bayer image sequences 2 are sent to debugging module by PCIe buses by itself, by debugging module pair
Bayer image sequences 2 are preserved, if debugging has been actually received ISP module 2 according to the mark of Bayer image sequences
Treated Bayer image sequences 2, then can notify ISP module 3 ' to handle Bayer image sequences 2, later, ISP module
3 ' can treated that Bayer image sequences 3 ' are then forwarded to ISP module 4, subsequent process flow by PCIe buses by itself
Identical as under debugging efforts pattern, details are not described herein.
In the above process, ISP module 3 ' is equivalent to the optimization and upgrading to 3 function of ISP module, by by Bayer image sequences
Row 2 are sent to ISP module 3 ' and are handled, then Bayer image sequences 3 ' are transferred to ISP module 4 by ISP module 3 ' and are carried out
The mode of reason has skipped ISP module 3, in this way, can be adjusted to the function of ISP module in FPGA 3 first, so that it may most from terminal
The Bayer image sequences shown eventually are intuitive to see the picture signal treatment effect of image-signal processor after debugging, can reduce
Developer writes the number of Verilog or VHDL program, shortens the development cycle of image-signal processor.
When it is implemented, if developer thinks the picture signal treatment effect of image-signal processor after this time adjusting still
It is so undesirable, it can continue to be adjusted in this manner, details are not described herein for adjustment process, until developer thinks to adjust
When the picture signal treatment effect of image-signal processor achieves the desired results afterwards, then in terminal using Verilog or
VHDL writes target program to realize the function of the currently used each ISP module of system, and develops work using corresponding FPGA
Tool by target program be converted into can programming program, and by program burn writing in FPGA boards, to complete to picture signal
Manage the update of the picture signal processing capacity of device.
In the embodiment of the present application, using terminal will be responsible for the camera of Image Acquisition and be responsible for carrying out picture signal processing
FPGA boards separate so that the exploitation of image-signal processor is not entirely dependent on the camera of Image Acquisition, that is to say, that as long as
The equipment that Bayer images can be exported may serve to provide image, it is not necessary to complete machine be researched and developed again, so research staff can be reduced
Workload, also, FPGA boards can further decrease image-signal processor as long as with can be used as long as PCIe bus interface
Hardware development environment builds difficulty.
Particularly, under soft or hard combination operating mode, the relatively high image letter of some complexities can be carried out using terminal
The verification of number Processing Algorithm when algorithm has reached desired effect, then writes Verilog VHDL codes to realize, can be big
The big development rate for accelerating image-signal processor.
In the embodiment of the present application, initial testing and need delete FPGA boards in any ISP module when, image letter
Each ISP module in number processor is arranged in FPGA boards, when needing to adjust or delete any ISP in FPGA boards
When module, the ISP module part in image-signal processor is arranged in FPGA boards, and a part is arranged in the terminal, and
The ISP module in FPGA boards is arranged can by itself, treated that Bayer image sequences are sent to end by PCIe buses
End.
Embodiment two
Corresponding to the debugging system for the image-signal processor that embodiment one provides, the embodiment of the present application also provides a kind of figure
As the adjustment method of signal processor, this method can be executed according to flow chart shown in Fig. 4, be included the following steps：
S401：Terminal obtains initial Bayer image sequences, and initial Bayer image sequences are sent to image letter
First ISP module in the ISP module of multiple concatenations in number processor.
When it is implemented, initial Bayer image sequences can be obtained from external camera, it can also be from local
Initial Bayer image sequences are obtained in Bayer image libraries.
S402：Each ISP module in image-signal processor schemes the Bayer image sequences received accordingly
As signal processing operations, and by itself, treated that Bayer image sequences are sent to terminal.
Specifically, first ISP module is used to carry out the initial Bayer image sequences received from terminal corresponding
Picture signal processing, and treated that Bayer image sequences are sent to next ISP module and terminal by itself；Except first
With each ISP module except the last one, for carrying out phase to the Bayer image sequences that are received from a upper ISP module
The picture signal processing operation answered, and treated that Bayer image sequences are sent to next ISP module and terminal by itself；
The last one ISP module, for carrying out corresponding picture signal to the Bayer image sequences received from a upper ISP module
Processing operation, and treated that Bayer image sequences are sent to terminal by itself.
S403：Terminal receives itself treated Bayer image sequence that each ISP module in image-signal processor is sent
Row, and the Bayer image sequences received are preserved.
When it is implemented, if developer thinks the picture signal treatment effect for the Bayer image sequences that terminal is shown not
Ideal, the then each ISP module that can be stored in analysing terminal treated Bayer image sequences are determined to need to be adjusted
Place increases an ISP module newly, or delete some ISP module for example, adjusting the function of certain ISP module.
S404：Judge whether the picture signal treatment effect of image-signal processor reaches desired effects, if so, into
S407；Otherwise, into S405.
S405：Terminal obtains the corresponding picture signal Processing Algorithm program of target ISP module and preserves, wherein target ISP
Module is ISP module to be increased or is any ISP module to be adjusted in FPGA boards.
S406：Between corresponding ISP module in initial Bayer image sequences object module in the terminal and FPGA boards
Pass order configured, return S401.
S407：The target program write with specified programming language is obtained, the corresponding FPGA developing instruments of FPGA boards are utilized
By target program be converted to can programming program, by program burn writing in FPGA boards.
Wherein, target program realizes each in image-signal processor when reaching desired picture signal treatment effect
The picture signal processing function of ISP module, and the picture signal treatment effect of each ISP module is that developer is last according to terminal
What the Bayer image sequences received determined.
When it is implemented, if it is determined that needing to delete any ISP module in FPGA boards, then step S405~S406 then may be used
It replaces with：It configures between other ISP modules of the initial Bayer image sequences in FPGA boards in addition to deleting ISP module
Pass order returns to S401.
In the above process, in any ISP module during FPGA boards are deleted in initial testing and needing, at picture signal
Each ISP module in reason device is arranged in FPGA boards, when needs adjust or delete any ISP module in FPGA boards
When, the ISP module part in image-signal processor is arranged in FPGA boards, part setting in the terminal, also,
Under a kind of possible embodiment, terminal and FPGA boards can be connected by bus (external bus, such as PCIe buses), then this
When, it is arranged that the ISP module in FPGA boards can treated that Bayer image sequences are sent to end by itself by the bus
End.
Embodiment three
As shown in figure 5, for the schematic diagram of image-signal processor provided by the embodiments of the present application, including multiple concatenations
ISP module：
Each ISP module, for carrying out corresponding picture signal processing operation to the Bayer image sequences received, and
By itself, treated that Bayer image sequences are sent to terminal.
Under a kind of possible embodiment, the ISP module of multiple concatenations is arranged in FPGA boards.
Under a kind of possible embodiment, at least one ISP module is arranged in terminal in the ISP module of multiple concatenations
In, remaining ISP module is arranged in FPGA boards.
Under a kind of possible embodiment, terminal is connected with FPGA boards by bus (external bus), and the bus
Bandwidth be more than setting value, at this point, the ISP module being arranged in FPGA boards can by itself, treated by the bus
Bayer image sequences are sent to terminal.
Example IV
It is shown in Figure 6, it is a kind of structural schematic diagram of terminal 600 provided by the embodiments of the present application.The terminal 600 includes
The physical devices such as transceiver 601 and processor 602, wherein processor 602 can be a central processing unit
(central processing unit, CPU), microprocessor, application-specific integrated circuit, programmable logic circuit, large-scale integrated
Circuit or for digital processing element etc..Transceiver 601 carries out data transmit-receive for terminal and other equipment.
The terminal can also include memory 603, and the software instruction for storing the execution of processor 602 certainly can be with
Store some other data that terminal needs, such as the encryption information of the identification information of terminal, terminal, user data.Memory
603 can be volatile memory (volatile memory), such as random access memory (random-access
Memory, RAM)；Memory 603 can also be nonvolatile memory (non-volatile memory), such as read-only storage
Device (read-only memory, ROM), flash memory (flash memory), hard disk (hard disk drive, HDD) or
Solid state disk (solid-state drive, SSD) or memory 603 can be used for carrying or storing with instruction or number
According to structure type desired program code and can by any other medium of computer access, but not limited to this, memory
603 can be the combination of above-mentioned memory.
Above-mentioned processor is not limited in the embodiment of the present application, specifically connecting between 602, memory 603 and transceiver 601
Connect medium.The embodiment of the present application between memory 603, processor 602 and transceiver 601 in figure 6 only to pass through bus 604
It is illustrated for connection, bus is indicated with thick line in figure 6, the connection type between other components, is only to carry out schematically
Illustrate, does not regard it as and be limited.The bus can be divided into address bus, data/address bus, controlling bus etc..For ease of indicating, Fig. 6
In only indicated with a thick line, it is not intended that an only bus or a type of bus.
Processor 602 can be specialized hardware or the processor of runs software, when processor 602 can be with runs software,
Processor 602 reads the software instruction that memory 603 stores, and under the driving of the software instruction, executes previous embodiment
The method that middle terminal is related to.
Embodiment five
It, can in terminal when the method provided in the embodiment of the present application is realized with software or hardware or software and hardware combining
To include multiple function modules, each function module may include software, hardware or its combination.Specifically, it is shown in Figure 7,
For a kind of structural schematic diagram of terminal 700 provided by the embodiments of the present application, which includes acquisition module 701, sending module
702, memory module 703, wherein：
Acquisition module 701, for obtaining initial Bayer image sequences；
Sending module 702, multiple concatenations for being sent to initial Bayer image sequences in image-signal processor
ISP module in first ISP module；
Memory module 703, itself for receiving that each ISP module sends treated Bayer image sequences, to receiving
Treated, and Bayer image sequences are preserved.
Under a kind of possible embodiment, acquisition module 701 is specifically used for：
Initial Bayer image sequences are obtained from external camera, or are obtained initially from local Bayer image libraries
Bayer image sequences.
Embodiment six
As shown in figure 8, being a kind of schematic diagram of FPGA boards provided by the embodiments of the present application, which may include
State any image-signal processor.
It should be understood by those skilled in the art that, embodiments herein can be provided as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the application
Apply the form of example.Moreover, the application can be used in one or more wherein include computer usable program code computer
The computer program production implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.)
The form of product.
The application is flow of the reference according to method, apparatus (system) and computer program product of the embodiment of the present application
Figure and/or block diagram describe.It should be understood that can be realized by computer program instructions every first-class in flowchart and/or the block diagram
The combination of flow and/or box in journey and/or box and flowchart and/or the block diagram.These computer programs can be provided
Instruct the processor of all-purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine so that the instruction executed by computer or the processor of other programmable data processing devices is generated for real
The device for the function of being specified in present one flow of flow chart or one box of multiple flows and/or block diagram or multiple boxes.
These computer program instructions, which may also be stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that instruction generation stored in the computer readable memory includes referring to
Enable the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one box of block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device so that count
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, in computer or
The instruction executed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although the preferred embodiment of the application has been described, created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the application range.
Obviously, those skilled in the art can carry out the application essence of the various modification and variations without departing from the application
God and range.In this way, if these modifications and variations of the application belong to the range of the application claim and its equivalent technologies
Within, then the application is also intended to include these modifications and variations.
Claims (16)
1. a kind of debugging system of image-signal processor, which is characterized in that including the processing of terminal, FPGA boards and picture signal
Device, described image signal processor include the picture signal processing ISP module of multiple concatenations, wherein：
The initial Bayer image sequences are sent to concatenation by the terminal for obtaining initial Bayer image sequences
First ISP module；Itself treated the Bayer image sequence for receiving that each ISP module sends, and to described in receiving
Bayer image sequences are preserved；
Each ISP module, for carrying out corresponding picture signal processing operation to the Bayer image sequences received, and will be certainly
Treated that Bayer image sequences are sent to the terminal for body.
2. the system as claimed in claim 1, which is characterized in that the ISP module of the multiple concatenation is arranged at the FPGA
In board.
3. the system as claimed in claim 1, which is characterized in that at least one ISP module in the ISP module of the multiple concatenation
It is arranged in the terminal, remaining ISP module is arranged in the FPGA boards.
4. system as claimed in claim 2 or claim 3, which is characterized in that the terminal is connected with the FPGA boards by bus,
And the bandwidth of the bus is more than setting value, the ISP module being arranged in the FPGA boards will be in certainly by the bus
Bayer image sequences after reason are sent to the terminal.
5. the system as described in claims 1 to 3 is any, which is characterized in that the terminal obtains initial Bayer image sequences
Row, are specifically used for：
The initial Bayer image sequences are obtained from external camera, or
The initial Bayer image sequences are obtained from local Bayer image libraries.
6. a kind of adjustment method of image-signal processor, the method includes：
Terminal obtains initial Bayer image sequences, and the initial Bayer image sequences are sent to picture signal processing
First ISP module in the ISP module of multiple concatenations in device；
Each ISP module in described image signal processor carries out corresponding image letter to the Bayer image sequences received
Number processing operation, and treated that Bayer image sequences are sent to the terminal by itself；
Itself treated Bayer image sequence that the terminal receives that each ISP module in described image signal processor sends
Row, and the Bayer image sequences received are preserved.
7. method as claimed in claim 6, which is characterized in that the ISP moulds of multiple concatenations in described image signal processor
Block is arranged in FPGA boards.
8. method as claimed in claim 6, which is characterized in that the ISP moulds of multiple concatenations in described image signal processor
At least one ISP module is arranged in the terminal in block, remaining ISP module is arranged in FPGA boards.
9. method as claimed in claim 7 or 8, which is characterized in that the terminal is connected with the FPGA boards by bus,
And the bandwidth of the bus is more than setting value, the ISP module being arranged in the FPGA boards will be in certainly by the bus
Bayer image sequences after reason are sent to the terminal.
10. the method as described in claim 6~8 is any, which is characterized in that terminal obtains initial Bayer image sequences, tool
Body includes：
The initial Bayer image sequences are obtained from external camera, or
The initial Bayer image sequences are obtained from local Bayer image libraries.
11. a kind of image-signal processor, which is characterized in that described image signal processor includes the picture signal of multiple concatenations
ISP module is handled, wherein：
Each ISP module, for carrying out corresponding picture signal processing operation to the Bayer image sequences received, and will be certainly
Treated that Bayer image sequences are sent to the terminal for body.
12. image-signal processor as claimed in claim 11, which is characterized in that the ISP module of the multiple concatenation is all provided with
It sets in FPGA boards.
13. image-signal processor as claimed in claim 11, which is characterized in that in the ISP module of the multiple concatenation extremely
A few ISP module is arranged in the terminal, remaining ISP module is arranged in FPGA boards.
14. the image-signal processor as described in claim 11 or 12, which is characterized in that the terminal and the FPGA boards
It is connected by bus, and the bandwidth of the bus is more than setting value, the ISP module being arranged in the FPGA boards passes through described
Treated that Bayer image sequences are sent to the terminal by itself for bus.
15. a kind of terminal, which is characterized in that including：
Acquisition module, for obtaining initial Bayer image sequences；
Sending module, for the initial Bayer image sequences to be sent to multiple concatenations in image-signal processor
First ISP module in ISP module；
Memory module, itself for receiving that the multiple ISP module sends treated Bayer image sequences, and to receiving
To the Bayer image sequences preserved.
16. a kind of FPGA boards, which is characterized in that include the image-signal processor as described in claim 11~14 is any.
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| CN201810540288.XA CN108733572B (en) | 2018-05-30 | 2018-05-30 | Debugging method and system of image signal processor and related equipment |
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| CN201810540288.XA CN108733572B (en) | 2018-05-30 | 2018-05-30 | Debugging method and system of image signal processor and related equipment |
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| US20050240820A1 (en) * | 2004-03-31 | 2005-10-27 | Vannerson Eric F | Method and apparatus for multiprocessor debug support |
| CN102244790A (en) * | 2011-06-27 | 2011-11-16 | 展讯通信（上海）有限公司 | Device and method for adaptively adjusting supporting parameters of image signal processor |
| CN104243834A (en) * | 2013-06-08 | 2014-12-24 | 杭州海康威视数字技术股份有限公司 | Image streaming dividing control method and device of high-definition camera |
| US9959192B1 (en) * | 2015-09-15 | 2018-05-01 | Google Llc | Debugging interface for inserted elements in a resource |
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|---|---|---|---|---|
| US20050240820A1 (en) * | 2004-03-31 | 2005-10-27 | Vannerson Eric F | Method and apparatus for multiprocessor debug support |
| CN102244790A (en) * | 2011-06-27 | 2011-11-16 | 展讯通信（上海）有限公司 | Device and method for adaptively adjusting supporting parameters of image signal processor |
| CN104243834A (en) * | 2013-06-08 | 2014-12-24 | 杭州海康威视数字技术股份有限公司 | Image streaming dividing control method and device of high-definition camera |
| US9959192B1 (en) * | 2015-09-15 | 2018-05-01 | Google Llc | Debugging interface for inserted elements in a resource |
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