CN108733389A - A kind of Flash data analysis filter - Google Patents
A kind of Flash data analysis filter Download PDFInfo
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- CN108733389A CN108733389A CN201810551270.XA CN201810551270A CN108733389A CN 108733389 A CN108733389 A CN 108733389A CN 201810551270 A CN201810551270 A CN 201810551270A CN 108733389 A CN108733389 A CN 108733389A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
- G06F8/63—Image based installation; Cloning; Build to order
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Abstract
The present invention relates to flash memory technology fields more particularly to a kind of Flash data to analyze filter.The present invention provides a kind of Flash data analysis filter, in flash memory and LA（Logic analyser）Between concatenate FPGA platelets, FPGA is programmed, circuit design is described by VHDL hardware description languages, then ALE (the address command lines for passing through flash memory）Or CLE (flash order wires）It is triggered.The present invention can reduce workload when analysis data, reduce use cost, simple in structure to largely reduce user data because the data packet for retaining specific length can be set.
Description
Technical field
The present invention relates to flash memory technology fields more particularly to a kind of Flash data to analyze filter.
Background technology
In flash memory industry, product problem is needed to carry out data analysis, usual manner is exactly to be connected to flash memory by LA（Figure
2）, data are captured, data analysis is then carried out, but LA itself is the equipment of a data grabber, he cannot carry out data
It distinguishes, so the data of crawl have system data（System data includes system operatio order, and address starts guiding data）With with
User data（User data includes file partition table, user's storage file）.Conventional LA（With reference to model TL2236, with reference to list
Valence 8000RMB）Installed System Memory only has 72Mbit, the data of crawl also can only just capture 100-200ms, this data length connects one
A start-up course cannot all capture completion, medium-to-high grade LA（With reference to model TL3234B+/LA3036B with reference to unit price 27000/
56000RMB）This LA can capture whole system start-up course, but because comprising user data, be needed when analysis
Data Classification and Identification is carried out, workload is huge.
Invention content
In view of the deficiencies in the prior art or insufficient, the technical solution that the present invention takes is to provide a kind of Flash numbers
According to analysis filter, in flash memory and LA（Logic analyser）Between concatenate FPGA platelets, FPGA is programmed, VHDL is passed through
Circuit design is described in hardware description language, then ALE (the address command lines for passing through flash memory）Or CLE (flash orders
Line）It is triggered.
As a further improvement on the present invention, FPGA is programmed, is included the following steps：
Step 1：Filter data was set, order is only retained；
Step 2：Setting retains fixed data length；
As a further improvement on the present invention, trigger condition is in ALE CLE rising edges.
As a further improvement on the present invention, to not meeting the packet discard of step 1 and step 2, to meeting step
One is connected to LA with the data of step 2 by analyzing filter plate（Logic analyser）, carry out artificial data analysis.
As a further improvement on the present invention, to RE (read command control lines）And WE（Write order control line）It is counted,
Coordinate ALE and CLE, retains specific length data packet.
The beneficial effects of the invention are as follows：The present invention can reduce workload when analysis data, reduce use cost, because
It is simple in structure to largely reduce user data for the data packet for retaining specific length can be set.
Description of the drawings
Fig. 1 is flow chart provided by the invention；
Fig. 2 is prior art products structure chart；
Fig. 3 is the schematic diagram for having used data analysis filter；
Fig. 4 is the structural schematic diagram that this patent directly concatenates FPGA platelets in flash memory and LA.
Specific implementation mode
The present invention is further described for explanation and specific implementation mode below in conjunction with the accompanying drawings.
As shown in Figure 1, the present invention provides a kind of Flash data analysis filter, in flash memory and LA（Logic analyser）It
Between concatenate FPGA platelets, FPGA is programmed, circuit design is described by VHDL hardware description languages, then passes through
ALE (the address command lines of flash memory）Or CLE (flash order wires）It is triggered.
FPGA is programmed, is included the following steps：
Step 1：Filter data was set, order is only retained；
Step 2：Setting retains fixed data length；
Trigger condition is in ALE CLE rising edges.
To not meeting the packet discard of step 1 and step 2, to meeting the data of step 1 and step 2 by dividing
It analyses filter plate and is connected to LA（Logic analyser）, carry out artificial data analysis.Manual analysis judgment criterion is according to flash open source informations
It is analyzed with engineer's working experience, analytical challenge is the abundant degree of working experience.Because considerably reducing data
Amount, such as the flash of existing mainstream is 16K page, once-through operation data volume is 18Kbytes, using reservation 8 after filter plate
Data are 8bytes（The mono- operation front flash is that 6 address dates, 2 order datas are followed by user data）, data are
Before 1/2250th, so the analysis difficulty of engineer is greatly lowered
To RE (read command control lines）And WE（Write order control line）It is counted, coordinates ALE and CLE, retain specific length number
According to packet.
Such as：Setting retains 8 data lengths, by counter O reset when ALE or CLE once rising edges,
Then connection flash and LA detects RE and WE and the number of failing edge occurs, start-stop counter often occur and add 1, when counter reaches
To the connection cut off when 8 times between flash and LA, once counter is reset again when ALE or CLE is reappeared,
It is connected to the data filtering that flash and LA carries out a new round.（Note：Flash operations RE and WE is low effective, and ALE and CLE are
High effectively, effectively operating falsh can respond, and invalid operation flash will not be responded）
If having used data analysis filter in flash data crawl（Fig. 3）, filter can directly filter user data
Or retain the data packet of setting length, only retain order and address uses conventional LA or middle height when problem analysis
The LA of shelves can capture complete start-up course, and because the data packet for retaining specific length can be set, to a large amount of
User data is reduced, workload when analysis data is reduced.
The realization method of data filter directly concatenates FPGA platelets in flash memory and LA（Fig. 4）, FPGA is programmed,
Pass through ALE (the address command lines of flash memory）Or CLE (flash order wires）It is triggered, to reach a reserved address and life
This effect is enabled, and can be to RE (read command control lines）WE（Write order control line）It is counted, coordinates ALE and CLE, from
And reach reservation specific length（Free setting）Data packet.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
The specific implementation of the present invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the present invention's
Protection domain.
Claims (5)
1. a kind of Flash data analyzes filter, it is characterised in that：In flash memory and LA（Logic analyser）Between concatenation FPGA it is small
Plate is programmed FPGA, and circuit design is described by VHDL hardware description languages, then ALE (for passing through flash memory
Location order wire）Or CLE (flash order wires）It is triggered.
2. Flash data according to claim 1 analyzes filter, it is characterised in that：FPGA is programmed, including
Following steps：
Step 1：Filter data was set, order is only retained；
Step 2：Setting retains fixed data length.
3. Flash data according to claim 1 analyzes filter, it is characterised in that：Trigger condition be in ALE or
When CLE rising edges.
4. Flash data according to claim 2 analyzes filter, it is characterised in that：To not meeting step 1 and step
Two packet discard is connected to LA with the data of step 2 to meeting step 1 by analyzing filter plate（Logic analyser）,
Carry out artificial data analysis.
5. Flash data according to claim 1 analyzes filter, it is characterised in that：To RE (read command control lines）With
WE（Write order control line）It is counted, coordinates ALE and CLE, retain specific length data packet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810551270.XA CN108733389A (en) | 2018-05-31 | 2018-05-31 | A kind of Flash data analysis filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810551270.XA CN108733389A (en) | 2018-05-31 | 2018-05-31 | A kind of Flash data analysis filter |
Publications (1)
| Publication Number | Publication Date |
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| CN108733389A true CN108733389A (en) | 2018-11-02 |
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|---|---|---|---|
| CN201810551270.XA Pending CN108733389A (en) | 2018-05-31 | 2018-05-31 | A kind of Flash data analysis filter |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100005343A1 (en) * | 2006-08-03 | 2010-01-07 | Kazushi Yamamoto | Peripheral device, integrated circuit for peripheral device and method for analyzing failure of peripheral device |
| CN201655336U (en) * | 2010-03-24 | 2010-11-24 | 青岛海信电器股份有限公司 | Serial flash debugging circuit based on FPGA and television set with same |
| CN107633867A (en) * | 2017-09-20 | 2018-01-26 | 南京扬贺扬微电子科技有限公司 | SPI Flash test system and method based on FT4222 |
-
2018
- 2018-05-31 CN CN201810551270.XA patent/CN108733389A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100005343A1 (en) * | 2006-08-03 | 2010-01-07 | Kazushi Yamamoto | Peripheral device, integrated circuit for peripheral device and method for analyzing failure of peripheral device |
| CN201655336U (en) * | 2010-03-24 | 2010-11-24 | 青岛海信电器股份有限公司 | Serial flash debugging circuit based on FPGA and television set with same |
| CN107633867A (en) * | 2017-09-20 | 2018-01-26 | 南京扬贺扬微电子科技有限公司 | SPI Flash test system and method based on FT4222 |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 518000 Intelligence Valley Innovation Park 701, 707, No. 1010 Bulong Road, Xinniu Community, Minzhi Street, Longhua District, Shenzhen City, Guangdong Province Applicant after: SHENZHEN DEMINGLI ELECTRONICS Co.,Ltd. Address before: 518000, 701, building 7, wisdom Valley Innovation Park, people's street, Longhua District, Shenzhen, Guangdong Applicant before: SHENZHEN DEMINGLI ELECTRONICS Co.,Ltd. |
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| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 518000 Intelligence Valley Innovation Park 701, 707, No. 1010 Bulong Road, Xinniu Community, Minzhi Street, Longhua District, Shenzhen City, Guangdong Province Applicant after: Shenzhen deminli Technology Co.,Ltd. Address before: 518000 Intelligence Valley Innovation Park 701, 707, No. 1010 Bulong Road, Xinniu Community, Minzhi Street, Longhua District, Shenzhen City, Guangdong Province Applicant before: SHENZHEN DEMINGLI ELECTRONICS Co.,Ltd. Address after: Room 2501, 2401, block a, building 1, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Applicant after: Shenzhen deminli Technology Co.,Ltd. Address before: 518000 Intelligence Valley Innovation Park 701, 707, No. 1010 Bulong Road, Xinniu Community, Minzhi Street, Longhua District, Shenzhen City, Guangdong Province Applicant before: Shenzhen deminli Technology Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181102 |