CN108732666A - A kind of grating lithographic method - Google Patents
A kind of grating lithographic method Download PDFInfo
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- CN108732666A CN108732666A CN201710239753.1A CN201710239753A CN108732666A CN 108732666 A CN108732666 A CN 108732666A CN 201710239753 A CN201710239753 A CN 201710239753A CN 108732666 A CN108732666 A CN 108732666A
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
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Abstract
Grating lithographic method provided by the invention grows coating photoresist and front baking after resist layer in monocrystal silicon substrate；It is developed in the preparation that monocrystal silicon substrate surface carries out sectored light resist mask figure using uv-exposure；Using resist layer corrosive agent and monocrystalline process silicon etching solution by sectored light resist mask pattern transfer to monocrystal silicon substrate, the crystal orientation that etching phenomenon difference determines monocrystal silicon substrate is corresponded to using different rectangular strips in fan-shaped mask graph；After the crystal orientation for determining monocrystal silicon substrate, the making of formal grid photo-etching glue mask graph is carried out using uv-exposure development；Formal grid photo-etching glue mask graph is transferred on resist layer using resist layer corrosive agent and obtains resist layer mask graph and photoresist removal is carried out to layer mask figure against corrosion；Resist layer mask graph is transferred in monocrystal silicon substrate using monocrystalline process silicon etching solution, cleaning treatment is carried out to monocrystal silicon substrate, effectively improves grating etch rate ratio in length and breadth, the grating to producing high-aspect-ratio has direct important value.
Description
Technical field
The present invention relates to spectral technique field, more particularly to a kind of grating lithographic method.
Background technology
Using X-ray grating as the grating spectrometer of dispersion element have light weight, simple in structure, spectral region is wide, system pair
The advantages that standard is easy, has obtained important application in the fields such as laser plasma diagnosis and astrophysics in recent years.Country will
Digital diagnosis and treat equipment Research Emphasis special project is included in 13 and gives priority to, wherein phase contrast CT equipment use X-ray grating as
Core component captures object as emphasis.
To reduce absorption of the X-ray grating to X-ray, diffraction efficiency of grating is improved, needs prepared grating to have higher
Depth-to-width ratio.It is the unique effective way that can obtain high-aspect-ratio to improve etch rate ratio (etch rate ratio in length and breadth).At this stage,
Etch rate ratio only up to reach 1 in length and breadth：188, this ratio cannot still meet X-ray grating and further increase depth-to-width ratio
It is required that.The making meaning weight for realizing high-aspect-ratio X-ray is compared so seeking a kind of method and further increasing etch rate in length and breadth
Greatly.
Invention content
In view of this, an embodiment of the present invention provides a kind of grating lithographic method, X-ray grating can effectively improve in length and breadth
Etch rate ratio, the X-ray grating to producing high-aspect-ratio have direct important value.
The present invention provides a kind of grating lithographic method, the method includes：
Photoresist and front baking are coated after growing resist layer in monocrystal silicon substrate；
It is developed in the preparation that the monocrystal silicon substrate surface carries out sectored light resist mask figure using uv-exposure；
Using resist layer corrosive agent and monocrystalline process silicon etching solution by sectored light resist mask pattern transfer to monocrystal silicon substrate
On, correspond to the crystal orientation that etching phenomenon difference determines the monocrystal silicon substrate using different rectangular strips in fan-shaped mask graph；
After the crystal orientation for determining the monocrystal silicon substrate, formal grid photo-etching glue mask graph is carried out using uv-exposure development
Making；
The formal grid photo-etching glue mask graph is transferred on resist layer using resist layer corrosive agent and obtains resist layer
Mask graph simultaneously carries out photoresist removal to the resist layer mask graph；
The resist layer mask graph is transferred in monocrystal silicon substrate using monocrystalline process silicon etching solution, to the monocrystalline silicon substrate
Bottom carries out cleaning treatment.
Optionally, coating photoresist and the front baking after resist layer is grown in monocrystal silicon substrate, including：
The monocrystal silicon substrate prepared using zone-melting process, it is clear using No.1 standard cleaning liquid and No. two standard cleaning liquid to silicon chip
After washing the resist layer that a layer thickness is 80 nanometers is grown on monocrystal silicon substrate surface；
Use spin-coating method in the monocrystal silicon substrate surface coating thickness with resist layer for 600 nanometers of photoresist, rotation
Apply speed 3000rpm, spin-coating time 30s；
The silicon base for having been coated with photoresist is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature, front baking time
20mins。
Optionally, described to be developed in the monocrystal silicon substrate surface progress sectored light resist mask figure using uv-exposure
Preparation, including：
Fan-shaped mask plate figure is recorded in using Exposure mode on photoresist using ultraviolet exposure machine, utilizes 3 ‰
NaOH solution develops to photoresist, to realize prepared by sectored light resist mask.
Optionally, it is described using resist layer corrosive agent and monocrystalline process silicon etching solution by sectored light resist mask pattern transfer extremely
In monocrystal silicon substrate, corresponds to etching phenomenon difference using different rectangular strips in fan-shaped mask graph and determine the monocrystal silicon substrate
Crystal orientation, including：
Resist layer is performed etching using buffered hydrofluoric acid etching liquid after development, etch period 60s, 20 DEG C of etching temperature,
By sectored light resist mask pattern transfer to resist layer；
The micro- sem observation sectored light resist mask figure difference rectangular strip etching for being 1000 by using amplification factor is existing
As the different determining accurate directions of crystal orientation；
Rectangular strip and crystal orientation misalignment are determined when microscope sees that rectangular strip both sides black surround width is not equal；
The crystal orientation alignment of monocrystal silicon substrate is determined when rectangular strip both sides black surround is narrower and wide.
Optionally, after the crystal orientation of the determination monocrystal silicon substrate, formal grating light is carried out using uv-exposure development
The making of resist mask figure, including：
After the crystal orientation of the monocrystal silicon substrate determines, the monocrystal silicon substrate is cleaned, using spin-coating method with
The photoresist that the monocrystal silicon substrate surface coating thickness of resist layer is 600 nanometers, spin speed 3000rpm, spin-coating time 30s；
The monocrystal silicon substrate for having been coated with photoresist is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature, front baking time
20mins；
The crystal orientation of monocrystal silicon substrate is aligned using rectangular raster mask plate, the grating of the rectangular raster mask plate
Line orientations are parallel with alignment slot direction, by the fan-shaped rectangular strip of alignment slot and crystal orientation deviation minimum on rectangular raster mask plate
It is aligned, alignment precision is 0.01 °；
Formal grid photo-etching glue mask is completed after aligned by uv-exposure developing process to prepare.
Optionally, described that the formal grid photo-etching glue mask graph is transferred on resist layer using resist layer corrosive agent
It obtains resist layer mask graph and photoresist removal is carried out to the resist layer mask graph, including：
Resist layer is performed etching using buffered hydrofluoric acid etching liquid after development, etch period 60s, 20 DEG C of etching temperature,
Formal grid photo-etching glue mask graph is transferred to resist layer and obtains resist layer mask graph；
Photoresist is removed using acetone, removal process is aided with supersonic oscillations, frequency of oscillation 100kHz, hunting power
300W removes time 20mins, and after photoresist removal, resist layer 10mins is rinsed with deionized water.
Optionally, described that the resist layer mask graph is transferred in monocrystal silicon substrate using monocrystalline process silicon etching solution, it is right
The monocrystal silicon substrate carries out cleaning treatment, including：
Monocrystalline silicon wet etching performs etching to obtain using monocrystalline process silicon etching solution to the resist layer mask graph in monocrystal silicon substrate
Grating, 20 DEG C of etching temperature, wherein the monocrystalline process silicon etching solution proportioning is 50%KOH：20%IPA：5 ‰ TMDD=10：4：2,
The above ratio is volume ratio；
After etching, grating surface residue is cleaned with 98% concentrated sulfuric acid, and successively by the grating after wet etching
It is put into acetone and deionized water and is aided with cleaned by ultrasonic vibration 20mins respectively.
Optionally, resist layer is performed etching using buffered hydrofluoric acid etching liquid after the development, etch period 60s, is carved
20 DEG C of temperature is lost, before sectored light resist mask pattern transfer to resist layer, the method further includes：
It is dried after being carried out to sectored light resist mask figure, 120 DEG C of baking temperature, baking time 20mins.
Optionally, resist layer is performed etching using buffered hydrofluoric acid etching liquid after the development, etch period 60s, is carved
20 DEG C of temperature is lost, formal grid photo-etching glue mask graph is transferred to before resist layer obtains resist layer mask graph, the side
Method further includes：
Alignment type grid photo-etching glue mask graph dries after carrying out, 120 DEG C of baking temperature, baking time 20mins.
Optionally, the resist layer is silicon dioxide layer or silicon nitride layer.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages：
The grating lithographic method of the present invention grows coating photoresist and front baking after resist layer in monocrystal silicon substrate；It utilizes
Uv-exposure is developed in the preparation that monocrystal silicon substrate surface carries out sectored light resist mask figure；Using resist layer corrosive agent and
Monocrystalline process silicon etching solution utilizes different rectangles in fan-shaped mask graph by sectored light resist mask pattern transfer to monocrystal silicon substrate
Item corresponds to the crystal orientation that etching phenomenon difference determines monocrystal silicon substrate；It is aobvious using uv-exposure after the crystal orientation for determining monocrystal silicon substrate
Shadow carries out the making of formal grid photo-etching glue mask graph；Formal grid photo-etching glue mask graph is turned using resist layer corrosive agent
It moves on resist layer and obtains resist layer mask graph and photoresist removal is carried out to layer mask figure against corrosion；Utilize monocrystalline silicon etching
Resist layer mask graph is transferred in monocrystal silicon substrate by liquid, is carried out cleaning treatment to monocrystal silicon substrate, be can effectively improve light
Etch rate ratio, the grating to producing high-aspect-ratio have direct important value to grid in length and breadth.
Description of the drawings
Fig. 1 is the step flow chart of the grating lithographic method in the embodiment of the present invention；
Fig. 2 is the process flow chart of the grating lithographic method in the embodiment of the present invention；
Fig. 2 a are the crystal orientation in the grating lithographic method in the embodiment of the present invention to mutatis mutandis fan-shaped mask plate schematic diagram；
Fig. 2 b are the exposure area schematic diagram of the crystal orientation alignment in the grating lithographic method in the embodiment of the present invention；
Fig. 3 is formal grating mask plate and alignment schematic diagram in the grating lithographic method in the embodiment of the present invention；
Fig. 4 is the high etch rate in length and breadth in the grating lithographic method in the embodiment of the present invention than grating groove profile electron microscope
Sample.
Specific implementation mode
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model that the present invention protects
It encloses.
Term " first ", " second ", " third " " in description and claims of this specification and above-mentioned attached drawing
The (if present)s such as four " are for distinguishing similar object, without being used to describe specific sequence or precedence.It should manage
The data that solution uses in this way can be interchanged in the appropriate case, so that the embodiments described herein can be in addition to illustrating herein
Or the sequence other than the content of description is implemented.In addition, term " comprising " and " having " and their any deformation, it is intended that
Cover it is non-exclusive include, for example, containing the process of series of steps or unit, method, system, product or equipment need not limit
In those of clearly listing step or unit, but may include not listing clearly or for these processes, method, production
The intrinsic other steps of product or equipment or unit.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, the every other implementation that those skilled in the art are obtained without creative efforts
Example, shall fall within the protection scope of the present invention.
Explanation of nouns：
Zone-melting process is also known as Fz methods, i.e. floating zone method.Zone-melting process is to generate one in one end of semiconductor bar using thermal energy
Melting zone, then welding single crystal seed.Adjusting temperature makes melting zone slowly be moved to the other end of stick, by whole bar, grows into
A piece monocrystalline, crystal orientation are identical as seed crystal.Zone-melting process is divided into two kinds：Horizontal zone-melting technique and vertical suspending zone-melting process.The former is main
Purification and crystal growth for materials such as germanium, GaAs.The latter is mainly used for silicon, this is because the temperature of silicon melt is high, chemistry
Performance is active, is easy to be stained by foreign matter, it is difficult to find suitable boat, cannot use horizontal zone-melting technique.
In conjunction with shown in Fig. 1, the present invention provides a kind of grating lithographic method, the method includes：
S101, coating photoresist and front baking after resist layer are grown in monocrystal silicon substrate；
S102, it is developed in the system that the monocrystal silicon substrate surface carries out sectored light resist mask figure using uv-exposure
It is standby；
S103, using resist layer corrosive agent and monocrystalline process silicon etching solution by sectored light resist mask pattern transfer to monocrystalline silicon
In substrate, the crystal orientation that etching phenomenon difference determines the monocrystal silicon substrate is corresponded to using different rectangular strips in fan-shaped mask graph；
S104, it after determining the crystal orientation of the monocrystal silicon substrate, carries out formal grid photo-etching glue using uv-exposure development and covers
The making of mould figure；
S105, the formal grid photo-etching glue mask graph is transferred on resist layer using resist layer corrosive agent is resisted
It loses layer mask figure and photoresist removal is carried out to the resist layer mask graph；
S106, the resist layer mask graph is transferred in monocrystal silicon substrate using monocrystalline process silicon etching solution, to the list
Crystal silicon substrate carries out cleaning treatment.
Optionally, in S101, coating photoresist and the front baking after resist layer is grown in monocrystal silicon substrate, including：
The monocrystal silicon substrate prepared using zone-melting process, it is clear using No.1 standard cleaning liquid and No. two standard cleaning liquid to silicon chip
After washing the resist layer that a layer thickness is 80 nanometers is grown on monocrystal silicon substrate surface；
Use spin-coating method in the monocrystal silicon substrate surface coating thickness with resist layer for 600 nanometers of photoresist, rotation
Apply speed 3000rpm (revolution per second), spin-coating time 30s (second, second)；
The silicon base for having been coated with photoresist is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature, front baking time
20mins (minute, minutes).
Optionally, described to be developed in the fan-shaped photoetching of monocrystal silicon substrate surface progress using uv-exposure in S102
The preparation of glue mask graph, including：
Fan-shaped mask plate figure is recorded in using Exposure mode on photoresist using ultraviolet exposure machine, utilizes 3 ‰ hydrogen
Sodium oxide molybdena NaOH solution develops to photoresist, to realize prepared by sectored light resist mask.
Optionally, described to utilize resist layer corrosive agent and monocrystalline process silicon etching solution by sectored light resist mask in S103
In pattern transfer to monocrystal silicon substrate, corresponds to etching phenomenon difference using different rectangular strips in fan-shaped mask graph and determine the list
The crystal orientation of crystal silicon substrate, including：
Resist layer is performed etching using buffered hydrofluoric acid etching liquid after development, etch period 60s, 20 DEG C of etching temperature,
By sectored light resist mask pattern transfer to resist layer；
The micro- sem observation sectored light resist mask figure difference rectangular strip etching for being 1000 by using amplification factor is existing
As the different determining accurate directions of crystal orientation；
Rectangular strip and crystal orientation misalignment are determined when microscope sees that rectangular strip both sides black surround width is not equal；
The crystal orientation alignment of monocrystal silicon substrate is determined when rectangular strip both sides black surround is narrower and wide.
Optionally, resist layer is performed etching using buffered hydrofluoric acid etching liquid after the development, etch period 60s, is carved
20 DEG C of temperature is lost, before sectored light resist mask pattern transfer to resist layer, the method further includes：
It is dried after being carried out to sectored light resist mask figure, 120 DEG C of baking temperature, baking time 20mins.
Optionally, it in S104, after the crystal orientation of the determination monocrystal silicon substrate, is carried out just using uv-exposure development
The making of formula grid photo-etching glue mask graph, including：
After the crystal orientation of the monocrystal silicon substrate determines, the monocrystal silicon substrate is cleaned, using spin-coating method with
The photoresist that the monocrystal silicon substrate surface coating thickness of resist layer is 600 nanometers, spin speed 3000rpm, spin-coating time 30s；
The monocrystal silicon substrate for having been coated with photoresist is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature, front baking time
20mins；
The crystal orientation of monocrystal silicon substrate is aligned using rectangular raster mask plate, the grating of the rectangular raster mask plate
Line orientations are parallel with alignment slot direction, by the fan-shaped rectangular strip of alignment slot and crystal orientation deviation minimum on rectangular raster mask plate
It is aligned, alignment precision is 0.01 °；
Formal grid photo-etching glue mask is completed after aligned by uv-exposure developing process to prepare.
Optionally, described to be shifted the formal grid photo-etching glue mask graph using resist layer corrosive agent in S105
Resist layer mask graph is obtained on to resist layer and photoresist removal is carried out to the resist layer mask graph, including：
Resist layer is performed etching using buffered hydrofluoric acid etching liquid after development, etch period 60s, 20 DEG C of etching temperature,
Formal grid photo-etching glue mask graph is transferred to resist layer and obtains resist layer mask graph；
Photoresist is removed using acetone, removal process is aided with supersonic oscillations, frequency of oscillation 100kHz (kHz), oscillation
Power 300W removes time 20mins, and after photoresist removal, resist layer 10mins is rinsed with deionized water.
Optionally, resist layer is performed etching using buffered hydrofluoric acid etching liquid after the development, etch period 60s, is carved
20 DEG C of temperature is lost, formal grid photo-etching glue mask graph is transferred to before resist layer obtains resist layer mask graph, the side
Method further includes：
Alignment type grid photo-etching glue mask graph dries after carrying out, 120 DEG C of baking temperature, baking time 20mins.
Optionally, described that the resist layer mask graph is transferred to monocrystalline silicon using monocrystalline process silicon etching solution in S106
In substrate, cleaning treatment is carried out to the monocrystal silicon substrate, including：
Monocrystalline silicon wet etching performs etching to obtain using monocrystalline process silicon etching solution to the resist layer mask graph in monocrystal silicon substrate
Grating, 20 DEG C of etching temperature, wherein the monocrystalline process silicon etching solution proportioning is 50%KOH：20%IPA：5 ‰ TMDD=10：4：2,
The above ratio is volume ratio.
After etching, grating surface residue is cleaned with 98% concentrated sulfuric acid, and successively by the grating after wet etching
It is put into acetone and deionized water and is aided with cleaned by ultrasonic vibration 20mins respectively.
Optionally, the resist layer is silicon dioxide layer or silicon nitride layer, can be specifically, the SiO2 of thermal oxidation method growth
Layer or the Si3N4 layers of Low Pressure Chemical Vapor Deposition growth, those of ordinary skill in the art are not it is to be appreciated that go to live in the household of one's in-laws on getting married herein
It states.
A kind of embodiment is additionally provided in conjunction with shown in Fig. 2,2a and 2b, in the embodiment of the present invention, is with resist layer below
It is illustrated for SiO2 layers, can specifically include following steps：
S201, base treatment：The monocrystal silicon substrate piece prepared using zone-melting process is clear using SC1+SC2 cleaning solutions to silicon chip
The resist layer of 80 nanometers of a layer thickness is grown after washing on its surface.Resist layer used in this experiment is the SiO2 of thermal oxidation method growth
Layer, selects different resist layers process route can be caused to be slightly different, but do not influence actual effect caused by this method.
S202, spin coating：Photoresist is coated in the silicon substrate surface with resist layer using spin-coating method, photoresist uses BP-
212-7S positive-tone photo virgin rubbers, spin speed 3000rpm, spin-coating time 30s are thick by the photoresist after step instrument test coating
Degree, photoresist thickness 600nm.The silicon base for having been coated with photoresist is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature is preceding
Dry time 20mins.
It is prepared by S203, fan-shaped mask：Figure on fan-shaped mask plate as shown in Figure 2 a is utilized into exposure using ultraviolet exposure machine
Mode is recorded on photoresist, and exposure area is as shown in Figure 2 b, is developed to photoresist using 3 ‰ NaOH solution, is realized
It is prepared by sectored light resist mask.
S204, resist layer pattern transfer：Buffered hydrofluoric acid (49%HF is utilized after development:40%NH3F=1:8) to SiO2
Layer performs etching, and photoresist mask graph is transferred to SiO2 layers by etch period 60s, 20 DEG C of etching temperature.Buffered hydrofluoric acid,
The etching liquid mixed by acidic oxide and ammonium fluoride, because HF acid contained by buffered hydrofluoric acid to post-develop photoresist inside
Contained humidity has extremely strong absorption, so needing to dry after carrying out photoresist mask before etching, 120 DEG C of baking temperature, baking time
20mins, to avoid photoresist mask in etching process from causing resist layer pattern transfer to fail by HF acid corrosions.
S205, monocrystalline silicon wet etching：Monocrystal silicon substrate is performed etching using 50% potassium hydroxide KOH etching liquids, etching temperature
20 DEG C of degree, etch period 16 hours, by SiO2 layer masks pattern transfer to monocrystal silicon substrate.
S206, crystal orientation alignment：Fan-shaped mask difference rectangular strip is observed by using high-power microscope (Max=1000*) to carve
Erosion phenomenon difference determines the accurate direction of crystal orientation.When rectangular strip is with crystal orientation misalignment, rectangular strip both sides can be seen by microscope
Black surround width differs, and when rectangular strip direction is closer to crystal orientation, rectangular strip both sides black surround is narrower and wide.It is by this principle
Crystal orientation can be determined by microscope, realize crystal orientation alignment.
S207, spin coating：After crystal orientation determines, monocrystal silicon substrate is cleaned, then uses spin-coating method with resist layer
Monocrystal silicon substrate surface coat photoresist, photoresist use BP-212-7S positive-tone photo virgin rubbers, spin speed 3000rpm, rotation
Time 30s is applied, the photoresist thickness after step instrument test coating, photoresist thickness 600nm are passed through.The list of photoresist will be had been coated with
Crystal silicon substrate is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature, front baking time 20mins.
It is prepared by S208, photoresist mask：Photoresist mask needs advanced line raster lines and crystal orientation Alignment Process before preparing.Profit
It is aligned with grating mask plate as shown in Figure 3, grating lines direction and alignment slot direction are strictly parallel.By pair on mask plate
Quasi- slot and the fan-shaped rectangular strip of crystal orientation deviation minimum are aligned using the aligning guide that ultraviolet exposure machine carries, alignment precision
0.01°.After alignment, realize prepared by photoresist mask by uv-exposure developing process.
S209, resist layer pattern transfer：Buffered hydrofluoric acid (49%HF is utilized after development:40%NH3F=1:8) to SiO2
Layer performs etching, and photoresist mask graph is transferred to SiO2 layers by etch period 60s, 20 DEG C of etching temperature.Because of buffered hydrofluoric acid
In contained HF acid have extremely strong absorption to contained humidity inside post-develop photoresist, so being needed before etching after being carried out to photoresist mask
It dries, 120 DEG C, baking time 20mins of baking temperature, to avoid photoresist mask in etching process from being caused to resist by HF acid corrosions
Lose layer pattern transfer failure.
S210, the removal of photoresist mask：Photoresist is removed using acetone, removal process is aided with supersonic oscillations, oscillation frequency
Rate 100kHz, hunting power 300W remove time 20mins.After photoresist removal, 10mins is rinsed with deionized water.
S211, monocrystalline silicon wet etching：To further increase etch rate ratio in length and breadth, etching liquid proportioning is optimized, is tested
Etching liquid proportioning used is 50%KOH：20%IPA：5 ‰ TMDD=10：4：2, the above ratio is volume ratio.After optimization
Etching liquid performs etching silicon chip, 20 DEG C of etching temperature, and etch period can change according to the specific flute profile depth requirements of grating.
The implementation case etch period is 17 hours, 16 μm of groove depth.It is carved in length and breadth by that can be obtained to grating progress Electronic Speculum test
It is 1 to lose speed ratio:300, test chart is as shown in figure 4, from test result it is found that institute's extracting method can effectively improve X-ray grating
The ratio of etch rate in length and breadth.
S212, cleaning treatment：After etching, grating surface residue is cleaned with 98% concentrated sulfuric acid, and wet method is carved
Grating after erosion is sequentially placed into acetone and deionized water is aided with cleaned by ultrasonic vibration 20mins respectively.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of division of logic function, formula that in actual implementation, there may be another division manner, such as multiple units or component
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be the indirect coupling by some interfaces, device or unit
It closes or communicates to connect, can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it can also
It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.Above-mentioned integrated list
The form that hardware had both may be used in member is realized, can also be realized in the form of SFU software functional unit.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can
It is completed with instructing relevant hardware by program, which can be stored in a computer readable storage medium, storage
Medium may include：Read-only memory (ROM, Read Only Memory), random access memory (RAM, Random
Access Memory), disk or CD etc..
One of ordinary skill in the art will appreciate that implement the method for the above embodiments be can be with
Relevant hardware is instructed to complete by program, the program can be stored in a kind of computer readable storage medium, on
It can be read-only memory, disk or CD etc. to state the storage medium mentioned.
A kind of grating lithographic method provided by the present invention is described in detail above, for the general skill of this field
Art personnel, the thought of embodiment according to the present invention, there will be changes in the specific implementation manner and application range, to sum up institute
It states, the content of the present specification should not be construed as limiting the invention.
Claims (10)
1. a kind of grating lithographic method, which is characterized in that the method includes：
Photoresist and front baking are coated after growing resist layer in monocrystal silicon substrate；
It is developed in the preparation that the monocrystal silicon substrate surface carries out sectored light resist mask figure using uv-exposure；
Using resist layer corrosive agent and monocrystalline process silicon etching solution by sectored light resist mask pattern transfer to monocrystal silicon substrate, profit
The crystal orientation that etching phenomenon difference determines the monocrystal silicon substrate is corresponded to different rectangular strips in fan-shaped mask graph；
After the crystal orientation for determining the monocrystal silicon substrate, the system of formal grid photo-etching glue mask graph is carried out using uv-exposure development
Make；
The formal grid photo-etching glue mask graph is transferred on resist layer using resist layer corrosive agent and obtains layer mask against corrosion
Figure simultaneously carries out photoresist removal to the resist layer mask graph；
The resist layer mask graph is transferred in monocrystal silicon substrate using monocrystalline process silicon etching solution, to the monocrystal silicon substrate into
Row cleaning treatment.
2. grating lithographic method according to claim 1, which is characterized in that described to grow resist layer in monocrystal silicon substrate
Coating photoresist and front baking afterwards, including：
The monocrystal silicon substrate prepared using zone-melting process, after being cleaned using No.1 standard cleaning liquid and No. two standard cleaning liquid to silicon chip
The resist layer that a layer thickness is 80 nanometers is grown on monocrystal silicon substrate surface；
Use spin-coating method in the monocrystal silicon substrate surface coating thickness with resist layer for 600 nanometers of photoresist, spin coating speed
Spend 3000rpm, spin-coating time 30s；
The silicon base for having been coated with photoresist is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature, front baking time 20mins.
3. grating lithographic method according to claim 1, which is characterized in that described to be developed in the list using uv-exposure
Crystal silicon substrate surface carries out the preparation of sectored light resist mask figure, including：
Fan-shaped mask plate figure is recorded in using Exposure mode on photoresist using ultraviolet exposure machine, it is molten using 3 ‰ NaOH
Liquid develops to photoresist, to realize prepared by sectored light resist mask.
4. grating lithographic method according to claim 1, which is characterized in that described to utilize resist layer corrosive agent and monocrystalline
Process silicon etching solution utilizes different rectangular strips pair in fan-shaped mask graph by sectored light resist mask pattern transfer to monocrystal silicon substrate
The crystal orientation that phenomenon difference determines the monocrystal silicon substrate should be etched, including：
Resist layer is performed etching using buffered hydrofluoric acid etching liquid after development, etch period 60s, 20 DEG C of etching temperature will be fanned
Shape photoresist mask graph is transferred to resist layer；
The micro- sem observation sectored light resist mask figure difference rectangular strip for being 1000 by using amplification factor etches phenomenon not
With the accurate direction of determining crystal orientation；
Rectangular strip and crystal orientation misalignment are determined when microscope sees that rectangular strip both sides black surround width is not equal；
The crystal orientation alignment of monocrystal silicon substrate is determined when rectangular strip both sides black surround is narrower and wide.
5. grating lithographic method according to claim 1, which is characterized in that the crystal orientation of the determination monocrystal silicon substrate
Afterwards, the making of formal grid photo-etching glue mask graph is carried out using uv-exposure development, including：
After the crystal orientation of the monocrystal silicon substrate determines, the monocrystal silicon substrate is cleaned, using spin-coating method with against corrosion
The photoresist that the monocrystal silicon substrate surface coating thickness of layer is 600 nanometers, spin speed 3000rpm, spin-coating time 30s；
The monocrystal silicon substrate for having been coated with photoresist is put into baking oven and carries out front baking processing, 90 DEG C of oven temperature, front baking time
20mins；
The crystal orientation of monocrystal silicon substrate is aligned using rectangular raster mask plate, the grating lines of the rectangular raster mask plate
Direction is parallel with alignment slot direction, and the fan-shaped rectangular strip of alignment slot and crystal orientation deviation minimum on rectangular raster mask plate is carried out
Alignment, alignment precision are 0.01 °；
Formal grid photo-etching glue mask is completed after aligned by uv-exposure developing process to prepare.
6. grating lithographic method according to claim 1, which is characterized in that it is described using resist layer corrosive agent by it is described just
Formula grid photo-etching glue mask graph be transferred on resist layer obtain resist layer mask graph and to the resist layer mask graph into
Row photoresist removes, including：
Resist layer is performed etching using buffered hydrofluoric acid etching liquid after development, etch period 60s, 20 DEG C of etching temperature will just
Formula grid photo-etching glue mask graph is transferred to resist layer and obtains resist layer mask graph；
Photoresist is removed using acetone, removal process is aided with supersonic oscillations, frequency of oscillation 100kHz, and hunting power 300W is gone
Except time 20mins, after photoresist removal, resist layer 10mins is rinsed with deionized water.
7. grating lithographic method according to claim 1, which is characterized in that described described to be resisted using monocrystalline process silicon etching solution
It loses in layer mask pattern transfer to monocrystal silicon substrate, cleaning treatment is carried out to the monocrystal silicon substrate, including：
Monocrystalline silicon wet etching performs etching to obtain light using monocrystalline process silicon etching solution to the resist layer mask graph in monocrystal silicon substrate
Grid, 20 DEG C of etching temperature, wherein the monocrystalline process silicon etching solution proportioning is 50%KOH：20%IPA：5 ‰ TMDD=10：4：2, with
Upper ratio is volume ratio；
After etching, grating surface residue is cleaned with 98% concentrated sulfuric acid, and the grating after wet etching is sequentially placed into
It is aided with cleaned by ultrasonic vibration 20mins in acetone and deionized water respectively.
8. grating lithographic method according to claim 4, which is characterized in that etched using buffered hydrofluoric acid after the development
Liquid performs etching resist layer, etch period 60s, 20 DEG C of etching temperature, by sectored light resist mask pattern transfer to resist layer
Before, the method further includes：
It is dried after being carried out to sectored light resist mask figure, 120 DEG C of baking temperature, baking time 20mins.
9. according to the method described in claim 6, it is characterized in that, using buffered hydrofluoric acid etching liquid to against corrosion after the development
Layer performs etching, and formal grid photo-etching glue mask graph is transferred to resist layer and obtained by etch period 60s, 20 DEG C of etching temperature
Before resist layer mask graph, the method further includes：
Alignment type grid photo-etching glue mask graph dries after carrying out, 120 DEG C of baking temperature, baking time 20mins.
10. method according to any one of claim 1 to 9, which is characterized in that the resist layer be silicon dioxide layer or
Silicon nitride layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109782382A (en) * | 2018-12-25 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | The preparation method of high opening area critical angle transmission grating |
| CN110082847A (en) * | 2019-04-29 | 2019-08-02 | 重庆大学 | A kind of preparation method of silicon substrate MEMS balzed grating, |
| CN113496946A (en) * | 2021-06-15 | 2021-10-12 | 南方科技大学 | Preparation method of monolithic interlayer through hole |
-
2017
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109782382A (en) * | 2018-12-25 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | The preparation method of high opening area critical angle transmission grating |
| CN110082847A (en) * | 2019-04-29 | 2019-08-02 | 重庆大学 | A kind of preparation method of silicon substrate MEMS balzed grating, |
| CN113496946A (en) * | 2021-06-15 | 2021-10-12 | 南方科技大学 | Preparation method of monolithic interlayer through hole |
| CN113496946B (en) * | 2021-06-15 | 2024-04-19 | 南方科技大学 | Preparation method of single-chip interlayer through hole |
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