CN108694900B

CN108694900B - Source electrode driving circuit, driving system and method for driving panel and display device thereof

Info

Publication number: CN108694900B
Application number: CN201711402383.5A
Authority: CN
Inventors: 张书玮; 余家齐; 许郭任
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2017-04-05
Filing date: 2017-12-22
Publication date: 2022-02-22
Anticipated expiration: 2037-12-22
Also published as: CN108694900A

Abstract

The invention discloses a source driving circuit, a driving system and a method for driving a display panel and a display device thereof. The source driving circuit comprises a plurality of output channels and a plurality of shift registers respectively corresponding to the output channels. The shift registers are divided into a plurality of shift register sequences, wherein a first shift register sequence comprises a first shift register and a second shift register which are respectively used as two end points of the first shift register sequence, and a second shift register sequence comprises a third shift register and a fourth shift register which are respectively used as two end points of the second shift register sequence; the first to fourth shift registers are connected to a timing controller, the first shift register is used for receiving a first start pulse transmitted by the timing controller, and the third shift register is used for receiving a second start pulse transmitted by the timing controller.

Description

Source electrode driving circuit, driving system and method for driving panel and display device thereof

Technical Field

The present invention relates to a driving system and method for a display panel, and more particularly, to a source driving circuit, a driving system and method for driving a display panel, and a display device using the same.

Background

Conventionally, a Display device such as a Liquid Crystal Display (LCD) includes a Display panel driven by a gate driving circuit and a source driving circuit. The timing controller is coupled to the gate driving circuit and the source driving circuit, and generates a gate control signal (also called a scan signal) to control a timing at which the data voltage signal is output from the source driving circuit to the display panel. The timing controller, the source driving circuit and the gate driving circuit may be implemented in a single or respective semiconductor chip.

Generally, a source driving circuit is required to have a function of driving various display panels with different resolutions, the display panels can be located on different devices such as tablet computers, mobile phones or car navigators, and the horizontal resolution of the display panel does not exceed the maximum resolution supported by the source driving circuit. For example, the source driving circuit has 1280 data voltage output channels (hereinafter, referred to as output channels for short, which may be regarded as output ports of the semiconductor chip integrating the source driving circuit), but the horizontal resolution of the display panel may be 960 pixels. In one case, each output channel can select three data lines on the display panel (e.g., through a data selector), and 320 additional output channels (i.e., 1280 and 960) in the source driver circuit are not coupled to the data lines on the display panel, which means that the 320 output channels are set as dummy channels.

Since a source driver circuit should be adjusted according to different horizontal resolutions of a display panel, various methods for adjusting the number of dummy channels are proposed. In one conventional method, additional connection lines are provided between different shift registers of the source driver circuit, so that the start pulse can skip several shift registers, and thus, the output channels corresponding to the skipped shift registers can be set as dummy channels.

Referring to fig. 1, fig. 1 is a schematic diagram of a conventional display device 10. The display device 10 includes a display panel 100 and a driving system 110 for driving the display panel 100. The display panel 100 includes a plurality of pixel units. The driving system 110 includes a timing controller 112 and a source driving circuit 114. The source driving circuit 114 includes: a Shift Register circuit having a plurality of Shift registers (Shift registers), a latch circuit, a Level Shift circuit (Level Shifter), a Digital-to-Analog Converter (DAC), an output buffer circuit for generating data voltage signals, and a plurality of output channels. The output channels are coupled to an output buffer circuit, which is used to output data voltage signals to data lines (not shown) on the display panel 100 to drive the pixel units. The output channels can be regarded as output ports of the semiconductor chips of the driving system 110, and the (valid) output channels are coupled to the data lines on the display panel 100 in a one-to-one or one-to-many manner. The timing controller 112 may transmit a start pulse to the shift register circuit, and the start pulse may be sequentially shifted in the shift register circuit according to a clock signal (not shown in fig. 1). The shift register may enable a corresponding latch unit to sample pixel data on a corresponding output channel. In fig. 1, a connection line W1 is connected between two non-adjacent shift registers, so that the start pulse can skip several shift registers, and the output channels corresponding to the skipped shift registers are set as dummy channels, which are not coupled to the data lines on the display panel 100.

Fig. 2A is a schematic diagram of a driving system 20, and fig. 2A shows a clear example of the connection line W1 in fig. 1. FIG. 2A shows only a portion of the driving system 20, which includes a timing controller 212 and shift registers SR01 SR16 connected in series. The connection line W1 is connected between two non-adjacent shift registers SR04 and SR13, such that a start pulse SP bypasses the shift registers SR 05-SR 12, and the output channels corresponding to the shift registers SR 05-SR 12 are set as dummy channels.

Fig. 2B and 2C show the same circuit and dummy channel settings as in fig. 2A, and indicate start pulses SP for different transmission directions. In fig. 2B, the timing controller 212 transmits the start pulse SP to the shift register SR01, the start pulse SP is sequentially shifted, and after the start pulse SP is shifted to the shift register SR04, the start pulse SP is then shifted to the shift register SR13 through the connection line W1 (as a bypass path). In fig. 2C, the timing controller 212 transmits the start pulse SP to the shift register SR16, the start pulse SP is sequentially shifted, and after the start pulse SP is shifted to the shift register SR13, the start pulse SP is then shifted to the shift register SR04 through the connection line W1. In the case of using the connection line W1, a source driving circuit having 16 output channels can be used to drive a display panel having a horizontal resolution of 8 pixels.

In order to support different display panels with different horizontal resolutions, the source driving circuit of the conventional driving system includes a plurality of connection lines (the connection lines W1 shown in fig. 1 and fig. 2A-2C) for skipping different numbers of shift registers to set different numbers of dummy channels. For example, if two additional connecting lines are used, the source driver circuit with 1280 output channels can support the horizontal resolution of 720 pixels and 960 pixels, i.e., one additional connecting line can skip 320 shift registers to set 320 (i.e., 1280-960) dummy channels, and another additional connecting line can skip 560 shift registers to set 560 (i.e., 1280-720) dummy channels, and these additional connecting lines occupy a large circuit layout area and reduce the layout flexibility. Therefore, it is necessary to provide a more efficient method and source driving circuit suitable for various horizontal resolutions, and further suitable for various types of display panels.

Disclosure of Invention

Therefore, it is a primary objective of the claimed invention to provide a driving system and method for driving a display panel and a display device thereof, so as to solve the above-mentioned problems.

The invention discloses a source driving circuit for driving a display panel, which comprises a plurality of output channels and a plurality of shift registers. The plurality of shift registers respectively correspond to the plurality of output channels, wherein the plurality of shift registers are divided into a plurality of shift register sequences, a first shift register sequence in the plurality of shift register sequences comprises a first shift register and a second shift register, the first shift register is one end point of the first shift register sequence, the second shift register is the other end point of the first shift register sequence, a second shift register sequence in the plurality of shift register sequences comprises a third shift register and a fourth shift register, the third shift register is one end point of the second shift register sequence, and the fourth shift register is the other end point of the second shift register sequence. The first shift register, the second shift register, the third shift register and the fourth shift register are connected to a timing controller, the first shift register is used for receiving a first start pulse transmitted by the timing controller, and the third shift register is used for receiving a second start pulse transmitted by the timing controller.

The invention also discloses a driving system for driving the display panel, which comprises a time schedule controller and a source electrode driving circuit. The timing controller can be used for generating a first start pulse and a second start pulse. The source driving circuit comprises a plurality of output channels and a plurality of shift registers, wherein the shift registers respectively correspond to the output channels. The shift registers are divided into a plurality of shift register sequences, a first shift register sequence in the shift register sequences comprises a first shift register and a second shift register, the first shift register is one end point of the first shift register sequence, the second shift register is the other end point of the first shift register sequence, a second shift register sequence in the shift register sequences comprises a third shift register and a fourth shift register, the third shift register is one end point of the second shift register sequence, and the fourth shift register is the other end point of the second shift register sequence; the timing controller is connected to the first shift register, the second shift register, the third shift register and the fourth shift register, and is used for transmitting the first start pulse to the first shift register and transmitting the second start pulse to the third shift register.

The invention also discloses a display device, which comprises a display panel, a time sequence controller and a source electrode driving circuit. The timing controller can be used for generating a first start pulse and a second start pulse. The source driving circuit can be used for driving the display panel and comprises a plurality of output channels and a plurality of shift registers, wherein the shift registers respectively correspond to the output channels. The shift registers are divided into a plurality of shift register sequences, a first shift register sequence in the shift register sequences comprises a first shift register and a second shift register, the first shift register is one end point of the first shift register sequence, the second shift register is the other end point of the first shift register sequence, a second shift register sequence in the shift register sequences comprises a third shift register and a fourth shift register, the third shift register is one end point of the second shift register sequence, and the fourth shift register is the other end point of the second shift register sequence; the timing controller is connected to the first shift register, the second shift register, the third shift register and the fourth shift register, and is used for transmitting the first start pulse to the first shift register and transmitting the second start pulse to the third shift register.

The invention also discloses a method for driving the display panel, which is used for a driving system comprising a time sequence controller and a source electrode driving circuit. The method comprises the following steps: the time schedule controller transmits a first starting pulse to one end point of a first shift register sequence of the source electrode driving circuit; and the time schedule controller transmits a second starting pulse to one end point of a second shift register sequence of the source electrode driving circuit before the first starting pulse is shifted to a target shift register in the first shift register sequence.

Drawings

Fig. 1 is a schematic diagram of a conventional display device.

Fig. 2A-2C are schematic diagrams of an exemplary driving system having 16 shift registers, where 16 shift registers correspond to 16 output channels of a source driving circuit.

Fig. 3 is a schematic diagram of a driving system according to an embodiment of the invention.

Fig. 4A and 4B are schematic views of the driving system of fig. 3.

Fig. 4C and 4D are schematic diagrams of the driving system of fig. 3 with dummy channels.

Fig. 4E is a waveform diagram of the start pulse in fig. 4A.

Fig. 5A and 5B are schematic views of the driving system of fig. 3.

Fig. 5C and 5D are schematic diagrams of the driving system of fig. 3 with dummy channels.

Fig. 5E is a waveform diagram of the start pulse in fig. 5C.

FIGS. 6A-6E are diagrams illustrating a method for transmitting a start pulse to a shift register in a display device according to an embodiment of the invention.

Fig. 7A to 7C are schematic views of a driving system according to an embodiment of the invention.

Fig. 8A is a schematic diagram of the driving system of fig. 7A for a display device with a horizontal resolution of 4 pixels.

Fig. 8B is a waveform diagram illustrating a waveform of a start pulse of the source driver circuit in fig. 8A.

FIG. 9 is a flow chart of an embodiment of the present invention.

Wherein the reference numerals are as follows:

10. 60 display device

100. 600 display panel

110. 20, 30, 70 drive system

112. 212, 312, 712 time schedule controller

W1 connecting line

SR 01-SR 16 shift register

SP Start pulse

P1 first Start pulse

P2 second Start pulse

114. 610 source electrode driving circuit

SW1, SW2, SW3 and SW4 switches

90 flow path

900 to 906 steps

Detailed Description

Referring to fig. 3, fig. 3 is a schematic diagram of a driving system 30 according to an embodiment of the invention. Fig. 3 shows a part of the circuit of the driving system 30, including a timing controller 312 and a Shift Register (Shift Register) circuit of a source driving circuit. The source driving circuit of the driving system 30 further includes a latch circuit, a Level Shifter (Level Shifter), a Digital-to-Analog Converter (DAC), an output buffer circuit, and a plurality of output channels, which can refer to the structure of fig. 1 and are omitted from fig. 3. It is noted that the output channel can be regarded as an output port of the semiconductor chip of the integrated source driving circuit or driving system 30, and the output channel described in this specification is a data voltage output channel. For convenience of illustration, the shift register circuit of FIG. 3 includes only 16 shift registers SR01 SR16 corresponding to 16 output channels as an example, but those skilled in the art will appreciate that a typical source driver circuit may include hundreds or thousands of shift registers and their corresponding output channels.

The shift registers SR01 SR16 can be divided into two shift register sequences, a first shift register sequence and a second shift register sequence, wherein each shift register sequence has a plurality of sequentially connected shift registers. The first shift register sequence may be disposed at one side of the timing controller 312, and the second shift register sequence may be disposed at the other side of the timing controller 312. The timing controller 312 can transmit two start pulses (i.e. a first start pulse P1 and a second start pulse P2, as shown in fig. 4A and 4B) to the corresponding shift register sequences at different time points or at the same time point. In one embodiment of the present invention, the second start pulse P2 is transmitted later than the first start pulse P1. As shown in fig. 3, a connection line between the timing controller 312 and the shift registers (SR01, SR08, SR09, and SR16) can be used as a medium for the timing controller 312 to transmit the first start pulse P1 and the second start pulse P2. For the source driving circuit, the timing controller 312 also transmits a clock signal (not shown) to each of the shift registers SR01 SR 16. According to the clock signal, the first start pulse P1 or the second start pulse P2 is shifted from one shift register to an adjacent (next) shift register during a period (e.g., one clock cycle).

Referring to fig. 4A and 4B, fig. 4A and 4B show the same circuit as fig. 3, with different transmission direction indications of the first start pulse P1 and the second start pulse P2 added. In one embodiment, the display panel employs a one-out-of-three data selector to couple one output channel to one of the corresponding data lines, so that all 16 output channels in the source driving circuit of the driving system 30 are used to drive the display panel with a horizontal resolution of 16 pixels.

Fig. 4A shows a start pulse transmitted from left to right. In FIG. 4A, the shift registers SR01 SR08 can be regarded as the first shift register sequence and the shift registers SR09 SR16 can be regarded as the second shift register sequence. In the first shift register series, the shift register SR01 is located at one end of the first shift register series and the shift register SR08 is located at the other end of the first shift register series. The timing controller 312 is connected to the shift register SR01 and to the shift register SR 08. In the second shift register series, the shift register SR09 is located at one end of the second shift register series and the shift register SR16 is located at the other end of the second shift register series. The timing controller 312 is connected to the shift register SR09 and to the shift register SR 16. As shown in fig. 4A, the timing controller 312 can transmit a first start pulse P1 to the shift register SR01 in the first shift register sequence, and after the first start pulse P1 is shifted to the shift register SR08 in the first shift register sequence, the timing controller 312 can transmit a second start pulse P2 to the shift register SR09 in the second shift register sequence, and the second start pulse P2 is sequentially shifted to the last shift register SR 16.

Fig. 4B shows the start pulse transmitted from right to left. In FIG. 4B, the shift registers SR16 SR09 can be regarded as the first shift register sequence and the shift registers SR08 SR01 can be regarded as the second shift register sequence. As shown in FIG. 4B, the timing controller 312 can transmit a first start pulse P1 to the shift register SR16, and after the first start pulse P1 is shifted to the shift register SR09, the timing controller 312 can transmit a second start pulse P2 to the shift register SR08, and the second start pulse P2 is sequentially shifted to the last shift register SR 01.

Unlike the source driver circuits shown in fig. 2A-2C in which 16 shift registers are connected in sequence (where SR08 is connected to SR09) and only a single start pulse is transmitted, the two shift register sequences of the source driver circuit shown in fig. 3 are not directly connected, and the timing controller 312 transmits two start pulses (P1 and P2) to the corresponding shift register sequences respectively. That is, in the embodiment of FIG. 3, there is no physical wire connection between a terminal of the first shift register sequence (e.g., SR08 or SR09) and a terminal of the second shift register sequence (e.g., SR09 or SR08) that can shift the start pulse.

When the driving system 30 is used to drive a display panel with a horizontal resolution of 16 pixels, the one-out-of-three data selector can be selectively coupled to the data lines, and the number of output channels (i.e. 16 output channels) of the source driving circuit in the driving system 30 is equal to the horizontal resolution of the display panel.

The drive system 30 including the circuit in fig. 3 may also support different display panels with different resolutions. In the case that the total number of output channels (i.e., data voltage output channels) in the driving system 30 is greater than the number of output channels required to drive the display panel, some of the output channels not coupled to the data lines on the display panel may be set as dummy output channels (hereinafter, referred to as dummy channels). In one embodiment, a portion of the first shift register sequence and a portion of the second shift register sequence correspond to dummy channels. The number of dummy channels of the shift registers corresponding to the partial sequence in the first shift register sequence may be the same or different from the number of dummy channels of the shift registers corresponding to the partial sequence in the second shift register sequence. Those skilled in the art will appreciate that the placement of the dummy channels should not be a limitation of the present invention.

Taking the transmission direction of the start pulse in fig. 4A as an example, if the source driver circuit has a dummy channel, the timing controller 312 may transmit the second start pulse P2 to the shift register SR09 before the first start pulse P1 is shifted to the shift register SR08 to skip the dummy channel. More specifically, the second start pulse P2 is transmitted to the shift register SR09 when the first start pulse P1 is shifted to a target shift register in the first shift register series, which can be any one of the shift registers SR01 SR08 in the first shift register series.

Referring to fig. 4C and 4D, fig. 4C and 4D show the same shift register circuit as fig. 3, with different transmission direction indications of the first start pulse P1 and the second start pulse P2 added. In the embodiment of fig. 4C and 4D, the four output channels corresponding to the four shift registers SR07, SR08, SR09 and SR10 are set as dummy channels, so that the remaining effective output channels include 12 output channels, which is sufficient to drive a display panel with a horizontal resolution of 12 pixels (if a one-out-of-three data selector is used). In fig. 4C and 4D, the shift registers marked with oblique lines represent the shift registers corresponding to the dummy channels.

Fig. 4C shows the start pulse transmitted from left to right. In FIG. 4C, the shift registers SR01 SR08 can be regarded as the first shift register sequence and the shift registers SR09 SR16 can be regarded as the second shift register sequence. Please refer to FIG. 4E, which is a waveform diagram illustrating the waveforms of the firing pulses P1 and P2 transmitted in the direction shown in FIG. 4C. First, the timing controller 312 can transmit the first start pulse P1 to the first shift register SR01 in the first shift register sequence, and the shift register SR01 shifts the first start pulse P1 to the right. The timing controller 312 transmits a second start pulse P2 to the first shift register SR09 in the second shift register sequence before the first start pulse P1 is shifted to a target shift register in the first shift register sequence. In the example where the target shift register is SR05, the timing controller 312 can transmit the second start pulse P2 when the first start pulse P1 is in the shift register SR04, so that in the next period, the first start pulse P1 reaches the target shift register SR05 and the second start pulse P2 reaches the shift register SR09 at about the same time. After the second start pulse P2 is transmitted to the second shift register sequence, the second start pulse P2 is sequentially shifted to the right of the last shift register SR 16.

The target shift register is determined according to the number of dummy channels (denoted by D) and the total number of shift registers in the first shift register sequence (denoted by N). More specifically, the first shift register which first receives the first start pulse P1 from the timing controller 312 is separated from the target shift register by (N-D-1) shift registers. In the embodiment of fig. 4C, N is equal to 8 and D is equal to 4, so the interval (N-D-1) between the shift register SR01 and the target shift register SR05 is 3 shift registers (i.e., the shift registers SR02, SR03, and SR 04). Therefore, the timing point when the second start pulse P2 is transmitted may be determined by the number of dummy channels in the source driving circuit, and if the number of dummy channels is large, the timing controller transmits the second start pulse P2 earlier.

Fig. 4D shows the start pulse transmitted from right to left. In FIG. 4D, the shift registers SR16 SR09 can be regarded as the first shift register sequence and the shift registers SR08 SR01 can be regarded as the second shift register sequence. Similar to the embodiment of FIG. 4C, first, the timing controller 312 can transmit the first start pulse P1 to the first shift register SR16 in the first shift register sequence, and the shift register SR16 shifts the first start pulse P1 to the left. The timing controller 312 transmits a second start pulse P2 to the first shift register SR08 in the second shift register sequence before the first start pulse P1 is shifted to a target shift register in the first shift register sequence. In the example where the target shift register is SR12, the timing controller 312 can transmit the second start pulse P2 when the first start pulse P1 is in the shift register SR13, so that in the next period, the first start pulse P1 reaches the target shift register SR12 and the second start pulse P2 reaches the shift register SR08 at about the same time.

The source driver circuit of the driving system 30 has a latch circuit coupled to the shift register circuit. In the embodiment of FIG. 3, the latch circuit in the source driving circuit of the driving system 30 includes 16 latch units L01-L16 (not shown in FIG. 3) respectively coupled to 16 shift registers SR 01-SR 16. In one embodiment, either the shift registers corresponding to the active output channels (SR01 SR06 and SR11 SR16) or the shift registers corresponding to the dummy channels (SR07 SR10) can shift the received enable pulse (P1 or P2) and generate an enable signal to enable the corresponding latch unit to sample the data transmitted on the data bus. Therefore, the pixel data of a horizontal display line can be sequentially sampled by the latch unit. Each of the latches L01-L08 is coupled to a data BUS BUS1, and each of the latches L09-L16 is coupled to another data BUS BUS2 (not shown in FIG. 3). The timing controller 312 is coupled to the data buses 1 and 2, and can control the timing of the pixel data transmitted through the data buses, respectively. The timing controller 312 knows which shift register (e.g., a counter) the current start pulse (P1 or P2) is shifted to, and therefore the timing controller 312 can output the corresponding data (which may be valid pixel data or dummy data) to the data bus line so that the data can be sampled by the corresponding latch unit. The effective output channels corresponding to the shift registers SR01 SR06 and SR11 SR16 are represented by CH01 CH06 and CH11 CH16, and the dummy channels corresponding to the shift registers SR07 SR10 are represented by CH07 CH10 (not shown in FIG. 3).

In one embodiment of the present invention, when the corresponding start pulse (P1 or P2) is shifted to the shift register corresponding to the dummy channel (such as SR07, SR08, SR09 or SR10 shown in FIGS. 4C and 4D), the data bus does not transmit the valid pixel data, and the voltage level on the data bus can be controlled to a specific voltage level, which is regarded as dummy data. In this way, the latch unit corresponding to the shift register SR07, SR08, SR09 or SR10 can sample dummy data corresponding to a dummy channel not coupled to a data line on the display panel.

In another embodiment of the present invention, the timing controller 312 can know the time when the first start pulse P1 is shifted to the shift register SR06 (i.e. the previous shift register of the shift register SR07 corresponding to the dummy channel), in which case the timing controller 312 can stop transmitting the clock signal to the shift register in the last two cycles. In this way, the shift registers SR07 and SR08 cannot shift the first start pulse P1 and cannot generate the corresponding enable signal, so that the corresponding latch unit does not sample the pixel data.

Taking fig. 4C and 4E as an example, when the first start pulse P1 is sequentially shifted in the shift registers SR01 SR04, the timing controller 312 can normally output the pixel data to the data BUS1, so that the latch units L01L 04 can sequentially sample the pixel data transmitted on the data BUS 1. Therefore, the output channels CH 01-CH 04 can output the data voltage signals.

When the first start pulse P1 shifts and reaches the target shift register SR05, the second start pulse P2 transmitted by the timing controller 312 reaches the shift register SR09 at about the same time. Correspondingly, the timing controller 312 may transfer corresponding pixel data to the data BUS1 and dummy data to the data BUS2 (i.e., the control BUS2 is at a particular voltage level), in which case the output channel CH05 may output a data voltage signal and the dummy channel CH09 may output a dummy signal.

In the next period, the first start pulse P1 is shifted to the shift register SR06 and the second start pulse P2 is shifted to the shift register SR 10. Correspondingly, the timing controller 312 may transmit corresponding pixel data to the data BUS1 and dummy data to the data BUS2 such that the output channel CH06 may output a data voltage signal and the dummy channel CH10 may output a dummy signal.

Then, in the next period, the first start pulse P1 is shifted to the shift register SR07 corresponding to the dummy channel CH07 and the second start pulse P2 is shifted to the shift register SR11 corresponding to the active output channel CH 11. Correspondingly, the timing controller 312 may transfer dummy data to the data BUS1 (i.e., the control BUS1 is at a particular voltage level) and transfer corresponding pixel data to the data BUS2, such that the dummy channel CH07 may output a dummy signal and the output channel CH11 may output a data voltage signal.

Then, in the next period, the first start pulse P1 is shifted to the shift register SR08 corresponding to the dummy channel CH08 and the second start pulse P2 is shifted to the shift register SR12 corresponding to the active output channel CH12, at which time the dummy channel CH08 can output a dummy signal and the output channel CH12 can output a data voltage signal. Then, the second start pulse P2 is sequentially shifted to the last shift register SR16, outputting channels CH 13-CH 16 and outputting data voltage signals accordingly.

Based on the driving system 30 shown in FIG. 3, the first start pulse P1 and the second start pulse P2 can be transmitted to the shift register sequence in different directions, as shown in FIGS. 4A-4D. Referring to FIGS. 5A-5D, FIGS. 5A-5D show the same circuit as FIG. 3 with different transmission direction indications of the first start pulse P1 and the second start pulse P2. Fig. 5A and 5B show a case where 16 shift registers correspond to valid output channels.

According to fig. 5A, the timing controller 312 first transmits the first start pulse P1 to the first shift register SR09 in the first shift register series (SR09 SR16), and after the first start pulse P1 sequentially shifts to the end SR16 of the first shift register series, the timing controller 312 can transmit the second start pulse P2 to the first shift register SR01 and the second start pulse P2 in the second shift register series (SR01 SR08) sequentially shifts to the end SR08 of the second shift register series. According to FIG. 5B, the timing controller 312 first transmits the first start pulse P1 to the first shift register SR08 in the first shift register series (SR08 SR01), and when the first start pulse P1 sequentially shifts to the end SR01 of the first shift register series, the timing controller 312 then transmits the second start pulse P2 to the first shift register SR16 in the second shift register series (SR16 SR 09).

Referring to fig. 5C and 5D, in which four output channels corresponding to the shift registers SR01, SR02, SR15 and SR16 (marked by oblique lines) are set as dummy channels, the shift registers SR03 to SR14 correspond to 12 effective output channels, and can be used to drive a display panel with a horizontal resolution of 12 pixels (if a one-out-of-three data selector is used). According to FIG. 5C, the timing controller 312 can transmit the second start pulse P2 to the shift register SR01 before the first start pulse P1 is shifted to the target shift register SR13, so that in the next period, the first start pulse P1 reaches the target shift register SR13 and the second start pulse P2 reaches the shift register SR01 at about the same time. Please refer to FIG. 5E, which is a waveform diagram illustrating the waveforms of the firing pulses P1 and P2 transmitted in the direction shown in FIG. 5C.

Fig. 5D shows a transmission scheme similar to that of fig. 5C, which is not described in detail here. The timing controller 312 may transmit the pixel data or the dummy data to the data bus at a suitable time point, such that the latch units corresponding to the shift registers SR 03-SR 14 may sample the pixel data, and the latch units corresponding to the shift registers SR01, SR02, SR15 and SR16 may sample the dummy data.

Referring to fig. 6A to 6E, fig. 6A to 6E are schematic diagrams illustrating a method for transmitting a start pulse to a shift register in a display device 60 according to an embodiment of the invention. As shown in fig. 6A to 6E, the display device 60 includes a display panel 600 and a source driving circuit 610. It should be noted that the display device 60 further includes a timing controller, which is not shown in the following description without affecting the present embodiment. The source driving circuit 610 includes a shift register circuit and a plurality of output channels, the shift register circuit further includes a plurality of shift registers corresponding to the plurality of output channels, wherein a portion of the output channels are coupled to data lines (hereinafter referred to as active output channels) on the display panel 600, and another portion of the output channels are set as dummy channels and are not coupled to the data lines on the display panel 600, and the dummy channels are output channels located in the middle region. The shift registers in the source driver 610 can be divided into a first shift register sequence and a second shift register sequence, wherein each shift register corresponds to an output channel. The timing controller may transmit a first start pulse (P1 in fig. 4C) to the first shift register in the first shift register sequence (in this case, the leftmost shift register in the first shift register sequence), and transmit a second start pulse (P2 in fig. 4C) to the first shift register in the second shift register sequence (in this case, the leftmost shift register in the second shift register sequence), the start pulses being shifted to the right sequentially. In fig. 6A to 6E, the shift register through which the start pulse has passed is indicated by oblique lines. Note that the source driver circuit 610 in fig. 6A to 6E omits a latch circuit, a level shift circuit, a digital-analog converter circuit, an output buffer circuit, and the like.

In fig. 6A, the first start pulse is transmitted by the timing controller and shifted in the first shift register sequence, while the second start pulse is not yet transmitted.

In fig. 6B, a second start pulse is delivered to the first shift register in the second shift register series corresponding to the dummy channel at about the same time as the first start pulse is shifted to the destination shift register.

In fig. 6C, the first start pulse is shifted from the shift register corresponding to the effective output channel to the shift register corresponding to the dummy channel, and accordingly, the timing controller ends the display data transmission on the left half horizontal display lines. At the same time, the second start pulse is shifted from the shift register corresponding to the dummy channel to the shift register corresponding to the effective output channel, and correspondingly, the timing controller starts to transmit the display data on the right half horizontal display lines.

In fig. 6D, the first start pulse is sequentially shifted between the shift registers corresponding to the dummy channels in the first shift register series, and the second start pulse is sequentially shifted between the shift registers corresponding to the active output channels. Therefore, the timing controller can continuously transmit the display data to the data bus. It is noted that the first start pulse may continuously shift or stop shifting between the shift registers corresponding to the dummy channels, which does not affect the display operation of the display panel 600. In one embodiment, the shift register stops shifting the first start pulse when the timing controller stops transmitting the clock signal to the shift register circuit.

In FIG. 6E, the first start pulse is shifted to the last shift register in the first shift register sequence (in this case, the rightmost shift register in the first shift register sequence), and the second start pulse is shifted to the right continuously, and correspondingly, the timing controller continuously transmits the display data on the right half of the horizontal display lines. Reference is made to fig. 3 to 5E for a detailed operation of fig. 6A to 6E.

Since the timing controller can control the time points of transmitting the first start pulse and the second start pulse, the number of output channels (i.e., the number of dummy channels) to be skipped can be arbitrarily set. In this case, the source driving circuit and the driving system of the embodiment of the invention can be applied to the horizontal resolution of any display panel without providing additional connecting lines between non-adjacent shift registers. For the display panel, the horizontal resolution can be fine-tuned. For example, by selecting the manner of transmitting the second start pulse at different time points, the horizontal resolution that can be supported by the source driving circuit with 1280 output channels includes 1280, 1278, 1276, 1274, etc.

It is noted that the number of dummy channel settings may be determined according to the horizontal resolution of the display panel. In one embodiment, the timing controller includes a counter for determining when to transmit the second start pulse, and the counter is set according to a horizontal resolution of the display panel.

In the above embodiments, the shift register can be divided into two shift register sequences, and the timing controller transmits the first start pulse to the first shift register sequence and transmits the second start pulse to the second shift register sequence. For this shift register circuit structure, the most extreme case is that the timing controller transmits the first start pulse and the second start pulse at the same time, in which case half of the output channels in the source driving circuit are set as dummy channels. That is, the horizontal resolution range that can be supported by the driving system adopting the shift register circuit structure is X/2 to X, wherein X is the total number of output channels in the source driving circuit. The circuit structure of the shift register may be further modified to be suitable for the case where the horizontal resolution is lower than X/2.

Referring to fig. 7A to 7C, fig. 7A to 7C are schematic diagrams of a driving system 70 according to an embodiment of the invention. Fig. 7A shows a circuit structure of the driving system 70, which includes a timing controller 712 and a source driving circuit. The source driving circuit comprises a plurality of output channels and a plurality of shift registers corresponding to the output channels. For convenience of illustration, the source driver circuit includes only 16 shift registers SR01 SR16 corresponding to 16 output channels. As for other components and circuit elements of the source driver circuit, such as a latch circuit, a level shifter circuit, a digital-to-analog converter circuit, and an output buffer circuit, they are not shown without affecting the description of the present embodiment. Fig. 7B shows a circuit configuration for a case when the driving system 70 of fig. 7A drives a display panel with a horizontal resolution equal to or less than half of the resolution supportable by the source driving circuit of the driving system 70 of fig. 7A. FIG. 7C shows another circuit configuration for a case when the driving system 70 of FIG. 7A drives a display panel with a horizontal resolution equal to or greater than half the resolution that can be supported by the source driving circuit of the driving system 70 of FIG. 7A.

Similar to the source driving circuit shown in fig. 3, in fig. 7A, the shift registers SR 01-SR 16 in the source driving circuit of the driving system 70 are also divided into 2 shift register sequences, wherein the first shift register sequence includes 8 shift registers SR 01-SR 08 disposed at one side of the timing controller 712, and the second shift register sequence includes 8 shift registers SR 09-SR 16 disposed at the other side of the timing controller 712. In addition, in FIG. 7A, the source driving circuit further includes 4 switches SW 1-SW 4 coupled between the shift registers SR 01-SR 16. In detail, switch SW1 is coupled between timing controller 712 and shift register SR08, switch SW2 is coupled between two adjacent shift registers SR04 and SR05 and also coupled to timing controller 712, switch SW3 is coupled between timing controller 712 and shift register SR09, and switch SW4 is coupled between two adjacent shift registers SR12 and SR13 and also coupled to timing controller 712. Each of the switches SW 1-SW 4 may receive a control signal for controlling the operations of the switches SW 1-SW 4, and the control signals are omitted from FIGS. 7A-7C for simplicity.

The switches SW 1-SW 4 can be set such that the source driving circuit of the driving system 70 can be applied to a display panel with a horizontal resolution equal to or less than half the resolution that the source driving circuit can support (i.e., equal to or less than half the number of output channels of the source driving circuit). In the embodiment of FIG. 7B, the switch SW1 is turned off, and the switch SW2 is turned on to connect the timing controller 712 and the shift register SR04, at which time the shift registers SR05 SR08 stop operating and the output channels corresponding to the shift registers SR05 SR08 are set as dummy channels. Similarly, the switch SW3 is turned off, and the switch SW4 is turned on to connect the timing controller 712 and the shift register SR13, at which time the shift registers SR09 SR12 stop operating and the output channels corresponding to the shift registers SR09 SR12 are set as dummy channels. In this case, the timing controller 712 may transmit the first start pulse to the shift register SR01 and the second start pulse to the shift register SR13, and the timing controller 712 may determine a time point of transmitting the second start pulse and set the dummy channel accordingly.

In the embodiment of FIG. 7B, an extreme case is that half of the output channels corresponding to the activated shift registers SR01 SR04 and SR13 SR16 are set as dummy channels, as shown in FIG. 8A. Fig. 8A shows a case where the driving system 70 is used for a display device having a horizontal resolution of 4 pixels, when 12 dummy channels exist in the source driving circuit. In this example, the output channels corresponding to the shift registers SR03 SR14 are set as dummy channels. Switch SW1 is turned off, switch SW2 is turned on to connect timing controller 712 with shift register SR04, switch SW3 is turned off, and switch SW4 is turned on to connect timing controller 612 with shift register SR 13. In this case, the timing controller may transmit the first start pulse and the second start pulse at the same time.

FIG. 8B is a waveform diagram illustrating the waveforms of the start pulse in the source driving circuit of FIG. 8A. As shown in FIG. 8B, when the first start pulse P1 is transmitted to the shift register SR01 and the second start pulse P2 is transmitted to the shift register SR13, the timing controller 712 transmits the first start pulse P1 and the second start pulse P2 at the same time. In this example, the target shift register may be shift register SR 01. When the first start pulse P1 is shifted to the shift register SR03 corresponding to the dummy channel, the second start pulse P2 is shifted to the shift register SR15 corresponding to the active output channel.

Alternatively, if the driving system 70 is applied to a display panel with a horizontal resolution greater than or equal to 8, the switches SW 1-SW 4 can be set as shown in FIG. 7C. In detail, the switch SW1 is turned on to connect the timing controller 712 and the shift register SR08, and the switch SW2 is turned on to connect the shift registers SR04 and SR 05. On the right side of the timing controller 712, the switch SW3 is turned on to connect the timing controller 712 and the shift register SR09, and the switch SW4 is turned on to connect the shift registers SR12 and SR 13. In the embodiment of fig. 7C, the operation of the driving system 70 is similar to that of fig. 4A-4D and 5A-5D, and is not repeated herein.

It is noted that the present invention is directed to a novel shift register circuit structure for a source driver circuit and a method for driving a display panel by controlling the timing point of the start pulse transmitted by a timing controller, so that the source driver circuit is applicable to more display panels with different horizontal resolutions. Those skilled in the art can make modifications or changes thereto without being limited thereto. For example, in the above embodiments, the number of shift registers in each shift register series is equal, however, in another embodiment, the number of shift registers in the first shift register series may be greater or less than the number of shift registers in the second shift register series. Further, in the above-described embodiment, the output channels located in the middle are set as dummy channels, and the dummy channels are equally distributed to the left and right sides of the timing controller. In another embodiment, the leftmost and/or rightmost output channels can be set as dummy channels, and the middle output channel can be coupled to the data lines on the display panel. In yet another embodiment, all or most of the dummy channels may be disposed on the same side of the timing controller. It should be noted that the dummy channels are preferably disposed in the middle region and equally distributed to the left and right sides of the timing controller, which can achieve bilateral symmetry of the display device load.

It should be noted that the timing controller may or may not be disposed between the shift registers. In one embodiment, the timing controller and the source driving circuit may be included in a single semiconductor chip. In other words, a display driving integrated circuit may include the timing controller and the source driving circuit, and is preferably suitable for a small-sized display device. In another embodiment, the timing controller may be included inside a semiconductor chip, and the source driving circuit may be included inside another semiconductor chip, or may be formed of a plurality of semiconductor chips. A driving system of a large-sized display device may include one or more source driving chips and a timing controller chip.

In one embodiment, the shift register can be divided into more sequences. For example, a source driver circuit may include 4 shift register sequences, and the timing controller is connected to both ends of each shift register sequence. This embodiment can be adopted when the source driver circuit includes two source driver chips and the shift registers in each source driver chip are divided into two groups. In this case, the timing controller may also set the time point for transmitting each start pulse to the respective shift register sequence, so that the source driving circuit may be applicable to display devices having different horizontal resolutions. For example, the timing controller may transmit a first start pulse to a first shift register sequence, a second start pulse to a second shift register sequence, a third start pulse to a third shift register sequence, and a fourth start pulse to a fourth shift register sequence. The shift registers corresponding to the dummy channels may be equally allocated to the four shift register sequences, and thus, the timing controller may transmit the second start pulse before the first start pulse is shifted to one target shift register and transmit the fourth start pulse before the third start pulse is shifted to another target shift register.

The operation of the above-described method for transmitting the start pulse to the shift register can be summarized as a process 90, as shown in FIG. 9. The process 90 can be applied to a timing controller of a display device, which includes the following steps:

step 900: and starting.

Step 902: a first start pulse is transmitted to a first shift register, which is an end of a first shift register sequence.

Step 904: before the first start pulse is shifted to a target shift register in the first shift register sequence, a second start pulse is transmitted to a second shift register, which is an endpoint of a second shift register sequence.

Step 906: and (6) ending.

For the detailed operation of the process 90, reference is made to the description in the above paragraphs, which are not repeated herein.

In summary, the present invention provides a novel shift register circuit structure for a source driver circuit and a method for driving a display panel by controlling the time point when a timing controller transmits a start pulse. The shift register can be divided into a plurality of shift register sequences, and the time sequence controller is connected with two ends of each shift register sequence. The timing controller transmits a first start pulse to the first shift register sequence, and transmits a second start pulse before the first start pulse is shifted to a target shift register. By controlling the time point of the second start pulse transmission, the source driving circuit can be suitable for display panels with different horizontal resolutions.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A source driving circuit for driving a display panel includes:

a plurality of output channels; and

a plurality of shift registers corresponding to the plurality of output channels, respectively, wherein,

the shift registers are divided into a plurality of shift register sequences, a first shift register sequence in the shift register sequences comprises a first shift register and a second shift register, the first shift register is one end point of the first shift register sequence, the second shift register is the other end point of the first shift register sequence, a second shift register sequence in the shift register sequences comprises a third shift register and a fourth shift register, the third shift register is one end point of the second shift register sequence, and the fourth shift register is the other end point of the second shift register sequence;

wherein the first shift register sequence has a first partial sequence including the second shift register and the second shift register sequence has a second partial sequence including the third shift register, the first partial sequence and the second partial sequence correspond to a plurality of dummy channels, and the plurality of dummy channels are a plurality of output channels of the plurality of output channels that are not coupled to the data lines on the display panel;

the first shift register, the second shift register, the third shift register and the fourth shift register are connected to a time schedule controller, the first shift register is used for receiving a first start pulse transmitted by the time schedule controller, the third shift register is used for receiving a second start pulse transmitted by the time schedule controller, wherein the first start pulse starts to be transmitted in advance before the second start pulse starts to be transmitted, and the advance time is set according to the number of the plurality of dummy channels.

2. The source driver circuit of claim 1, wherein the second start pulse is transmitted to the third shift register when the first start pulse is shifted to a destination shift register in the first shift register sequence.

3. The source driver circuit of claim 2, wherein the first shift register and the destination shift register are separated by N-D-1 shift registers, where N is equal to the total number of shift registers in the first shift register sequence and D is equal to the number of dummy channels included in the plurality of output channels and not coupled to data lines on the display panel.

4. The source driver circuit of claim 1, further comprising:

a first switch coupled between the timing controller and the second shift register;

a second switch coupled between two adjacent shift registers in the first shift register sequence and coupled to the timing controller;

a third switch coupled between the timing controller and the third shift register; and

and the fourth switch is coupled between two adjacent shift registers in the second shift register sequence and coupled to the time schedule controller.

5. The source driver circuit as claimed in claim 4, wherein when the horizontal resolution of the display panel is less than half of the number of output channels in the source driver circuit, the first switch is turned off and the second switch is turned on to connect the timing controller to one of the two adjacent shift registers that is relatively close to the first shift register.

6. The source driver circuit of claim 1, wherein the second shift register in the first shift register series and the third shift register in the second shift register series are not connected to each other.

7. The source driver circuit of claim 1, wherein the timing controller and the source driver circuit are included in a semiconductor chip.

8. The source driver circuit of claim 1, wherein the source driver circuit is formed of a plurality of first semiconductor chips and the timing controller is a second semiconductor chip.

9. A driving system for driving a display panel, comprising:

a time sequence controller for generating a first start pulse and a second start pulse; and

the source electrode driving circuit comprises a plurality of output channels and a plurality of shift registers, wherein the shift registers respectively correspond to the output channels;

the timing controller is connected to the first shift register, the second shift register, the third shift register and the fourth shift register, and is used for transmitting the first start pulse to the first shift register and transmitting the second start pulse to the third shift register, wherein the first start pulse starts to be transmitted in advance before the second start pulse starts to be transmitted, and the advance time is set according to the number of the dummy channels.

10. The driving system as recited in claim 9 wherein said second start pulse is transmitted to said third shift register when said first start pulse is shifted to a destination shift register in said first shift register sequence.

11. The driving system as recited in claim 10, wherein the first shift register and the destination shift register are separated by N-D-1 shift registers, wherein N is equal to the total number of shift registers in the first shift register sequence and D is equal to the number of dummy channels included in the plurality of output channels and not coupled to data lines on the display panel.

12. The driving system as claimed in claim 9, wherein the timing controller receives an indication indicating a horizontal resolution of the display panel, and the timing controller determines to transmit the second start pulse at a time point such that the second start pulse is shifted to the third shift register while the first start pulse is shifted to a target shift register in the first shift register sequence according to the indication.

13. The driving system as claimed in claim 12, wherein the timing controller comprises a counter for determining when to transmit the second start pulse to the third shift register, wherein the counter is set according to a horizontal resolution of the display panel.

14. The drive system of claim 9, further comprising:

15. The driving system as claimed in claim 14, wherein when the horizontal resolution of the display panel is less than half of the number of output channels in the driving system, the first switch is turned off and the second switch is turned on to connect the timing controller to one of the two adjacent shift registers that is relatively close to the first shift register.

16. The driving system as recited in claim 9 wherein said second shift register in said first shift register series and said third shift register in said second shift register series are not connected to each other.

17. The driving system of claim 9, wherein the timing controller and the source driving circuit are included in a semiconductor chip.

18. The driving system as claimed in claim 9, wherein the source driving circuit is formed of a plurality of first semiconductor chips, and the timing controller is a second semiconductor chip.

19. A display device, comprising:

a display panel;

a source driving circuit for driving the display panel, the source driving circuit including a plurality of output channels and a plurality of shift registers, the plurality of shift registers respectively corresponding to the plurality of output channels;

20. The display device of claim 19, wherein the second start pulse is shifted to the third shift register when the first start pulse is shifted to a target shift register in the first shift register sequence.

21. The display device of claim 20, wherein the first shift register and the target shift register are separated by N-D-1 shift registers, wherein N is equal to a total number of shift registers in the first shift register sequence and D is equal to a number of dummy channels included in the plurality of output channels and not coupled to data lines on the display panel.

22. The display device of claim 19, wherein the timing controller receives an indication indicating a horizontal resolution of the display panel, and determines to transmit the second start pulse at a time point such that the second start pulse is shifted to the third shift register at the same time as the first start pulse is shifted to a target shift register in the first shift register sequence according to the indication.

23. The display device of claim 22, wherein the timing controller comprises a counter for determining when to transmit the second start pulse to the third shift register, wherein the counter is set according to a horizontal resolution of the display panel.

24. The display device according to claim 19, wherein the source driving circuit further comprises:

25. The display device according to claim 24, wherein when the horizontal resolution of the display panel is less than half of the number of output channels in the source driving circuit, the first switch is turned off and the second switch is turned on to connect the timing controller to one of the two adjacent shift registers that is relatively close to the first shift register.

26. The display device of claim 19, wherein the second shift register in the first series of shift registers and the third shift register in the second series of shift registers are not connected to each other.

27. The display device according to claim 19, wherein the timing controller and the source driving circuit are included in a semiconductor chip.

28. The display device according to claim 19, wherein the source driving circuit is formed of a plurality of first semiconductor chips, and the timing controller is a second semiconductor chip.

29. A method for driving a display panel is used for a driving system comprising a timing controller and a source driving circuit, wherein the source driving circuit comprises a plurality of shift registers, the plurality of shift registers are divided into a plurality of shift register sequences, and the plurality of shift registers comprise a first shift register sequence and a second shift register sequence, and the method comprises the following steps:

the time schedule controller transmits a first starting pulse to one end point of the first shift register sequence of the source electrode driving circuit; and

the timing controller transmits a second start pulse to a terminal of the second shift register sequence of the source driver circuit before the first start pulse is shifted to a target shift register in the first shift register sequence;

wherein a first partial sequence of the first shift register sequence and a second partial sequence of the second shift register sequence correspond to a plurality of dummy channels, and the dummy channels are output channels of a plurality of output channels not coupled to the data lines on the display panel;

wherein, before the second start pulse starts to transmit, the first start pulse starts to transmit in advance, and the advance time is set according to the number of the dummy channels.

30. The method of claim 29 wherein the second start pulse is transmitted to a third shift register in the second shift register series when the first start pulse is shifted to the destination shift register in the first shift register series.

31. The method as claimed in claim 30, wherein the first shift register and the target shift register are separated by N-D-1 shift registers, where N is equal to the total number of shift registers in the first shift register sequence and D is equal to the number of dummy channels included in the plurality of output channels of the source driver circuit and not coupled to the data lines on the display panel.

32. The method of claim 29, further comprising:

the timing controller determines when to transmit the second start pulse to a third shift register in the second shift register sequence according to the horizontal resolution of the display panel.