CN108682683A - A kind of pressure eliminant power electronics diode and its production technology - Google Patents

A kind of pressure eliminant power electronics diode and its production technology Download PDF

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Publication number
CN108682683A
CN108682683A CN201810310103.6A CN201810310103A CN108682683A CN 108682683 A CN108682683 A CN 108682683A CN 201810310103 A CN201810310103 A CN 201810310103A CN 108682683 A CN108682683 A CN 108682683A
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CN
China
Prior art keywords
type layer
pressure
eliminant
power electronics
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810310103.6A
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Chinese (zh)
Inventor
王兴龙
李述洲
刘章利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Pingwei Enterprise Co Ltd
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Chongqing Pingwei Enterprise Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to CN201810310103.6A priority Critical patent/CN108682683A/en
Publication of CN108682683A publication Critical patent/CN108682683A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8613Mesa PN junction diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes

Abstract

The invention discloses a kind of pressure eliminant power electronics diodes, including the copper-based of P-type layer, P+ type layer, N+ types layer, N types layer and both ends, be equipped with groove close to the surface of P+ type layer in P-type layer, P+ type layer, P+ type layer with it is corresponding it is copper-based between scolding tin, corresponding copper-based inner surface be disposed as the shape mating with the groove in P-type layer.The invention also discloses a kind of production technologies of pressure eliminant power electronics diode, include the following steps:Egative film prepares;Groove etching;Ion implanting;Trench etch;Passivation Treatment;Oxidation film is sintered;Lithography fair lead;Surface metalation;Both ends are connect by scolding tin with copper-based progress alloy, pressure eliminant power electronics diode is formed.Pressure surface area bigger of the eliminant power electronics diode P-type layer by P+ type layer and scolding tin and corresponding copper-based contact of the present invention extends the application range of power electronics diode to be obviously improved electric current handling capacity, pressure-resistant performance and heat dissipation effect.

Description

A kind of pressure eliminant power electronics diode and its production technology
Technical field
The present invention relates to a kind of power electronics diode and its production technology more particularly to a kind of pressure eliminant power electronics two Pole pipe and its production technology.
Background technology
When power electronic devices works, device heating, heating can be caused because of power attenuation.Device temperature is excessively high will to shorten the longevity Life, or even burn, this is the main reason for limiting power electronic devices electric current, voltage capacity.For that purpose it is necessary to consider the cold of device But problem.With the continuous development that power electronic technique is applied, the requirement to power electronic devices performance indicator and reliability It is increasingly strict.Specifically, it is desirable that power electronic devices has the current density of bigger, higher operating temperature, stronger dissipates Thermal energy power, higher operating voltage, lower on-state voltage drop, faster switch time, and for space flight and Military Application, also want Stronger capability of resistance to radiation and anti-vibrating and impact ability are asked.
For the application problem more than overcoming, if designing with good heat radiating ability and having sufficiently high reversed resistance to A kind of pressure eliminant power electronics diode of pressure just has great application prospect, future to can be used for intelligent grid, automotive electronics, letter Breath and office automation, household special power supply, traction special power supply, new energy, solar energy, wind energy and fuel cell power source etc..
But traditional power electronics diode, P-type layer surface are plane, pass through scolding tin and copper-based electric connection Contact surface be also plane, there is a problem of that electric current handling capacity is insufficient, pressure-resistant performance is insufficient, heat dissipation effect is poor, limit The application range of power electronics diode.
Invention content
The purpose of the present invention is that solve the above-mentioned problems and provides that a kind of electric current handling capacity is strong, pressure-resistant performance Good, heat dissipation effect preferably presses eliminant power electronics diode and its production technology.
The present invention is achieved through the following technical solutions above-mentioned purpose:
A kind of pressure eliminant power electronics diode, including P-type layer, P+ type layer, N+ types layer, N-type layer and the copper at both ends Base, the P+ type layer and the N+ types layer are respectively by the copper-based connection of scolding tin and both ends, close to described in the P-type layer The surface of P+ type layer be equipped with groove, the P+ type layer, the P+ type layer with it is corresponding it is described it is copper-based between scolding tin, corresponding institute It states copper-based inner surface and is disposed as the shape mating with the groove in the P-type layer.Here mating, refer on P+ type layer and Position corresponding with the groove of P-type layer is equipped with recessed groove, copper-based inner surface position corresponding with the groove of P-type layer on scolding tin Corresponding convex block is installed.
Specifically, the groove in the P-type layer is four circular grooves and is uniformly distributed in the surface of the P-type layer, institute The depth for stating circular groove is 20-30um, radius 100-1000um.
Alternatively, the groove in the P-type layer is a square groove, the depth of the square groove is 20-30um, side A length of 200-2000um.
A kind of production technology of pressure eliminant power electronics diode, includes the following steps:
Step (1):Egative film prepares:The egative film division chip area of P-type layer, N-type layer, N+ type layers will have been spread;
Step (2):Groove etching:Etch depth is the groove of 20-30um on the outer surface of the P-type layer;
Step (3):Ion implanting:P+ is formed by way of ion implanting on the P-type layer surface once etched Type layer;
Step (4):Trench etch:Trench etch is carried out according to required chip area, is partitioned into respective chip area;
Step (5):Passivation Treatment:Processing is passivated to groove with SIPOS;SIPOS is to mix oxygen semi-insulating polysilicon Film has half insulation and electroneutral;
Step (6):Oxidation film is sintered:Vitreous coating and sintering processes are carried out on the outside of the P-type layer and the N-type layer Form oxidation film;
Step (7):Lithography fair lead;
Step (8):Surface metalation:Gold-plated or Nickel Plating Treatment is carried out in two end surfaces;
Step (9):Both ends are connect by scolding tin with copper-based progress alloy, pressure eliminant power electronics diode is formed.
Preferably, in the step (1), diffusion depth 70-90um, the electrical resistivity range 45-70 of the P-type layer Ω·cm。
Preferably, in the step (3), the thickness of the P+ type layer is 2-5um, a concentration of 1*1020cm-3
The beneficial effects of the present invention are:
The present invention by being arranged groove on P-type layer surface, and by P+ type layer and corresponding scolding tin, copper-based carry out corresponding shape The adaptability design of shape, the surface area bigger for making P-type layer pass through P+ type layer and scolding tin with corresponding copper-based contact, to significantly Electric current handling capacity, pressure-resistant performance and heat dissipation effect are improved, the application range of power electronics diode is extended, it is especially suitable In the high requests such as space flight and Military Application application scenario.
Description of the drawings
Fig. 1 is one of the sectional view of pressure eliminant power electronics diode of the present invention;
Fig. 2 is one of the vertical view of P-type layer of pressure eliminant power electronics diode of the present invention;
Fig. 3 is the two of the sectional view of pressure eliminant power electronics diode of the present invention;
Fig. 4 is the two of the vertical view of the P-type layer of pressure eliminant power electronics diode of the present invention.
Specific implementation mode
With reference to embodiment and attached drawing, the invention will be further described:
Embodiment 1:
As depicted in figs. 1 and 2, a kind of pressure eliminant power electronics diode, including P-type layer 4, P+ type layer 3, N+ types layer 7, Copper-based the 1 of N-type layer 6 and both ends, P+ type layer 3 and N+ types layer 7 are connect by scolding tin 2 with copper-based the 1 of both ends respectively, P-type layer 4 The upper surface close to P+ type layer 3 sets that there are four the circular groove 41 on the surface for being uniformly distributed in P types layer 4, the depths of circular groove 41 Degree is 20-30um, radius 100-1000um, and P+ type layer 3, P+ type layer 3 (are in figure with the scolding tin 2 between corresponding copper-based 1 The scolding tin 2 on top), it is corresponding that copper-based 1 (inner surface of copper-based 1) in figure for top is disposed as and the groove in P-type layer 4 41 mating shapes, i.e., on P+ type layer 3, on scolding tin 2 position corresponding with four circular grooves 41 of P-type layer 4 be equipped with it is recessed Four grooves, copper-based 2 inner surface position corresponding with four circular grooves 41 of P-type layer 4 is equipped with corresponding four convex blocks; The outside of P-type layer 4 and N-type layer 6 is equipped with oxidation film 5.
Embodiment 2:
As shown in Figure 3 and Figure 4, a kind of pressure eliminant power electronics diode, including P-type layer 4, P+ type layer 3, N+ types layer 7, Copper-based the 1 of N-type layer 6 and both ends, P+ type layer 3 and N+ types layer 7 are connect by scolding tin 2 with copper-based the 1 of both ends respectively, P-type layer 4 The upper surface close to P+ type layer 3 sets that there are one the square groove 42 that depth is 200-2000um as 20-30um, the length of side, P+ type layers 3, the scolding tin 2 between P+ type layer 3 and corresponding copper-based 1 (being the scolding tin 2 on top in figure), corresponding copper-based 1 (are top in figure Copper-based inner surface 1) is disposed as the shape mating with the groove 41 in P-type layer 4, i.e., on P+ type layer 3, on scolding tin 2 with P The 42 corresponding position of square groove of type layer 4 is equipped with a recessed square groove, the side of copper-based 2 inner surface and P-type layer 4 42 corresponding position of connected in star is equipped with a corresponding bumping square;The outside of P-type layer 4 and N-type layer 6 is equipped with oxidation film 5.
The production technology of the pressure eliminant power electronics diode of above-mentioned two embodiment is consistent, includes the following steps:
Step (1):Egative film prepares:The egative film division chip area of P-type layer 4, N-type layer 6, N+ types layer 7, p-type will have been spread The diffusion depth 70-90um of layer 4, electrical resistivity range are 45-70 Ω cm;
Step (2):Groove etching:Etch depth is corresponding recesses i.e. four of 20-30um on the outer surface of P-type layer 4 A circular groove 41 or a square groove 42;
Step (3):Ion implanting:P+ type is formed by way of ion implanting on the surface of the P-type layer 4 once etched The thickness of layer 3, P+ type layer 3 is 2-5um, a concentration of 1*1020cm-3
Step (4):Trench etch:Trench etch is carried out according to required chip area, is partitioned into respective chip area;
Step (5):Passivation Treatment:Processing is passivated to groove with SIPOS;
Step (6):Oxidation film is sintered:Vitreous coating is carried out in the outside of P-type layer 4 and N-type layer 6 and sintering processes are formed Oxidation film 5;
Step (7):Lithography fair lead;
Step (8):Surface metalation:Gold-plated or Nickel Plating Treatment is carried out in two end surfaces;
Step (9):Both ends are connect by scolding tin 2 with copper-based 1 progress alloy, pressure eliminant power electronics diode is formed.
Above-described embodiment is presently preferred embodiments of the present invention, is not the limitation to technical solution of the present invention, as long as Without the technical solution that creative work can be realized on the basis of the above embodiments, it is regarded as falling into patent of the present invention Rights protection scope in.

Claims (6)

1. a kind of pressure eliminant power electronics diode, including P-type layer, P+ type layer, N+ types layer, N-type layer and both ends it is copper-based, The P+ type layer and the N+ types layer pass through the copper-based connection of scolding tin and both ends respectively, it is characterised in that:In the P-type layer Close to the P+ type layer surface be equipped with groove, the P+ type layer, the P+ type layer with it is corresponding it is described it is copper-based between scolding tin, The corresponding copper-based inner surface is disposed as the shape mating with the groove in the P-type layer.
2. pressure eliminant power electronics diode according to claim 1, it is characterised in that:Groove in the P-type layer is Four circular grooves and the surface for being uniformly distributed in the P-type layer, the depth of the circular groove is 20-30um, radius is 100-1000um。
3. pressure eliminant power electronics diode according to claim 1, it is characterised in that:Groove in the P-type layer is One square groove, the depth of the square groove is 20-30um, length of side 200-2000um.
4. a kind of production technology of pressure eliminant power electronics diode as claimed in claim 1,2 or 3, it is characterised in that:Packet Include following steps:
Step(1):Egative film prepares:The egative film division chip area of P-type layer, N-type layer, N+ type layers will have been spread;
Step(2):Groove etching:Etch depth is the groove of 20-30um on the outer surface of the P-type layer;
Step(3):Ion implanting:P+ type layer is formed by way of ion implanting on the P-type layer surface once etched;
Step(4):Trench etch:Trench etch is carried out according to required chip area, is partitioned into respective chip area;
Step(5):Passivation Treatment:Processing is passivated to groove with SIPOS;
Step(6):Oxidation film is sintered:Vitreous coating is carried out on the outside of the P-type layer and the N-type layer and sintering processes are formed Oxidation film;
Step(7):Lithography fair lead;
Step(8):Surface metalation:Gold-plated or Nickel Plating Treatment is carried out in two end surfaces;
Step(9):Both ends are connect by scolding tin with copper-based progress alloy, pressure eliminant power electronics diode is formed.
5. the production technology of pressure eliminant power electronics diode according to claim 4, it is characterised in that:The step (1)In, the diffusion depth 70-90um of the P-type layer, electrical resistivity range are 45-70 Ω cm.
6. the production technology of pressure eliminant power electronics diode according to claim 4, it is characterised in that:The step (3)In, the thickness of the P+ type layer is 2-5um, a concentration of
CN201810310103.6A 2018-04-09 2018-04-09 A kind of pressure eliminant power electronics diode and its production technology Pending CN108682683A (en)

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Application Number Priority Date Filing Date Title
CN201810310103.6A CN108682683A (en) 2018-04-09 2018-04-09 A kind of pressure eliminant power electronics diode and its production technology

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113054037A (en) * 2019-12-27 2021-06-29 常州星海电子股份有限公司 Fast recovery diode chip and manufacturing method thereof
CN113054037B (en) * 2019-12-27 2024-05-03 常州星海电子股份有限公司 Fast recovery diode chip and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102725848A (en) * 2009-09-23 2012-10-10 维谢综合半导体有限责任公司 Double trench rectifier
US20130240905A1 (en) * 2011-09-08 2013-09-19 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Silicon Carbide Rectifier
CN205428951U (en) * 2016-03-14 2016-08-03 江苏捷捷微电子股份有限公司 VR is greater than 2600V's square piece formula glass passivation diode chip

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102725848A (en) * 2009-09-23 2012-10-10 维谢综合半导体有限责任公司 Double trench rectifier
US20130240905A1 (en) * 2011-09-08 2013-09-19 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Silicon Carbide Rectifier
CN205428951U (en) * 2016-03-14 2016-08-03 江苏捷捷微电子股份有限公司 VR is greater than 2600V's square piece formula glass passivation diode chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113054037A (en) * 2019-12-27 2021-06-29 常州星海电子股份有限公司 Fast recovery diode chip and manufacturing method thereof
CN113054037B (en) * 2019-12-27 2024-05-03 常州星海电子股份有限公司 Fast recovery diode chip and manufacturing method thereof

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Application publication date: 20181019