CN108682376B - Overcurrent protection system and overcurrent protection method - Google Patents
Overcurrent protection system and overcurrent protection method Download PDFInfo
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- CN108682376B CN108682376B CN201810463410.8A CN201810463410A CN108682376B CN 108682376 B CN108682376 B CN 108682376B CN 201810463410 A CN201810463410 A CN 201810463410A CN 108682376 B CN108682376 B CN 108682376B
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- 238000010586 diagram Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
Abstract
The invention discloses an overcurrent protection system and an overcurrent protection method. The driving module is used for providing a first driving signal to the gate driving array. The first current adjusting circuit is coupled between the driving module and the gate driving array, wherein the first current adjusting circuit is located on a current path of a first signal current of the first driving signal. During the pulse period of the first signal current, if the absolute value of the magnitude of the first signal current is greater than a preset threshold value and continuously exceeds a preset time length, the first current adjusting circuit limits the absolute value of the magnitude of the first signal current not to be greater than the preset threshold value until the pulse period of the first signal current is finished.
Description
Technical Field
The invention relates to an overcurrent protection system and an overcurrent protection method suitable for a display panel.
Background
Conventional displays usually include an over-current protection device for protecting the gate driving module. The over-current protection device starts the over-current protection mechanism only when the sum of the over-current events of the gate driving module reaches a specific time length. However, in the process of calculating the total time of the overcurrent events by the overcurrent protection device, the gate driving module continuously receives an excessive current. Therefore, even if the conventional display is provided with the overcurrent protection device, the gate driving module in the conventional display is still easily damaged by being subjected to an excessive current for a long time.
Disclosure of Invention
Therefore, it is an objective of the present invention to provide an over-current protection system and an over-current protection method that can reduce the magnitude of the current borne by the gate driving module in time when an over-current event occurs.
The overcurrent protection system is suitable for a display panel, the display panel comprises a gate drive array and a display area, and the overcurrent protection system comprises a drive module and a first current regulation circuit. The driving module is used for providing a first driving signal to the gate driving array. The first current adjusting circuit is coupled between the driving module and the gate driving array, wherein the first current adjusting circuit is located on a current path of a first signal current of the first driving signal. Wherein, during the pulse period of the first signal current, if the absolute value of the magnitude of the first signal current is greater than a predetermined threshold and exceeds a predetermined time duration, the first current adjustment circuit limits the absolute value of the magnitude of the first signal current not to be greater than the predetermined threshold until the pulse period of the first signal current is finished.
The overcurrent protection method is suitable for a display panel, the display panel comprises a gate drive array and a display area, and the overcurrent protection method comprises the following steps: providing a driving module, wherein the driving module is used for providing a first driving signal to the gate driving array; providing a first current adjusting circuit, wherein the first current adjusting circuit is coupled between the driving module and the gate driving array and is located on a current path of a first signal current of the first driving signal; during the pulse period of the first signal current, if the absolute value of the magnitude of the first signal current is greater than a preset threshold and exceeds a preset time length, the first current adjusting circuit is utilized to limit the absolute value of the magnitude of the first signal current not to be greater than the preset threshold until the pulse period of the first signal current is ended.
The overcurrent protection system and the overcurrent protection method in the above embodiments can prevent the display panel from being damaged by being subjected to an excessive current for a long time.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 is a simplified functional block diagram of an overcurrent protection system according to an embodiment of the invention.
Fig. 2 is a simplified functional block diagram of a gate driving module according to an embodiment of the invention.
Fig. 3 is a simplified timing diagram of an embodiment of the overcurrent protection system of fig. 1.
Fig. 4 is a simplified timing diagram of another embodiment of the overcurrent protection system of fig. 1.
Fig. 5a and 5b are flow charts illustrating an over-current protection method according to an embodiment of the invention.
Wherein the reference numerals are:
100: overcurrent protection system
101: display panel
103: gate driving module
105: display area
110: drive module
120a to 120 n: current regulation circuit
130: logic circuit
140: storage module
201: short-circuit path
203a to 203 n: shift register
500: overcurrent protection method
Ihck 1: first signal current
Ihck 2: second signal current
Vhck 1: a first clock signal
Vhck 2: the second clock signal
Vssg: fixed voltage
Vst: initial pulse signal
Tp: duration of pulse
T1, T2, T3: a first period, a second period, and a third period
s502 to s 528: flow path
Detailed Description
The embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.
Fig. 1 is a simplified functional block diagram of an overcurrent protection system 100 according to an embodiment of the invention. The overcurrent protection system 100 includes a driving module 110, a plurality of current adjusting circuits 120a to 120n, a logic circuit 130, and a storage module 140, wherein the storage module 140 is coupled to the logic circuit 130 and is configured to store information required by the operation of the logic circuit 130. For simplicity and ease of illustration, other elements and connections in the overcurrent protection system 100 are not shown in fig. 1.
The overcurrent protection system 100 is coupled to a display panel 101, wherein the display panel 101 includes a gate driving module 103 and a display area 105. The overcurrent protection system 100 can limit or cut off the current in the gate driving module 103 when an overcurrent (overcurrent) event occurs in the gate driving module 103, so as to prevent the gate driving module 103 from being damaged due to the overcurrent.
In the present embodiment, the overcurrent protection system 100 and the display panel 101 are disposed on different substrates, respectively. However, in some embodiments, the overcurrent protection system 100 may be disposed on the same substrate as the display panel 101.
Fig. 2 is a simplified functional block diagram of the gate driving module 103 according to an embodiment of the invention. Referring to fig. 1 and fig. 2, the driving module 110 is configured to output the first clock signal Vhck1, the second clock signal Vhck2, the start pulse signal Vst and the fixed voltage Vssg to the gate driving module 103, so as to control the gate driving module 103 to update the display image of the display area 105. The first clock signal Vhck1 and the second clock signal Vhck2 are used for sequentially operating the shift registers 203a 203n of the gate driving module 103. The start pulse signal Vst is used to trigger the gate driving array 103 at the beginning of each frame of the display area 105.
Note that, the lower case english indices a to n in the component numbers used in the present specification and drawings are only for convenience of referring to individual components, and are not intended to limit the number of the above components to a specific number. In the specification and drawings, if an element number or a signal number is used without indicating an index of the element number or the signal number, the element number or the signal number refers to any unspecified element or signal in an element group or a signal group. For example, the object designated by the element number 120a is the current adjustment circuit 120a, and the object designated by the element number 120 is an unspecified arbitrary current adjustment circuit 120 among the current adjustment circuits 120a to 120 n.
The current regulator circuit 120a is located on the signal path of the first clock signal Vhck1 between the driving module 110 and the gate driving module 103. The current adjusting circuit 120b is located on the signal path of the second clock signal Vhck2 between the driving module 110 and the gate driving module 103. The current regulator circuit 120c is located on the signal path between the driving module 110 and the gate driving module 103 with the constant voltage Vssg. The current adjusting circuit 120n is located on a signal path of the start pulse signal Vst between the driving module 110 and the gate driving module 103, and so on.
That is, the current adjusting circuits 120a to 120n are respectively located on a plurality of signal paths between the driving module 110 and the gate driving module 103
When the current adjusting circuits 120a to 120n detect that the magnitude of the signal current of the corresponding signal exceeds the predetermined threshold, the current adjusting circuits 120a to 120n limit the corresponding signal current below the predetermined threshold, so as to prevent the gate driving module 103 from bearing an excessive current for a long time. For example, when the magnitude of the first signal current Ihck1 of the first clock signal Vhck1 exceeds a predetermined threshold, the current regulator circuit 120a limits the first signal current Ihck 1. For another example, when the magnitude of the second signal current Ihck2 of the second clock signal Vhck2 exceeds the predetermined threshold, the current adjustment circuit 120b limits the second signal current Ihck2, and so on.
In practice, the current adjusting circuits 120a to 120n may be implemented by a comparator, a switch circuit, a resistance-capacitance circuit (R-C circuit), and a current limiting resistor. For example, when the magnitude of the first signal current Ihck1 exceeds a predetermined threshold, the first signal current Ihck1 charges the rc circuit to a specific voltage. When the comparator receives the specific voltage, the comparator controls the switch circuit to switch the first signal current Ihck1 from the original current path to another current path including a current-limiting resistor, so as to limit the magnitude of the first signal current Ihck 1.
The operation of the current adjusting circuits 120 a-120 n will be further described with reference to fig. 2-4. For brevity of description, the current adjusting circuit 120a will be described as an example. Referring to fig. 2, during the manufacturing or operation of the gate driving module 103, a short circuit may occur between the signal paths of the first clock signal Vhck1 and the second clock signal Vhck2 (i.e., a short circuit path 201 is generated).
If there is no short circuit between the signal paths of the first clock signal Vhck1 and the second clock signal Vhck2 (i.e., there is no short circuit path 201), the waveform of the first signal current Ihck1 is as shown in fig. 3. That is, during each pulse period Tp of the first signal current Ihck1, the absolute value of the magnitude of the first signal current Ihck1 exceeds the predetermined threshold value only during the first period T1 and is lower than the threshold value during the second period T2 and the third period T3.
Since the absolute value of the magnitude of the first signal current Ihck1 is lower than the predetermined threshold value in the second period T2, the current adjustment circuit 120a does not limit the first signal current Ihck 1.
On the other hand, if a short circuit occurs between the signal paths of the first clock signal Vhck1 and the second clock signal Vhck2 (i.e., there is a short circuit path 201), the waveform of the first signal current Ihck1 is as shown in fig. 4. That is, during each pulse period Tp of the first signal current Ihck1, the absolute value of the magnitude of the first signal current Ihck1 exceeds the predetermined threshold value during both the first time period T1 and the second time period T2.
In this case, in the second period T2, if the duration of the absolute value of the first signal current Ihck1 exceeding the predetermined threshold exceeds the predetermined time duration, the current adjustment circuit 120a limits the first signal current Ihck1 in the following third period T3.
In other words, the current adjustment circuit 120a limits the absolute value of the first signal current Ihck1 to be lower than the predetermined threshold value until the pulse time Tp ends. Therefore, when an overcurrent event occurs, the overcurrent protection system 100 can reduce the current magnitude borne by the gate driving module 103 in real time, and reduce the risk of damage to the gate driving module 103.
In addition, each time the current adjustment circuits 120a to 120n limit the corresponding signal current, the current adjustment circuits 120a to 120n notify the logic circuit 130 of the occurrence of an overcurrent event. In a frame of the display area 105, if any one of the current adjusting circuits 120a to 120n notifies the logic circuit 130 of the number of times of the overcurrent event, and the number of times exceeds the preset number of times corresponding to the current adjusting circuit 120, the logic circuit 130 adjusts the statistical value stored in the storage device 140 to accumulate the total number of frames of the overcurrent event.
It is noted that the predetermined number of times that the current adjusting circuits 120a to 120n respectively receive corresponds to the type of the signal received by the current adjusting circuits 120a to 120n respectively. For example, the preset times corresponding to the current regulation circuit 120a for receiving the first clock signal Vhck1, the current regulation circuit 120b for receiving the second clock signal Vhck2, the current regulation circuit 120c for receiving the fixed voltage Vssg, and the current regulation circuit 120n for receiving the start pulse signal Vst are 32 times, 1 time, and 1 time, respectively.
Since the first clock signal Vhck1 has a plurality of periods in each frame and the start pulse signal Vst has only one period in each frame, the predetermined number of times (e.g., 32 times) corresponding to the current adjustment circuit 120a is greater than the predetermined number of times (e.g., 1 time) corresponding to the current adjustment circuit 120 n.
In other words, in a frame of the display area 105, if the total number of cycles of the signal received by a certain current adjusting circuit 120 is larger, the preset number of times corresponding to the certain current adjusting circuit 120 is also larger.
If the logic circuit 130 finds that the statistical value exceeds a predetermined number of frames (for example, 32 frames), the logic circuit 130 determines that the number of frames of the gate driving module 103 with the over-current event is too large. At this time, the logic circuit 130 controls the driving module 110 to stop outputting all the signals transmitted to the gate driving module 103. Thus, accidents during the use of the display panel 101 can be avoided. For example, an electrical fire (electric fire).
In some embodiments, the statistical value represents a total number of consecutive frames in which an overcurrent event occurred. If the logic circuit 130 does not receive the notification from the current adjustment circuits 120a to 120n in a certain frame (i.e., the current adjustment circuits 120a to 120n do not limit the corresponding signal currents), the logic circuit 130 returns the statistical value to zero to recalculate the total number of consecutive frames with the over-current event.
Fig. 5a and 5b together illustrate a simplified flowchart of an over-current protection method 500 according to an embodiment of the invention, in which the over-current protection method 500 is applied to the over-current protection system 100. For brevity of description, the current adjusting circuits 120a and 120b are described below as an example.
In the flow diagrams of fig. 5a and 5b, the flow in the field of a specific device represents the flow performed by the specific device. For example, the flow marked in the "driver module 110" field represents the flow performed by the driver module 110; the flow marked in the "current adjustment circuit 120 a" field represents the flow performed by the current adjustment circuit 120 a.
In a process s502, the driving module 110 outputs the first clock signal Vhck1 and the second clock signal Vhck2 to the current adjusting circuits 120a and 120b, respectively. The current adjustment circuit 120a performs a process s504 to receive the first clock signal Vhck1, and performs a process s506 to determine whether the absolute value of the first signal current Ihck1 of the first clock signal Vhck1 continuously exceeds a predetermined threshold for a predetermined time period.
If the first signal current Ihck1 does not exceed the predetermined threshold value for the predetermined time period, the current adjusting circuit 120a repeats the process s 504. On the other hand, if the first signal current Ihck1 continuously exceeds the predetermined threshold value for the predetermined time period, the current adjustment circuit 120a then executes the process s508 to limit the first signal current Ihck1 until the end of the pulse period of the first signal current Ihck 1. The current adjustment circuit 120a then executes the process s510 to send an over-current event notification to the logic circuit 130.
The current adjusting circuit 120b performs a process s512 to receive the second clock signal Vhck2, and performs a process s514 to determine whether the absolute value of the second signal current Ihck2 of the second clock signal Vhck2 continuously exceeds the predetermined threshold value within the predetermined time period.
If the second signal current Ihck2 does not continuously exceed the predetermined threshold value for the predetermined time period, the current adjusting circuit 120b repeatedly executes the process s 512. On the other hand, if the second signal current Ihck2 continuously exceeds the predetermined threshold value for the predetermined time period, the current adjustment circuit 120b then executes the process s516 to limit the second signal current Ihck2 until the pulse period of the second signal current Ihck2 is over. The current adjusting circuit 120b then executes the process s518 to send an over-current event notification to the logic circuit 130.
Referring to fig. 5b, the logic circuit 130 executes a process s520 to receive the over-current event notification from the current adjusting circuit 120a or 120 b. Next, the logic circuit 130 executes a process s522 to determine whether the number of notifications from the current adjusting circuit 120a exceeds a predetermined number (e.g., 32) of notifications from the current adjusting circuit 120a and whether the number of notifications from the current adjusting circuit 120b exceeds a predetermined number (e.g., 32) of notifications from the current adjusting circuit 120 b.
In one frame, if the number of times of notification from the current adjusting circuit 120a exceeds the preset number of times corresponding to the current adjusting circuit 120a, or the number of times of notification from the current adjusting circuit 120b exceeds the preset number of times corresponding to the current adjusting circuit 120b, the logic circuit 130 then executes the process s524 to adjust the statistical value. Thus, the logic circuit 130 can accumulate the total number of frames with over-current events.
On the other hand, if the number of times of notification from the current adjustment circuit 120a does not exceed the preset number of times corresponding to the current adjustment circuit 120a, and the number of times of notification from the current adjustment circuit 120b does not exceed the preset number of times corresponding to the current adjustment circuit 120b, the logic circuit 130 repeatedly executes the flow s 520.
Next, the logic circuit 130 executes the process s526 to determine whether the statistical value exceeds the predetermined frame number. If so, the logic circuit 130 controls the driving module 110 to execute the process s528, so that the driving module 110 stops outputting all the signals transmitted to the gate driving module 103. If not, the logic circuit 130 repeatedly executes the process s 522.
Please note that, the flow charts shown in FIG. 5a and FIG. 5b are only exemplary embodiments and are not meant to limit the embodiments of the present invention.
For example, the processes s 504-s 510 may be performed simultaneously with the processes s 512-s 518.
For another example, in some embodiments, before executing the process s520, the logic circuit 130 determines whether the current adjusting circuits 120a and 120b do not limit the first signal current Ihck1 and the second signal current Ihck2 in one frame. That is, it is determined whether the gate driving module 103 has no over-current event in one frame. If so, the logic circuit 130 returns the statistical value to zero.
As can be seen from the above description, the overcurrent protection system 100 and the overcurrent protection method 500 can prevent the display panel 101 from being damaged or causing an accident (e.g., a wire fire) due to a large current (e.g., a short-circuit current) flowing for a long time.
Certain terms are used throughout the description and claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the various elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" as used herein includes any direct or indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.
The above are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the protection scope of the appended claims.
Claims (12)
1. An over-current protection system, suitable for a display panel including a gate driving array and a display area, the over-current protection system comprising:
a driving module for providing a first driving signal to the gate driving array;
a first current adjusting circuit coupled between the driving module and the gate driving array, wherein the first current adjusting circuit is located on a current path of a first signal current of the first driving signal;
wherein, during a pulse period of the first signal current, if the absolute value of the magnitude of the first signal current is continuously greater than a predetermined threshold and exceeds a predetermined time duration, the first current adjustment circuit limits the absolute value of the magnitude of the first signal current not to be greater than the predetermined threshold until the pulse period of the first signal current is ended;
a logic circuit for judging whether the number of times that the first current adjusting circuit limits the first signal current exceeds a preset number of times in each frame of picture of the display area;
in each frame, if the first current adjusting circuit limits the first signal current for a number of times greater than the preset number of times, the logic circuit adjusts a statistical value to count the total number of frames with over-current;
when the statistic value is larger than a preset frame number, the logic circuit controls the driving module to stop outputting the first driving signal.
2. The over-current protection system of claim 1, wherein the logic circuit resets the statistic to zero if the first current adjusting circuit does not limit the magnitude of the first signal current in each frame.
3. The system of claim 1, wherein the driving module provides a second driving signal to the gate driving array, the overcurrent protection system further comprising:
a second current adjusting circuit coupled between the driving module and the gate driving array, wherein the second current adjusting circuit is located on a current path of a second signal current of the second driving signal;
wherein, during the pulse period of the second signal current, if the absolute value of the magnitude of the second signal current is continuously larger than the predetermined threshold and exceeds the predetermined time duration, the second current adjustment circuit limits the absolute value of the magnitude of the second signal current not to be larger than the predetermined threshold until the pulse period of the second signal current is finished.
4. The over-current protection system as claimed in claim 3, wherein the logic circuit adjusts the statistic value if the first current adjustment circuit limits the first signal current more than the predetermined number of times or the second current adjustment circuit limits the second signal current more than the predetermined number of times in each frame.
5. The over-current protection system of claim 1, wherein the predetermined number of times corresponds to a total number of cycles of the first driving signal in each frame.
6. The over-current protection system of claim 5, wherein if the first driving signal is a clock signal for sequentially operating a plurality of shift registers in the gate driver array, the predetermined number of times is equal to 32,
if the first driving signal is a start pulse signal for triggering the gate driving array at the beginning of each frame, the predetermined number of times is equal to 1,
if the first driving signal is a fixed voltage, the predetermined number of times is equal to 1.
7. An over-current protection method is suitable for a display panel, the display panel comprises a gate drive array and a display area, the over-current protection method comprises the following steps:
providing a driving module, wherein the driving module is used for providing a first driving signal to the gate driving array;
providing a first current adjusting circuit, wherein the first current adjusting circuit is coupled between the driving module and the gate driving array and is located on a current path of a first signal current of the first driving signal;
during the pulse period of the first signal current, if the absolute value of the magnitude of the first signal current is continuously larger than a preset threshold value and exceeds a preset time length, the absolute value of the magnitude of the first signal current is limited not to be larger than the preset threshold value by using the first current adjusting circuit until the pulse period of the first signal current is ended;
utilizing a logic circuit to judge whether the number of times that the first current adjusting circuit limits the first signal current exceeds a preset number of times in each frame of picture of the display area;
in each frame, if the first current adjusting circuit limits the number of times of the first signal current to be greater than the preset number of times, the logic circuit is used for adjusting a statistical value so as to count the total number of frames with overcurrent;
when the statistic value is larger than a preset frame number, the logic circuit is used for controlling the driving module to stop outputting the first driving signal.
8. The method of claim 7, wherein the adjusting the statistical value by the logic circuit comprises:
in each frame, if the first current adjusting circuit does not limit the first signal current, the logic circuit is used to return the statistic value to zero.
9. The method of claim 7, wherein the driving module provides a second driving signal to the gate driving array, the method further comprising:
providing a second current adjusting circuit, wherein the second current adjusting circuit is coupled between the driving module and the gate driving array and is located on a current path of a second signal current of the second driving signal;
during the pulse period of the second signal current, if the absolute value of the magnitude of the second signal current is continuously larger than the preset threshold value and exceeds the preset time length, the second current adjusting circuit is utilized to limit the absolute value of the magnitude of the second signal current not to be larger than the preset threshold value until the pulse period of the second signal current is ended.
10. The method of claim 9, wherein the process of adjusting the statistical value by the logic circuit further comprises:
in each frame, if the number of times that the first current adjusting circuit limits the first signal current is greater than the preset number of times, or the number of times that the second current adjusting circuit limits the second signal current is greater than the preset number of times, the logic circuit adjusts the statistic value.
11. The method of claim 7, wherein the predetermined number of times corresponds to a total number of cycles of the first driving signal in each frame.
12. The method of claim 11, wherein if the first driving signal is a clock signal for sequentially operating a plurality of shift registers in the gate driver array, the predetermined number of times is equal to 32,
if the first driving signal is a start pulse signal for triggering the gate driving array at the beginning of each frame, the predetermined number of times is equal to 1,
if the first driving signal is a fixed voltage, the predetermined number of times is equal to 1.
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| Application Number | Priority Date | Filing Date | Title |
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| TW107105655A TWI668932B (en) | 2018-02-14 | 2018-02-14 | Over current protection system and over current protection method |
| TW107105655 | 2018-02-14 |
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| CN108682376B true CN108682376B (en) | 2021-08-20 |
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| TWI630591B (en) * | 2017-05-11 | 2018-07-21 | 友達光電股份有限公司 | Displaying device and protecting circuit thereof |
| CN107393491B (en) * | 2017-07-18 | 2018-08-14 | 深圳市华星光电半导体显示技术有限公司 | Clock signal output circuit and liquid crystal display device |
-
2018
- 2018-02-14 TW TW107105655A patent/TWI668932B/en active
- 2018-05-15 CN CN201810463410.8A patent/CN108682376B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN108682376A (en) | 2018-10-19 |
| TW201935795A (en) | 2019-09-01 |
| TWI668932B (en) | 2019-08-11 |
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