CN108681445B - P L C program design method based on time automaton - Google Patents
P L C program design method based on time automaton Download PDFInfo
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Abstract
The invention discloses a P L C program design method based on a time automaton, which comprises the steps of dividing an industrial control system into a plurality of subsystems according to application requirements of the industrial control system, constructing a time automaton model for each subsystem, instantiating each constructed time automaton model to generate a corresponding process, simulating and verifying the generated process, converting each time automaton into a corresponding SFC language function block to obtain a plurality of SFC function blocks and a P L C project containing the SFC function blocks, and correspondingly converting variable declarations, states, transfer edges, synchronization and system declarations in the time automaton into a P L C program according to a designed conversion rule to obtain a complete P L C program which meets IEC61131-3 standards.
Description
Technical Field
The invention belongs to the technical field of Programmable Controller software, and particularly relates to a P L C (Programmable L organic Controller) program design method based on a time automaton.
Background
The IEC61131 standard programming language defines three graphical programming languages including a ladder Diagram (L D, L adapter L g, graphical programming L), a Function Block Diagram (FBD, Function Block Diagram) and a Sequential Function Diagram (SFC, Sequential Function Chart) so that program instructions are visualized, but the logic relationship among abstract program instructions, especially the complexity of the structure of the industrial control system is increased in recent years, the number of states of the control system is huge, which results in that the workload of the P L C program design is cumbersome, the development period and the cost of the program control are complicated, and the program control system is difficult to detect errors of the logic relationship among abstract program instructions, especially the complexity of the structure of the industrial control system is increased, the program control system is difficult to detect errors of the program sequences, and the like, and the program control system is difficult to detect errors of the program sequences, such as errors of the program sequences, and the like, and the debugging of the program sequences are difficult to detect all errors of the program sequences, such as errors of the program sequences, the debugging software is difficult to detect, and the errors of the program sequences are difficult to detect and the errors of the related errors of the program sequences of the program control system are difficult to detect.
Disclosure of Invention
Aiming at the defects and improvement requirements of the prior art, the invention provides a P L C program design method based on a time automaton, and aims to solve the problems of complex programming workload and difficult checking of application program logic errors caused by large state number in the P L C program design process of a complex industrial control system.
In order to achieve the above object, the present invention provides a P L C programming method based on a time automaton, comprising the following steps:
(1) dividing the industrial control system into a plurality of subsystems according to the application requirement of the industrial control system, and constructing a time automaton model for each subsystem;
(2) instantiating each constructed time automaton model to generate a corresponding process, and then simulating and verifying the generated process to avoid program logic errors;
(3) converting each time automaton into a corresponding Sequential Function Chart (SFC) language function block to obtain a plurality of SFC function blocks and a P L C project containing the SFC function blocks;
(4) converting the global variable statement of the time automaton into a global variable of a P L C project, converting the local variable statement of the time automaton into a local variable of a corresponding SFC function block, and converting the parameter of the time automaton into an input variable of the corresponding SFC function block, thereby completing the conversion of the variable statement of the time automaton;
(5) converting the state of the time automaton into the corresponding SFC function block, converting the constraint condition on the transfer side of the time automaton into the transfer condition of the corresponding SFC function block, and converting the variable resetting and updating on the transfer side of the time automaton into the action block of the corresponding SFC function block, thereby completing the conversion of the state of the time automaton and the transfer side;
(6) converting the synchronous channel between the time automata into a synchronous mechanism between the corresponding SFC functional blocks, thereby completing the synchronous conversion of the time automata;
(7) and converting the instantiation process of the time automaton into P L C main program instantiation calling each corresponding SFC function block, thereby completing the conversion of the system declaration of the time automaton.
Further, in the step (1), a time automaton model is constructed for each subsystem, and the method comprises the following steps:
(11) determining possible existing states of the time automaton of each subsystem, and determining an initial state and the type of each state; the types of states include: a normal state, an urgent state, and a constrained state; the normal state allows time to stay; the urgent state does not allow a lapse of time to occur; the constraint state does not allow the time to pass, and requires that the transition of the state occurs immediately, and simultaneously requires that no transition occurs in other states except the constraint state;
(12) analyzing the logic relation among the states, determining the transition edges of the states and the constraint conditions on the edges, and resetting and updating variables to be executed; the variable resetting and updating refers to resetting of a clock variable, updating of a numerical variable value and calling of a function;
(13) analyzing the behavior cooperativity among all subsystems, determining transfer edges needing to be synchronized among the time automata, and adding a synchronization channel; the synchronous channel is composed of a channel signal transmitting side ("|) and a channel signal receiving side (".
Further, in the step (2), the simulation and verification of the process generated by the time automata model means that a simulator is used for simulating the time automata model of the system, the correctness of the system model is preliminarily judged, the BNF grammar is used for performing formal and standard verification on the system model in the verifier, the correctness of the application logic of the system is verified, and the logic errors of programs such as unreachability, insecurity, logic conflict and deadlock are avoided.
Furthermore, in step (4), if the variable to be converted is declared as a clock variable, the TON timer function block is called in the P L C project, and the output ET is used as the conversion result, if the variable to be converted is declared as a function with an input parameter and without using an external variable declaration, the variable to be converted is converted into a function programmed in ST language in the P L C project, if the variable to be converted is declared as a function with an input parameter and with an external variable declaration, the variable to be converted is converted into a function programmed in ST language in the P L C project, if the variable to be converted is declared as a function without an input parameter, the variable to be converted is converted into the action of the corresponding SFC function block, and if the variable to be converted is declared as a synchronous channel variable, the step (6) is carried out.
Further, in step (5), if the state to be converted is the emergency state or the constraint state, the step elapsed time of the step in the corresponding SFC function block is set to 0.
Furthermore, in step (5), if multiple transition edges in the time automaton are converged into one state, that is, there is a case where multiple subsequences in the time automaton are converged, for this case, the variable reset and update on the multiple transition edges cannot be directly translated into an action block connected to the next step of the SFC function block, so that an auxiliary step and a transition condition with a boolean value of constant 1 are inserted after each transition condition in the corresponding SFC function block.
Further, in the step (5), the variable resetting and updating on the transfer edge of the time automaton are converted into the action block of the corresponding SFC function block, specifically, the clock variable resetting expression, the numerical variable assignment expression and the function on the transfer edge of the time automaton are converted into the action block of the SFC function block corresponding to the transfer edge and connected in the next step, and then the clock variable resetting expression is converted into the action block to call the TON timer function block and reset.
Furthermore, in the step (5), if there is a state evolution process loop in the time automaton, that is, the entire process starts to evolve from the initial state, and finally returns to the initial state to implement a periodic loop, and an internal loop in which a certain state in the process returns to the original state after several transitions; since the directed links in the SFC cannot cross or go up, for this case, the next step is specified in the corresponding SFC functional block using the jump symbol.
Further, in the step (6), converting the synchronization channel between the time automata into a synchronization mechanism between the corresponding SFC function blocks specifically includes the following operations:
the method comprises the steps of creating a channel signal sending function block chan _ P and a channel signal receiving function module chan _ V in a P L C project, and declaring Boolean-type condition variables POK and VOK, wherein the condition variables POK are true to represent the execution completion of an operation primitive of the channel signal sending function block chan _ P, and the condition variables VOK are true to represent the execution completion of the operation primitive of the channel signal receiving function module chan _ V, inserting a signal sending step and a transfer condition with Boolean value POK behind the transfer condition between two steps in a corresponding SFC if a channel signal sender exists on a transfer edge between the two states in a time automaton, and calling the channel signal sending function block chan _ P in an action block connected with the signal sending step, and calling the channel signal receiving function module chan _ V in an action block connected with a preceding step in a corresponding SFC function block if a channel signal receiver exists on the transfer edge between the two states in the time automaton, and combining the corresponding transfer conditions with the Boolean value VOK.
Further, in step (7), the execution sequence of each SFC function block when the P L C main program instantiates and calls each SFC function block is consistent with the priority sequence between the instantiation processes of the time automaton set by the system.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
(1) according to the P L C program design method based on the time automata, after the time automata model of each subsystem is constructed and the instantiation process of the time automata model is simulated and verified, detailed and complete conversion rules from the time automata model to the P L C program are designed, including conversion of variable statements of the time automata, conversion of states and transfer edges, synchronous conversion and conversion of system statements, so that the designed P L C program meets the IEC61131-3 standard, and conversion from a formal model of a complex industrial control system to a complete P L C program can be achieved.
(2) The P L C program design method based on the time automaton, provided by the invention, utilizes the time automaton to model each subsystem, describes the control algorithm of a complex system in an automaton graphic mode, has a good structure, is vivid and visual in program instruction logic relation, and can simplify programming work and shorten project development period compared with the traditional P L C program design method.
(3) According to the P L C program design method based on the time automata, after the time automata is used for modeling each subsystem, the instantiation process of the time automata model can be simulated and verified, so that the formal verification is performed on the application logic of the system, the problems that the traditional P L C programming can only detect grammatical errors and cannot check program logic errors are solved, the correctness of the application logic of the system model is ensured, inaccessible sequences, unsafe sequences, logic conflicts, deadlocks and the like in the program are avoided, and the method has higher correctness and reliability compared with the traditional P L C programming method.
Drawings
Fig. 1 is a flowchart of a P L C programming method based on a time automaton according to an embodiment of the present invention;
FIG. 2 is a time robot model of a train subsystem provided by an embodiment of the present invention;
FIG. 3 is a time robot model of a bridge subsystem provided by an embodiment of the present invention;
FIG. 4 is a simulation of a railway control system time automaton model provided by an embodiment of the present invention; (a) simulating a model of the time robot for the first train subsystem; (b) simulation of a time automaton model for a second train subsystem; (c) simulation of a time automaton model for a third train subsystem; (d) simulating a time automaton model of a bridge subsystem;
FIG. 5 is a list of railway control system property verifications provided by embodiments of the present invention;
FIG. 6 is a diagram of a verification result of the properties of a railway control system provided by an embodiment of the present invention;
FIG. 7 is a schematic diagram of SFC function blocks converted from train subsystem time automata model provided by the embodiment of the invention;
FIG. 8 is a schematic diagram of SFC function blocks converted from a time automaton model of a bridge subsystem according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a P L C program instantiating a calling SFC function block provided by the embodiment of the invention, (a) - (C) are schematic diagrams of a P L C program instantiating a calling SFC function block "Train; (d) are schematic diagrams of a P L C program instantiating a calling SFC function block" Bridge ";
FIG. 10 is a flow chart of synchronization signal execution according to an embodiment of the present invention; (a) executing the flow for the operation primitive of the channel signal sending function block; (b) executing the flow for the operation primitive of the channel signal receiving function block;
FIG. 11 is a synchronization signal slew rate process according to an embodiment of the present invention; (a) switching to the sender of the synchronization signal; (b) for the switching of the receiver of the synchronization signal.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Before describing the technical scheme of the invention in detail, firstly, a railway control system which is designed by the P L C program of the invention is briefly introduced, the railway control system controls the right of three trains to a bridge, the bridge is a key shared resource, only one train can pass through at any time, the train cannot be stopped or started immediately, the stopping and starting process requires time, therefore, when the train approaches the bridge, the train sends an approach signal to the bridge, within 10 seconds after the approach signal is sent, if a stop signal of the bridge is received, the bridge is occupied by other trains, the train is safely stopped before approaching the bridge, until the previous train leaves the bridge, the bridge sends a start signal, the train is restarted, the starting time is 7 seconds, then the bridge passes through the bridge, the leaving signal passes through the bridge, the time is 3 seconds after the approach signal is sent, if a stop signal of the bridge is not received, the bridge is not occupied, the train does not need to stop, the bridge directly passes through the bridge, the P L C program of the invention is designed based on the description of the P control system, and the invention is provided by an example L.
The invention provides a time-based automatic P L C programming method, as shown in FIG. 1, comprising the following steps:
(1) dividing the industrial control system into a plurality of subsystems according to the application requirement of the industrial control system, and constructing a time automaton model for each subsystem;
the railway control system is divided into two parts of a Train and a Bridge, namely a Train subsystem and a Bridge subsystem, and respectively creates a time automaton 'Train' and 'Bridge';
respectively constructing a time automaton model for the two subsystems, comprising the following steps:
(11) determining the state of each subsystem time automaton;
the time automaton "Train" includes Train _ Safe, Train _ Appr, Train _ Stop, Train _ Start, Train _ Cross, for a total of 5 states, as shown in FIG. 2; train _ Safe is an initial state, indicating that the Train has not yet approached the bridge; train _ apr indicates that the Train has approached the bridge and has sent a proximity signal to the bridge; train _ Stop means that the Train stops after receiving the Stop signal; train _ Start indicates that the Train restarts after receiving a starting signal; train Cross indicates that the Train is passing through the bridge;
the time automaton "Bridge" includes Bridge _ Free, Bridge _ Occ, Bridge _ Add, Bridge _ Stop, Bridge _ Remove, Bridge _ Go, for a total of 6 states, as shown in fig. 3; bridge _ Free is an initial state, indicating that the Bridge is not occupied; bridge _ Occ indicates that the train is passing through the Bridge; the Bridge is in Bridge Occ state, if there are other trains approaching at this time, the Bridge will record its id in Bridge Add state and join the queue, and then send out Stop signal in Bridge Stop state, state Bridge Add and state Bridge Stop do not allow time lapse; bridge _ Remove means that after the train passes through the Bridge, the id of the train is removed from the queue, and the state does not allow the time to pass; bridge _ Go indicates that the Bridge is issuing a start signal, a state that does not allow time to elapse;
(12) adding branch edges, constraint conditions, variable resetting and updating;
in the automatic time machine "Train", Train _ Safe is transferred to Train _ Appr; the Train _ Appr can be transferred to a Train _ Stop or a Train _ Cross, and is determined by constraint conditions; the Train _ Stop transition to Train _ Start; transition from Train _ Start to Train _ Cross; train _ Cross is transferred to Train _ Safe as shown in FIG. 2; where 'x-0' represents a clock variable x reset;
in the time automaton "Bridge", Bridge _ Free can be transferred to Bridge _ Occ, also to Bridge _ Go, depending on the constraints; bridge _ Occ can be transferred to Bridge _ Add or to Bridge _ Remove; bridge _ Add to Bridge _ Stop; bridge _ Stop transfer to Bridge _ Occ; bridge _ Remove to Bridge _ Free; bridge _ Go to Bridge _ Occ, as shown in fig. 3; wherein 'enqueue (ee)', 'dequeue ()', 'tail ()', and 'front ()' all represent the calling of functions;
fourthly, adding a synchronous channel;
in the time automaton "Train" shown in figure 2, Train _ Safe is transferred to Train _ Appr, the Train issues a proximity signal' apr! ', the time automaton "Bridge" shown in fig. 3, Bridge _ Free is transferred to Bridge _ Occ and Bridge _ Occ is transferred to Bridge _ Add, on both transfer sides the Bridge can receive the approach signal' appr? '; within the time automaton "Train", Train _ Cross is transferred to Train _ Safe, the Train issues a leave signal' leave! ', in the time automaton "Bridge", Bridge _ Occ transferred to Bridge _ Remove, did the Bridge receive the leave signal' leave? '; within the time automaton "Bridge", the Bridge _ Stop is transferred to Bridge _ Occ, and the Bridge issues a Stop signal' Stop! 'in the time automaton "Train", Train _ appl is transferred to Train _ Stop, is the Train receive Stop signal' Stop? '; within the time automaton "Bridge", Bridge _ Go is transferred to Bridge _ Occ, and the Bridge issues an initiation signal' Go! 'in the time automaton "Train", the Train _ Stop transitions to Train _ Start, does the Train receive the Start signal' go? ';
(2) instantiating each constructed time automaton model to generate a corresponding process, and then simulating and verifying the generated process to avoid program logic errors;
the method specifically comprises the following operations: in the software simulator, a time automatic machine model of the railway control system is simulated, the correctness of the system model is preliminarily judged, as shown in fig. 4, the "train _ 1" is passing through the Bridge, the "train _ 3" is in a stop state, the "train _ 2" is close to the Bridge, the "Bridge" sends out a stop signal, and the "train _ 2" receives the stop signal.
Formalized specification verification is carried out on the system model in a verifier by utilizing a BNF grammar, and a system property list is shown in FIG. 5, wherein A [ ] not decode lock, security verification shows that the system cannot be deadlocked; e < > Train _1.Train _ Cross ═ 1, reachability verification, meaning that "Train _ 1" Train is passing through the bridge; e < > Train _2.Train _ Cross ═ 1, reachability verification, meaning that "Train _ 2" Train is traversing the bridge; e < > Train _3.Train _ Cross ═ 1, reachability verification, meaning that "Train _ 3" Train is passing through the bridge; a [ ] Train _1.Train _ Cross + Train _2.Train _ Cross + Train _3.Train _ Cross < ═ 1, safety verification, meaning that three trains "Train _ 1", "Train _ 2", and "Train _ 3" can only allow one Train to pass through the bridge at any time, i.e. two trains or three trains are not allowed to pass through the bridge at the same time; e < > Train _1.Train _ Cross & & Train _2.Train _ Stop, reachability verification, indicating that there is a case where "Train _ 1" is passing through the bridge and "Train _ 2" is in a Stop state;
the corresponding verification results are shown in fig. 6;
(3) converting each time automaton into a corresponding Sequential Function Chart (SFC) language function block to obtain a plurality of SFC function blocks and a P L C project containing the SFC function blocks;
for the time automaton "Train", the SFC function block "Train" is created, as shown in fig. 7; for the time automaton "Bridge", the SFC function block "Bridge" is created, as shown in fig. 8;
(4) converting the global variable statement of the time automaton into a global variable of a P L C project, converting the local variable statement of the time automaton into a local variable of a corresponding SFC function block, and converting the parameter of the time automaton into an input variable of the corresponding SFC function block, thereby completing the conversion of the variable statement of the time automaton;
the global declaration of the system model is converted into global variables of the P L C engineering, the local declaration of the time automaton "Train" is converted into local variables of the SFC function block "Train", the time automaton "Bridge" has no local declaration, the parameter 'id' of the time automaton "Train" is converted into the input variable 'id' of the SFC function block "Train", the time automaton "Bridge" has no parameter, the clock variable 'x' of the time automaton "Train", the type of declaration of the variable 'x' in the SFC function block "Train" calls the TON timer function block, replacing the clock variable 'x' with 'x.et';
the function defined in the time automaton, which has input parameters and uses the external variable declaration, is translated into the function block programmed by ST language in P L C engineering, the function ' enqueue ' defined in the embodiment '
Translating into an ST function block 'issue' in P L C engineering, translating a function without an input parameter into an action of an SFC function block, and translating functions 'issue', 'front', 'tail' into ST actions 'issue', 'front', 'tail';
(5) converting the state of the time automaton into the corresponding SFC function block, converting the constraint condition on the transfer side of the time automaton into the transfer condition of the corresponding SFC function block, and converting the variable resetting and updating on the transfer side of the time automaton into the action block of the corresponding SFC function block, thereby completing the conversion of the state of the time automaton and the transfer side;
for states of the time automaton "Train _ Safe, Train _ Appr, Train _ Stop, Train _ Start, and Train _ Cross, 5 corresponding steps of Train _ Safe, Train _ Appr, Train _ Stop, Train _ Start, and Train _ Cross are created in the SFC function block" Train ", and the initial state of Train _ Safe corresponds to the initial step of Train _ Safe, as shown in FIG. 7; for the states of the time automaton "Bridge _ Free, Bridge _ oc, Bridge _ Add, Bridge _ Stop, Bridge _ Remove, Bridge _ Go, 6 corresponding steps Bridge _ Free, Bridge _ oc, Bridge _ Add, Bridge _ Stop, Bridge _ Remove, Bridge _ Go are created in the SFC function block" Bridge ", the initial state Bridge _ Free corresponding to the initial step Bridge _ Free, as shown in fig. 8;
the constraint conditions on the transition edge of the time automaton "Train" are converted into the transition conditions corresponding to the interior of the SFC function block "Train", as shown in fig. 7; the constraint conditions on the transfer edge of the time automaton "Bridge" are converted into transfer conditions inside the corresponding SFC function block "Bridge", as shown in fig. 8; the states of the time automaton "Bridge _ Add, Bridge _ Stop, Bridge _ Remove, and Bridge _ Go are all constraint states, and no time is allowed to elapse, and in the SFC function block" Bridge ", the step elapsed times of steps Bridge _ Add, Bridge _ Stop, Bridge _ Remove, and Bridge _ Go are 0, and" Bridge _ add.t > T #0s "," Bridge _ stop.t > T #0s ", and" Bridge _ go.t > T #0s "are respectively taken in the transition conditions following the steps, as shown in fig. 8;
FIG. 2 is a diagram in which the "Train" state Train _ Appr and the "Train _ Start" state converge to the "Train _ Cross" state, and an auxiliary Step Train _ Step0 is inserted after the SFC function block "Train" corresponding to the transition condition, the transition condition being Boolean 1, the auxiliary Step Train _ Step1, the transition condition being Boolean 1, as shown in FIG. 7; fig. 3 shows that the time automaton "Bridge" state Bridge _ Go and the state Bridge _ Free converge to the state Bridge _ Occ, in the SFC block "Bridge" a subsidiary Step Bridge _ Step0 is inserted after the corresponding transfer condition, with a boolean value of 1 and a subsidiary Step Bridge _ Step1, with a boolean value of 1, as shown in fig. 8;
translating a clock variable resetting expression, a numerical variable assignment expression and a function on the transfer edge of the time automaton into an action block which is connected with the next step of the transfer edge and corresponds to the SFC function block; the clock variable reset expression ' x ═ 0 ' IN fig. 2 translates into action block ' x (IN: ═ 0); x (IN: ═ 1)', as shown IN fig. 7;
a state evolution flow loop exists in the time automaton "Train", that is, the state Train _ Cross in fig. 2 is transferred to the initial state Train _ Safe, the directed connection lines in the SFC cannot be crossed or go up, and the corresponding transfer edge in the SFC function block "Train" uses a jump symbol to designate the next step Train _ Safe, as shown in fig. 7; the existence state Bridge _ Remove in the time automaton "Bridge" of fig. 3 is transferred to the initial state Bridge _ Free, the corresponding transfer edge in the SFC function "Bridge" specifies the post-stage Bridge _ Free using a jump symbol, as shown in fig. 8; there is an internal loop in the time automaton "Bridge" of fig. 3, the state Bridge _ Stop is transferred to the state Bridge _ Occ, the corresponding transfer edge in the SFC function "Bridge" specifies the post-step Bridge _ Occ using the jump sign, as shown in fig. 8;
(6) converting the synchronous channel between the time automata into a synchronous mechanism between the corresponding SFC functional blocks, thereby completing the synchronous conversion of the time automata;
creating a channel signal sending function block chan _ P representing "|" and a channel signal receiving function block chan _ V representing ";
the time automaton "Train" in FIG. 2 has a synchronous send signal' apr! 'and' leave! ' after the corresponding transition condition in the SFC function block "Train", a signaling step Send _ apr and a transition step apr _ p.pok, a signaling step Send _ leave and a transition condition leave _ p.pok are inserted respectively, an aprr _ P instantiation call function block chan _ P in the action block connected by step Send _ apr, and a leave _ P instantiation call function block chan _ P in the action block connected by step Send _ leave, as shown in fig. 7; is there a synchronous received signal 'stop' within the time automaton 'Train' of fig. 2? 'and' go? ' in the SFC function block "Train", a Stop _ V instantiates a call function block chan _ V, a transfer condition conjunctive Stop _ v.vok in an action block corresponding to a transfer condition previous step Train _ apr connection, a go _ V instantiates a call function block chan _ V, a transfer condition conjunctive go _ v.vok in an action of a previous step Train _ Stop connection, as shown in fig. 7;
the presence of a synchronous transmission signal ' stop!in the time automaton ' Bridge ' of figure 3! 'and' go! ' inserting a signaling step Send _ stop and a transfer stop _ p.POK, a signaling step Send _ go and a transfer condition go _ p.POK respectively after the corresponding transfer condition in the SFC function block ' Bridge ', instantiating a calling function block chan _ P in the step Send _ stop connected action block, and instantiating a calling function block chan _ P in go _ go connected action block, as shown in FIG. 8; is there a synchronous received signal 'appr' in the time automaton 'Bridge' of fig. 3? 'and' leave? ' in the SFC function block "Bridge", apr _ V instantiates the calling function block chan _ V, the branch condition conjuncts apr _ v.vok in the action block corresponding to the branch condition preceding step Bridge _ Free connection, apr _ V instantiates the calling function block chan _ V, the leave _ V instantiates the calling function block chan _ V, the branch condition conjuncts apr _ v.vok and leave _ v.vok, respectively, in the action block corresponding to the preceding step Bridge _ Free connection in the preceding step Bridge _ Occ connection, as shown in fig. 8;
(7) converting the instantiation process of the time automaton into a P L C main program, and instantiating and calling each corresponding SFC function block, thereby completing the conversion of the system declaration of the time automaton;
the railway control system instantiates 'Train _1 ═ Train (1)', Train _2 ═ Train (2) ', Train _3 ═ Train (3)', Bridge _0 ═ Bridge () ', system Train _1, Train _2, Train _3, Bridge _ 0;' in the P L C main program, the function blocks Train _1, Train _2, Train _3 instantiate call SFC function block 'Train', the function block Bridge _0 instantiates call SFC function block 'Bridge', as shown in fig. 9;
the time automaton model of the system sets the priorities between processes with the symbol "<", and the function block execution order priorities are set correspondingly in the P L C project.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A P L C programming method based on a time automaton is characterized by comprising the following steps:
(1) dividing the industrial control system into a plurality of subsystems according to the application requirement of the industrial control system, and constructing a time automaton model for each subsystem;
(2) instantiating each constructed time automaton model to generate a corresponding process, and then simulating and verifying the generated process to avoid program logic errors;
(3) converting each time automaton into a corresponding SFC language function block to obtain a plurality of SFC function blocks and a P L C project containing the SFC function blocks;
(4) converting the global variable statement of the time automaton into a global variable of a P L C project, converting the local variable statement of the time automaton into a local variable of a corresponding SFC function block, and converting the parameter of the time automaton into an input variable of the corresponding SFC function block, thereby completing the conversion of the variable statement of the time automaton;
(5) converting the state of the time automaton into the corresponding SFC function block, converting the constraint condition on the transfer side of the time automaton into the transfer condition of the corresponding SFC function block, and converting the variable resetting and updating on the transfer side of the time automaton into the action block of the corresponding SFC function block, thereby completing the conversion of the state of the time automaton and the transfer side;
(6) converting the synchronous channel between the time automata into a synchronous mechanism between the corresponding SFC functional blocks, thereby completing the synchronous conversion of the time automata;
in the step (6), converting the synchronization channel between the time automata into the synchronization mechanism between the corresponding SFC function blocks specifically includes the following operations:
creating a channel signal sending function block chan _ P and a channel signal receiving function module chan _ V in a P L C project, and declaring Boolean type condition variables POK and VOK, wherein the condition variables POK are true to represent the execution completion of an operation primitive of the channel signal sending function block chan _ P, and the condition variables VOK are true to represent the execution completion of the operation primitive of the channel signal receiving function module chan _ V;
(7) and converting the instantiation process of the time automaton into P L C main program instantiation calling each corresponding SFC function block, thereby completing the conversion of the system declaration of the time automaton.
2. The method as claimed in claim 1, wherein in the step (4), if the variable to be converted is declared as a clock variable, the TON timer function block is called in the P L C project and the output ET is used as the conversion result, if the variable to be converted is declared as a function with input parameters and without using external variable declarations, the function is converted into a function programmed in ST language in the P L C project, if the variable to be converted is declared as a function with input parameters and with external variable declarations, the function is converted into a function programmed in ST language in the P L C project, if the variable to be converted is declared as a function without input parameters, the function is converted into the corresponding SFC function block, and if the variable to be converted is a synchronous channel variable, the step (6) is proceeded.
3. The method of P L C programming based on temporal automata according to claim 1, wherein in the step (5), if the state to be converted is an emergency state or a constraint state, a step elapsed time of the step in the corresponding SFC function block is set to 0.
4. The method of claim 1, wherein in the step (5), if a plurality of transition edges in the time automaton are collected into one state, an auxiliary step and a transition condition with a Boolean constant of 1 are inserted after each transition condition in the corresponding SFC function block.
5. The method for P L C programming based on time automata according to claim 1, wherein in step (5), the variable reset and update on the transition edge of the time automata is converted into the action block of the corresponding SFC function block, specifically, the clock variable reset expression, the numerical variable assignment expression and the function on the transition edge of the time automata are converted into the action block of the SFC function block corresponding to the post-step connection of the transition edge, and then the clock variable reset expression is converted into the action block calling the TON timer function block and reset.
6. The method of claim 1, wherein in the step (5), if there is a state evolution flow loop in the temporal automaton, a subsequent step is designated using a jump symbol in a corresponding SFC function block.
7. The method for P L C programming based on temporal automata according to claim 1, wherein in the step (7), the execution sequence of each SFC function block when the P L C main program instantiates and calls each SFC function block is consistent with the priority sequence between the instantiation processes of the temporal automata set by the system.
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