CN108666278A - Semiconductor package part - Google Patents
Semiconductor package part Download PDFInfo
- Publication number
- CN108666278A CN108666278A CN201710196958.6A CN201710196958A CN108666278A CN 108666278 A CN108666278 A CN 108666278A CN 201710196958 A CN201710196958 A CN 201710196958A CN 108666278 A CN108666278 A CN 108666278A
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- China
- Prior art keywords
- crystal grain
- semiconductor package
- size
- encapsulated
- package part
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000013078 crystal Substances 0.000 claims abstract description 201
- 239000000758 substrate Substances 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 23
- 239000004642 Polyimide Substances 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 8
- 229920000647 polyepoxide Polymers 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- 229920000642 polymer Polymers 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 229910000831 Steel Inorganic materials 0.000 claims description 3
- 239000010959 steel Substances 0.000 claims description 3
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 description 48
- 238000012545 processing Methods 0.000 description 30
- 238000004806 packaging method and process Methods 0.000 description 27
- 235000012431 wafers Nutrition 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 19
- 239000000084 colloidal system Substances 0.000 description 15
- 230000000694 effects Effects 0.000 description 15
- 238000012856 packing Methods 0.000 description 13
- 239000004020 conductor Substances 0.000 description 12
- 238000005538 encapsulation Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229920000297 Rayon Polymers 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010422 painting Methods 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- HBGPNLPABVUVKZ-POTXQNELSA-N (1r,3as,4s,5ar,5br,7r,7ar,11ar,11br,13as,13br)-4,7-dihydroxy-3a,5a,5b,8,8,11a-hexamethyl-1-prop-1-en-2-yl-2,3,4,5,6,7,7a,10,11,11b,12,13,13a,13b-tetradecahydro-1h-cyclopenta[a]chrysen-9-one Chemical compound C([C@@]12C)CC(=O)C(C)(C)[C@@H]1[C@H](O)C[C@]([C@]1(C)C[C@@H]3O)(C)[C@@H]2CC[C@H]1[C@@H]1[C@]3(C)CC[C@H]1C(=C)C HBGPNLPABVUVKZ-POTXQNELSA-N 0.000 description 1
- PFRGGOIBYLYVKM-UHFFFAOYSA-N 15alpha-hydroxylup-20(29)-en-3-one Natural products CC(=C)C1CCC2(C)CC(O)C3(C)C(CCC4C5(C)CCC(=O)C(C)(C)C5CCC34C)C12 PFRGGOIBYLYVKM-UHFFFAOYSA-N 0.000 description 1
- 241000208340 Araliaceae Species 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- SOKRNBGSNZXYIO-UHFFFAOYSA-N Resinone Natural products CC(=C)C1CCC2(C)C(O)CC3(C)C(CCC4C5(C)CCC(=O)C(C)(C)C5CCC34C)C12 SOKRNBGSNZXYIO-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A kind of semiconductor package part has size equivalent or more than a standard size 0201.The semiconductor package part includes a crystal grain, has the size of the half less than the standard size 0201；And one be encapsulated part, is encapsulated the crystal grain.
Description
Technical field
Disclosed embodiment of this invention is related to a kind of semiconductor package part, more particularly to a kind of includes being less than a gauge
The semiconductor package part of very little crystal grain.
Background technology
With flourishing for electronic industry, electronic product also progresses into multi-functional, high performance R＆D direction.It is full
The sufficient high integration of semiconductor package part (integration) and the encapsulation requirement that (miniaturization) is miniaturized, provide
The circuit board of most active or passive elements and connection, also gradually evolves into multi-layer board, so that limited by lamina
Under space, by interlayer interconnection technique (interlayer connection) expand circuit board on available layout area by
Coordinate integrated circuit (integrated circuit) demand of high electron density.
This " discussion of background technology " chapters and sections is only to provide background technology data.It is old in this " discussion of background technology "
It states it is not an admission that the target disclosed in this " background technology " chapters and sections constitutes the prior art of the disclosure, and this " background technology " chapter
It saves no any part to be used as recognizing any part of present application, including this " background technology " chapters and sections, constitutes this public affairs
The prior art opened.
Invention content
In an embodiment of the disclosure, a kind of semiconductor package part is provided.The semiconductor package part has equivalent or big
In the size of a standard size 0201.The semiconductor package part includes a crystal grain, has two points less than the standard size 0201
One of size；And one be encapsulated part, is encapsulated the crystal grain.
In an embodiment of the disclosure, which further includes one first conductive pad, is located on the crystal grain, is used
To be electrically connected the crystal grain, and it is in direct contact the crystal grain；And one second conductive pad, it is located on the crystal grain, is for electrically connecting to
The crystal grain, and be in direct contact the crystal grain, wherein this be encapsulated a part for part to by first conductive pad it is electrically isolated this second
Conductive pad.
In an embodiment of the disclosure, this is encapsulated part around first conductive pad and second conductive pad, this is encapsulated part
A part be located between first conductive pad and second conductive pad.
In an embodiment of the disclosure, which further includes a first electrode, this be encapsulated part and this
On one conductive pad, and it is electrically connected with first conductive pad；And a second electrode, part and second conductive pad are encapsulated at this
On, and be electrically connected with second conductive pad.
In an embodiment of the disclosure, the size of the crystal grain is standard size 01005.
In an embodiment of the disclosure, the size of the semiconductor package part is equivalent or is more than a standard size 0402 and one
One of standard size DFN 10.
In an embodiment of the disclosure, which includes polyimides (polyimide), epoxy resin
One of (epoxy resin), benzocyclobutane olefine resin (BCB) or high molecular polymer (polymer).
In an embodiment of the disclosure, which further includes a substrate.This is encapsulated part and the crystal grain is located at
It is contacted on the substrate and with the substrate.
In an embodiment of the disclosure, the material of the substrate includes glass, printed circuit board (printed circuit
Board, PCB), stainless steel or high molecular one.
In an embodiment of the disclosure, which includes one of a conducting carrier plate and a non-conductive support plate.
In an embodiment of the disclosure, which includes a printed circuit board (printed circuit
Board, PCB).
In an embodiment of the disclosure, which is one first crystal grain.The semiconductor package part further includes one second crystalline substance
Grain.This is encapsulated part and is encapsulated second crystal grain, and first crystal grain and second crystal grain are separated
In the disclosure, the structure of the semiconductor package part of the disclosure can reflect that the semiconductor package part passes through one kind
The method of special manufacture semiconductor package part completes.Specifically, even if the size of desired packaging part is gauge
Very little 0201, or more than the standard size 0402 and DFN 10 of standard size 0201, pass through the special manufacture semiconductor packages
The method of part can provide more crystal grain in the limited areal of wafer, and these crystal grain are during subsequent simple grain
Equally can coverlet be granulated into meet desired packaging part size be standard-sized 0201,0402 or DFN 10.In view of
This, the method for the special manufacture semiconductor package part that the structure of the semiconductor package part of the disclosure is reflected can make cost
Efficiency is opposite to be promoted.In addition, when being encapsulated crystal grain, the relatively high packing colloid of dielectric coefficient is not used, uses dry film
Protection materials in processing procedure, or the encapsulating material using dielectric coefficient less than packing colloid.Accordingly, ghost effect is not relatively tight
Weight.In addition, the present invention carries out the electric connection between crystal grain and carrier substrate by the conductive component of no conductive, therefore relatively not
Easily cause ghost effect.Be therefore, when crystal grain is operated in high frequency, crystal grain is influenced relatively small by ghost effect, and then makes
The electrical efficiency of crystal grain is obtained opposite to get a promotion.
Opposite, in some existing semiconductor package parts, the size of crystal grain is equal to the size of semiconductor package part.
For example, when the size of semiconductor package part is standard size 0201, the size of crystal grain is then similarly standard size 0201.
Thus, in the given area of wafer, the quantity for the crystal grain that can be obtained is opposite to be lacked so that cost efficiency is relatively
It is low.In addition, in some existing semiconductor package parts, it is encapsulated using packing colloid.However, due to Jie of packing colloid
Electrostrictive coefficient is relatively high, and packing colloid may cause relatively serious ghost effect (such as parasitic capacitance or dead resistance).In addition,
Crystal grain is electrically connected by plain conductor and carrier substrate.Therefore, the relatively long length of plain conductor is also easy to draw
Play ghost effect.Be therefore, when crystal grain operate in high frequency when, crystal grain may be influenced by ghost effect and so that crystal grain is electrically imitated
It can not be promoted.In addition, the encapsulation of packaging part may need multiple linkage interface interface, the complexity of processing procedure is relative increased
Degree.In addition, the encapsulation of crystal grain is in addition to needing viscous brilliant (die bonding) processing procedure, bonding wire (wire bonding) processing procedure and sealing
(molding) the complicated processing procedure such as processing procedure could be completed, it is also necessary to could carry crystal grain using the substrate of lead frame or circuit board.Such as
This one, cost can not be reduced effectively.
Description of the drawings
Spread out when can be considered in conjunction with the accompanying by reference to detailed description and claim for the more complete understanding of the disclosure
It is raw, wherein throughout the drawings, similar Ref. No. refers to similar element.
Fig. 1 is the schematic diagram of wafer in the related technical field.
Fig. 2 is the schematic diagram of the semiconductor package part of the crystal grain of Fig. 1 in the related technical field.
Fig. 3 to 9 is the sectional view according to the manufacturing process of the method for the manufacture semiconductor package part of the present invention.
Figure 10 is the flow chart according to the method for the manufacture semiconductor package part of the present invention.
Figure 11 is the perspective view of the semiconductor package part of one embodiment of the invention.
Figure 12 is the sectional view of the semiconductor package part of Figure 11 of the embodiment of the present invention.
Figure 13 is the top view of the semiconductor package part of Figure 11 of the embodiment of the present invention.
Figure 14 is the perspective view of the semiconductor package part of another embodiment of the present invention.
Figure 15 is the sectional view observed by visual angle of the semiconductor package part of Figure 14 of the embodiment of the present invention along direction B.
Reference sign：
10 wafers
12 crystal grain
20 semiconductor package parts
21 viscose glues
22 substrates
23 conduction columns
24 weld pads
26 packing colloids
28 plain conductors
W1 width
W2 width
30 wafers
32 crystal grain
34 joint sheets
36 joint sheets
50 carrier substrates
51 conduction columns
52 joint sheets
53 conduction columns
54 joint sheets
56 joint sheets
58 joint sheets
60 conductive components
62 conductive components
80 are encapsulated part
90 resultative constructions
92 are encapsulated part through simple grain
94 through simple grain substrate
100 methods
102-1 is operated
200 semiconductor package parts
202 crystal grain
204 are encapsulated part
206 first conductive pads
208 second conductive pads
210 first electrodes
212 second electrodes
216 substrates
W20 width
W22 width
W24 distances
W26 distances
300 semiconductor package parts
320 first crystal grain
340 second crystal grain
306A electrodes
306B electrodes
308A electrodes
308B electrodes
310A electrodes
310B electrodes
360 conductive components
322 electrodes
342 electrodes
W30 sizes
W32 sizes
Specific implementation mode
Attached embodiment of the disclosure shown in the drawings or example are described using language-specific now.However it should manage
Solution, is not intended to thereby limit embodiment of the present disclosure.By any change and modification in the described embodiment, and retouch
Any further application for stating principle within this document is considered as the relevant skilled artisan of the disclosure and can normally think
To person.Embodiment repeated reference may be spread to number, but this is not to say that certain feature of being somebody's turn to do (s) needed one embodiment
It is administered to another embodiment, even if they share identical Ref. No..It will be understood that when an element is referred to as " being connected to " separately
When one element or " being coupled with another element ", it can be connected directly to or be coupled to another element or may occur in which intermediary
Element.
Furthermore space correlation vocabulary, such as " ... under ", " below ", "lower", " above ", "upper" and similar vocabulary,
It can be in order to make specification convenient for an elements or features of the description as shown in attached drawing and another (or multiple) elements or features
Relativeness and use in this article.Other than orientation drawn in attached drawing, these spaces are also intended to respect to vocabulary for containing
Different direction when lid arrangement is in use or operates.The equipment, which can be oriented otherwise, (to be rotated by 90 ° or in other sides
Position), these used space correlation specifiers can be explained in a similar manner herein accordingly.
Fig. 1 is the schematic diagram of wafer 10 in the related technical field.Referring to Fig.1, wafer 10 includes multiple crystal grain 12.It is logical
For often, the size of crystal grain is that the specification met required for obtained packaging part after encapsulation according to the crystal grain is recorded
Size determines.Accordingly, when the size of the packaging part recorded in the specification is standard-sized 0201, the size of crystal grain will be essential
When being above equal to standard-sized 0201, the size of crystal grain will be essentially equal to standard-sized 0201, wherein standard-sized
0201 refers to a length of 600 microns (m), width 300m, a height of 300m, and wherein length respectively can be with the deviation of ± 100m
Value.Similarly, when the size of the packaging part recorded in the specification is standard-sized 0402, the size of crystal grain will be essentially equal to mark
The 0402 of object staff cun, wherein standard-sized 0402 refer to a length of 1000 μm, width be 500 μm, it is 500 μm a height of, wherein it is long,
Wide, the high deviation that can respectively have ± 200m.Also, the size for working as the packaging part recorded in specification is standard-sized DFN 10
When, when the size of crystal grain will be essentially equal to standard-sized DFN 10, the size of crystal grain will be essentially equal to standard-sized
DFN 10, wherein standard-sized DFN 10 refers to that a length of 2500m, width 1000m, a height of 500m, wherein length are each
From the deviation that can have ± 200m.On the implementation, since other additional elements can be added in a package, the size of crystal grain can be slightly
It is small in standard-sized 0402, but be substantially identical to standard-sized 0402.Due to standard-sized 0201 and 0402
Size is relatively large, therefore the size of crystal grain 12 is also relatively large.Under the given area of wafer 30, since the size of crystal grain 12 is opposite
Greatly, the quantity for the crystal grain 12 that wafer 30 can include is relatively limited.
Fig. 2 is the schematic diagram of the semiconductor package part 20 of the crystal grain 12 of Fig. 1 in the related technical field.With reference to Fig. 2, remove
Outside crystal grain 12, semiconductor package part 20 includes a substrate 22, a plurality of plain conductors 28 and a packing colloid 26.Crystal grain 12 is logical
The surface that a viscose glue 21 is fixed on substrate 22 is crossed, is respectively and electrically connected on substrate 22 further through a plurality of plain conductors 28 plural
A weld pad 24.Substrate 22 includes a plurality of conduction columns 23, therefore a plurality of weld pads 24 can pass through a plurality of conduction columns 23 and substrate
A plurality of connection pads 26 of 22 bottoms are electrically connected.Also, a plurality of connection pads 26 can be combined with tin ball (not shown), it so can be with shape
At ball grid array (ball grid array, BGA) packaging part.For crystal grain 12 and a plurality of plain conductors 28 can be protected not to be damaged
Bad, crystal grain 12 and a plurality of plain conductors 28 are coated with the influence of isolated environment by packing colloid 26.In addition, continuing at institute in Fig. 1
Illustrate, as can be seen from Figure 2 the size of crystal grain 12, such as width W1, the size with packaging part 20, such as width W2, substantially
It is identical.
It is that crystal grain 12 is pasted on 22 top surface of substrate in short, in the structure of the packaging part 20 of Fig. 2.Then, it is beaten
Wire bonding (wire bonding) processing procedure.In addition, then at the back side (connection pad 26 where face) of substrate 12 plant with solder ball with into
The electric connection of row and exterior electrical components.In the case, usually, the dielectric coefficient of packing colloid 26 is relatively high, envelope
Dress colloid 26 may cause relatively serious ghost effect (such as parasitic capacitance or dead resistance).In addition, plain conductor 28
Relatively long length also easily causes ghost effect.Therefore, when crystal grain 12 is operated in high frequency, crystal grain 12 may be by parasitism
The influence of effect and make 12 electrical efficiency of crystal grain can not be promoted.In addition, the encapsulation of packaging part 20 may need multiple connection
Interface relative increases the complexity of processing procedure.In addition, the encapsulation of crystal grain 12 is in addition to needing viscous brilliant (die bonding) system
The complicated processing procedures such as journey, bonding wire (wire bonding) processing procedure and sealing (molding) processing procedure could be completed, it is also necessary to use conducting wire
The substrate of frame or circuit board could carry crystal grain 12.Thus, which cost can not be reduced effectively.
Fig. 3 to 9 is the sectional view according to the manufacturing process of the method for the manufacture semiconductor package part of the present invention.Reference Fig. 3,
One wafer 30 is provided.In addition, forming the crystalline substance with the size much smaller than standard size 0201 in wafer 30 and on the wafer 30
Grain 32, wherein standard-sized 0201 refers to that a length of 600m, width 300m, a height of 300m, wherein length can respectively have
There is the deviation of ± 100m.Alternatively, the size of crystal grain 32 refers to growing much smaller than standard-sized 0402, standard-sized 0402
For 1000 microns (m), width 500m, a height of 500m, wherein length respectively can be with the deviation of ± 200m.Also, alternatively,
The size of crystal grain 32 be much smaller than standard-sized DFN 10, standard-sized DFN 10 refer to a length of 2500 μm, width be 1000 μ
M, a height of 500 μm, wherein length respectively can be with the deviation of ± 200m.In one embodiment, the size of crystal grain 32 is small
In the half of standard size 0201.In some embodiments, about the 3% of the size under gauge 0201 of crystal grain 32.
In another embodiment, the one third of the one of the size under gauge 0201 of crystal grain 32.In still another embodiment
In, 32 size of crystal grain is standard-sized 01005, wherein standard-sized 01005 refers to that a length of 300 microns of (m), width are
160m, a height of 100m.Then, joint sheet 34 and 36 is formed on crystal grain 32.In one embodiment, the size of crystal grain 32 includes 4
One of Mill (mil), 6mil and 8mil.In order to which attached drawing is succinct, joint sheet 34 and 36 is drawn only on a crystal grain 32.Reference
Fig. 4 obtains crystal grain 32 by cutting crystal wafer 30.In other words, each crystal grain 32 is detached via the cutting operation one from another entity.
In one embodiment, crystal grain 32 be a transient voltage suppressor (transient voltage suppressor,
TVS).In further embodiments, crystal grain 32 can be logic crystal grain (e.g., central processing unit, microcontroller, etc.), storage
Device crystal grain (e.g., dynamic random access memory (dynamic random access memory, DRAM) crystal grain, static random
Access memory (static random access memory, SRAM) crystal grain, etc.), power management crystal grain (e.g., power management
Integrated circuit integrated circuit (power management integrated circuit, PMIC) crystal grain), radio frequency (radio
Frequency, RF) crystal grain, sensor crystal grain, MEMS (micro-electro-mechanical-system, MEMS)
Crystal grain, signal processing crystal grain (e.g., Digital Signal Processing (digital signal processing, DSP) crystal grain), front end are brilliant
Grain (e.g., AFE(analog front end) (analog front-end, AFE) crystal grain), analog, or combinations thereof.Also, in some embodiments,
Crystal grain 32 can have different sizes, and in other embodiments, and crystal grain 32 can have identical size, but much smaller than standard size
0201。
With reference to Fig. 5, a carrier substrate 50 is provided.It is provided with joint sheet 52 and 54 on first face of carrier substrate 50, engages
Pad 52 and 54 is being electrically connected.Be provided with joint sheet 56 and 58 on second face of carrier substrate 50, joint sheet 56 and 58 to
Electrical connection, wherein first faces to stand on the second face.Conduction column 51 and 53 is equipped in carrier substrate 50, conduction column 51 is to electrical
Joint sheet 52 and 56 is connected, and conduction column 53 is being electrically connected joint sheet 54 and 58.Carrier substrate 50 includes a conducting carrier plate
And one of a non-conductive support plate.In one embodiment, which includes a printed circuit board (printed circuit
Board, PCB).In further embodiments, carrier substrate 50 can be glass carrier substrate, ceramic monolith substrate or similar
Object.In some embodiments, carrier substrate 50 is not semiconductor substrate.More particularly, carrier substrate 50 be not it is doped or
Undoped silicon or semiconductor-on-insulator (semiconductor-on-insulator, SOI) substrate.
With reference to Fig. 6, conductive component 60 and 62 is formed on carrier substrate 50.More specifically, it is respectively formed conductive component
60 and 62 on the joint sheet 52 of carrier substrate 50 and 54.In one embodiment, one of steel plate or screen painting processing procedure are utilized
Form conductive component 60 and 62.In one embodiment, in the person of steel plate or screen painting processing procedure, the material of use includes silver
Or one of tin.In one embodiment, the material of use includes conducting resin material, such as transparent conductive oxide (transparent
Conducting oxide, TCO), graphene or other suitable materials.In one embodiment, punching press can be used
(stamping) processing procedure or dispensing processing procedure.In one embodiment, conductive component 60 and 62 includes planting ball, elargol or tin cream.At this
In embodiment, conductive component 60 and 62 is located at the center of joint sheet 52 and 54, but the present invention is not limited thereto.Conductive part 60
It can be located on joint sheet 52 close to the end of joint sheet 54, conductive part 62 can be located on joint sheet 54 close to the end of joint sheet 52
Portion.Accordingly, even if the volume of crystal grain 32 further reduces so that the distance between the joint sheet 34 of crystal grain 32 and 36 becomes smaller, without
The design for changing the joint sheet 52 and 54 on substrate 50, (for example, it is not necessary to modify the design of joint sheet 52 and 54, so that joint sheet
52 and 54 closer to), the crystal grain 32 that still can arrange in pairs or groups relatively small.Thus, which fabrication steps can be relatively easy.
With reference to Fig. 7, crystal grain 32 is bonded on conductive component 60 and 62.More specifically, by the joint sheet 44 of crystal grain 32
And 46 be respectively aligned to conductive component 60 and 62, and the joint sheet of crystal grain 32 44 and 46 is respectively engaged to conductive component 60 and 62
On.Crystal grain 12 is by conductive component 60 and 62 from passing through a conducting wire (for example, plain conductor 28 of Fig. 2) and carrier substrate 50
It is electrically connected.
With reference to Fig. 8, crystal grain 32 is encapsulated.More specifically, by one be encapsulated part 80 by crystal grain 32, joint sheet 44 and 46,
Conductive component 60 and 62 and joint sheet 52 and 54 be encapsulated in and be encapsulated in part 80.In more detail, on Practical Operation, Fig. 8 institutes
The resultative construction shown includes not only a crystal grain 12, contains multiple crystal grain 12.In order to which attached drawing understands, only shown in Fig. 8 single
A crystal grain 12.In one embodiment, the packaging part 20 for being different from Fig. 2 is encapsulated crystal grain 12 using sealing (molding) processing procedure, the reality
It is such as in a dry film processing procedure, crystal grain 12 to be encapsulated using a protection materials to apply example.It can via heat treatment (curing) program
So that crystal grain 32 is combined with part 80 is encapsulated, it is encapsulated part 80 and then can be used to protective substrate 50, preventing substrate 50, there is a situation where fragmentations.
In one embodiment, protection materials include polyimides (polyimide), epoxy resin (epoxy resin), benzocyclobutene
One of resin (BCB) or high molecular polymer (polymer) or any suitable material.In one embodiment, protected material
Material includes liquid photoresist.
With reference to Fig. 9, resultative construction 90 (total as shown in Figure 8) simple grain after crystal grain 12 is encapsulated turns to an encapsulation
Part 90.In other words, a packaging part 90 is containing there are one crystal grain 32.Substrate 50 becomes after simple grain through simple grain substrate 94, and
Being encapsulated part 80 becomes being encapsulated part 92 through simple grain after simple grain.The size of packaging part 90 is equal to standard size 0201.At some
In embodiment, the size of packaging part 90 is equal to standard size 0402.In further embodiments, the size of packaging part 90 is equally marked
Object staff cun DFN 10.The size of crystal grain 32, such as width W3 are much smaller than the size of packaging part 90, such as width W3.Packaging part 90
Size, such as width W4 is essentially equivalent to standard-sized 0201.In the present invention, even if the ruler of desired packaging part
Very little is standard-sized 0201 (standard size 0402 or standard size DFN 10), passes through the manufacture semiconductor packages of the disclosure
The method of part can provide more crystal grain in the limited areal of wafer, and these crystal grain are during subsequent simple grain
Equally can coverlet be granulated into meet desired packaging part size be standard-sized 0201.In view of this, the system of the disclosure
The method of manufacturing semiconductor packaging part can make cost efficiency is opposite to be promoted.
Figure 10 is the flow chart according to the method 100 of the manufacture semiconductor package part of the present invention.Referring to Fig.1 0, method 100
Start from operation 102, in operation 102, provides wafer.Method 100 continues at operation 104, in operation 104, in the wafer
In and be formed with less than on the wafer a standard size 0201 half a crystal grain.Then, method 100 continues at
Operation 106, in operation 106, crystal grain is obtained by cutting crystal wafer.Method 100 continues at operation 108, in operation 108, carries
For carrier substrate.Method 100 continues at operation 110, in operation 110, forms conductive component on carrier substrate.Method 100
Operation 112 is continued at, in operation 112, is engaged on crystal grain to conductive component.Method 100 continues at operation 114, in operation 114
In, it is encapsulated crystal grain.Method 100 continues at operation 116, and in operation 116, the resultative construction simple grain after crystal grain is encapsulated turns to envelope
The size of dress, encapsulation is equivalent or is more than the standard size 0201.
In the disclosure, when being encapsulated crystal grain, the relatively high packing colloid of dielectric coefficient is not used, uses dry film
Protection materials in processing procedure, or the encapsulating material using dielectric coefficient less than packing colloid.Accordingly, ghost effect is not relatively tight
Weight.In addition, the present invention is to carry out electric connection between crystal grain and carrier substrate by the conductive component of no conductive, thus it is opposite
It is not easy to cause ghost effect.Be therefore, when crystal grain operate in high frequency when, crystal grain influenced by ghost effect it is relatively small, in turn
Enable the electrical efficiency of crystal grain is opposite to get a promotion.Furthermore even if the size of desired packaging part is standard-sized 0201 (mark
0402 or standard size DFN 10 of object staff cun), it, can be in wafer by the method for the manufacture semiconductor package part of the disclosure
In limited areal, provide more crystal grain, and these crystal grain during subsequent simple grain equally can coverlet be granulated into symbol
The size for closing desired packaging part is standard size 0201.In view of this, the method energy of the manufacture semiconductor package part of the disclosure
It is promoted so that cost efficiency is opposite.
Opposite, in some relevant packaging part manufacturing methods, it is encapsulated using packing colloid.However, due to envelope
The dielectric coefficient for filling colloid is relatively high, and packing colloid may cause relatively serious ghost effect (such as parasitic capacitance or parasitism
Resistance).In addition, crystal grain is electrically connected by plain conductor and carrier substrate.Therefore, the relatively long length of plain conductor
Degree also easily causes ghost effect.It is event, when crystal grain is operated in high frequency, crystal grain may be influenced by ghost effect and be made
The electrical efficiency of crystal grain can not be promoted.In addition, the encapsulation of packaging part may need multiple linkage interface interface, system is relative increased
The complexity of journey.In addition, the encapsulation of crystal grain is in addition to needing viscous brilliant (die bonding) processing procedure, bonding wire (wire bonding) system
The complicated processing procedure such as journey and sealing (molding) processing procedure could be completed, it is also necessary to can just be held using the substrate of lead frame or circuit board
Carry crystal grain.Thus, which cost can not be reduced effectively.
Figure 11 is the perspective view of the semiconductor package part 200 of one embodiment of the invention.Semiconductor package part 200 has equivalent
Or the size more than a standard size 0201.In another embodiment, semiconductor package part 200, which has, is equal to or is more than a standard
The size of size 0402.In still another embodiment, semiconductor package part 200, which has, is equal to or is more than a standard size DFN 10
Size.
Referring to Fig.1 1, semiconductor package part 200 is encapsulated part 204 including a crystal grain 202 and one.Crystal grain 202 is located at a substrate
It is contacted on 216 and with substrate 216.In one embodiment, the material of substrate 216 includes glass, printed circuit board (printed
Circuit board, PCB), stainless steel or high molecular one.In one embodiment, the material for being encapsulated part 204 includes dry film
Material.In one embodiment, the material for being encapsulated part 204 includes polyimides (polyimide), epoxy resin (epoxy
Resin), one of benzocyclobutane olefine resin (BCB) or high molecular polymer (polymer).
In addition to this, the size of crystal grain 202 is much smaller than standard size 0201.For example, the size of crystal grain 202 has small
In the size of the half of the standard size 0201, drawings in detail is illustrated in Figure 12.In another embodiment, crystal grain
202 have the size less than standard size 0402.In still another embodiment, crystal grain 202, which has, is less than standard size DFN 10
Size.In one embodiment, the size of crystal grain 202 is standard size 01005.In one embodiment, the size of crystal grain 202 is small
In the one third of standard size 0201.In one embodiment, the size of crystal grain 202 includes 4 Mills (mil), 6mil and 8mil
One of.
In addition, in one embodiment, crystal grain 202 is a transient voltage suppressor (transient voltage
Suppressor, TVS).In further embodiments, crystal grain 202 can be logic crystal grain (e.g., central processing unit, microcontroller
Device, etc.), (e.g., dynamic random access memory (dynamic random access memory, DRAM) is brilliant for memory crystal grain
Grain, static RAM (static random access memory, SRAM) crystal grain, etc.), power management crystal grain
(e.g., power management integrated circuits integrated circuit (power management integrated circuit, PMIC) crystal grain),
Radio frequency (radio frequency, RF) crystal grain, sensor crystal grain, MEMS (micro-electro-mechanical-
System, MEMS) crystal grain, signal processing crystal grain (e.g., Digital Signal Processing (digital signal processing, DSP)
Crystal grain), front end crystal grain (e.g., AFE(analog front end) (analog front-end, AFE) crystal grain), analog, or combinations thereof.Also, one
In a little embodiments, crystal grain 202 can have different sizes, and in other embodiments, and crystal grain 202 can have identical size, but all remote
Less than standard size 0201.
It is encapsulated part 204, is contacted on a substrate 216 and with substrate 216, to be encapsulated crystal grain 202.It is encapsulated part 204
A part is located at 212 lower section of a first electrode 210 and a second electrode of semiconductor package part 200.
Crystal grain 202 is equipped with one first conductive pad 206 and one second conductive pad 208.First conductive pad 206, positioned at being used for
It is electrically connected 210 lower section of a first electrode of the electrical components outside semiconductor package part 200, is for electrically connecting to first electrode
210 to crystal grain 202, and is in direct contact crystal grain 202.Second conductive pad 208, positioned at for being electrically connected semiconductor package part 200
212 lower section of a second electrode of external electrical components, is for electrically connecting to second electrode 212 to crystal grain 202, and be in direct contact
Crystal grain 202.
Figure 12 is the sectional view of the semiconductor package part 200 of Figure 11 of the embodiment of the present invention.Referring to Fig.1 2, crystal grain 202
Width W20 is much smaller than the width W22 for being encapsulated part 204.It is noted that the width W22 for being encapsulated part 204 may be somewhat smaller in half
The width of conductor packaging part 200, but substantially it is equal to the width of semiconductor package part 200.Alternatively, being encapsulated the width of part 204
The difference of W22 and the width of semiconductor package part 200 between be encapsulated part 204 compared with distance W24 is not show relatively with crystal grain 202
It writes.
In addition, the part for being encapsulated part 204 is located at the top of crystal grain 202, and to by the first conductive pad 206 electrically isolated the
Two conductive pads 208.In more detail, part 204 is encapsulated around the first conductive pad 206 and the second conductive pad 208.It is encapsulated part 204
A part is between the first conductive pad 206 and the second conductive pad 208.Furthermore the part for being encapsulated part 204 is located at first electrode
Between 210 and second electrode 212, and to electrically isolated first electrode 210 and second electrode 212.
Based on the schematic diagram of disclosure Figure 12, in the disclosure, even if the size of desired semiconductor package part is standard
0201 (standard size 0402 or standard size DFN 10) of size, the structure institute by the semiconductor package part of the disclosure are anti-
The method of the manufacture semiconductor package part mirrored can provide more crystal grain in the limited areal of wafer, and the crystal grain
During subsequent simple grain equally can coverlet be granulated into the standard size 0201 for meeting desired semiconductor package part.Have
In consideration of it, the method for the manufacture semiconductor package part that the structure of the semiconductor package part of the disclosure is reflected can make cost imitate
Rate is opposite to be promoted.
Figure 13 is the top view of the semiconductor package part 200 of Figure 11 of the embodiment of the present invention.Referring to Fig.1 3, in crystal grain 202
Size be standard size 01005 embodiment in, a length of 300 μm of crystal grain 202 and width are 160 μm；Crystal grain 202 and it is encapsulated material
The distance W24 and W26 of material 204 are respectively 145 μm and 65m.It can be seen that from a length of 300m and distance W24 of crystal grain 202 for 145m,
Crystal grain 202 is much smaller than encapsulation materials 204 (also that is, being much smaller than semiconductor package part 200).
Figure 14 is the perspective view of the semiconductor package part 300 of another embodiment of the present invention.Referring to Fig.1 4, along hatching A-
The diagrammatic cross-section of A ' is equivalent to the sectional view that Figure 12 is shown；And illustrate along the section observed by the view directions of direction B
Figure please refers to Figure 15.Ginseng is back to Figure 14, and semiconductor package part 300 is similar to the semiconductor package part 200 that Figure 11 is illustrated,
The difference is that semiconductor package part 300 includes one first crystal grain 320 and one second crystal grain 340.First crystal grain 320 and the second crystal grain
It is identical to crystal grain 202 on 340 structural nature, therefore some detailed are described in this omission.
Outside the electrode 306A and 306B and semiconductor package part 300 that first crystal grain 320 passes through semiconductor package part 300
Electrical components are electrically connected.The electrode 308A and 308B and semiconductor package part that second crystal grain 340 passes through semiconductor package part 300
Electrical components outside 300 are electrically connected.Partial electrode in described electrode 306A, 306B, 308A, 308B can pass through semiconductor
The conductive component 360 of packaging part 300 is electrically connected to electrode 310A and 310B.
When the size that semiconductor package part 300 is wanted is (or the ruler more than standard size 0201 of standard size 0201
When very little) when, even if the size of first electrode 320 and second electrode 340 (is, for example, less than standard size much smaller than standard size 0201
Half), can still be encapsulated as meeting the semiconductor package part 300 of wanted standard size 0201, without by first electricity
The each of pole 320 and second electrode 340 is designed and sized to standard size 0201, then by complicated processing procedure means, will have
The each of the first electrode 320 and second electrode 340 that have standard size 0201 is integrated.
Figure 15 is observed by view directions of the semiconductor package part 300 of Figure 14 of the embodiment of the present invention along direction B
Sectional view.The size W32 of referring to Fig.1 5, the size W30 of the first crystal grain 320 and the second crystal grain 340 is much smaller than being encapsulated part 304
Size W34.In addition it is brilliant can be electrically connected to electrode 310A and second by conductive component 360 for an electrode 322 of the first crystal grain 320
One electrode 342 of grain 340.
In the present invention, though the size of desired semiconductor package part be standard-sized 0201 (standard size 0402,
Or standard size DFN 10), the manufacture semiconductor package part reflected by the structure of the semiconductor package part of the disclosure
Method can provide more crystal grain in the limited areal of wafer, and these crystal grain are same during subsequent simple grain
Can coverlet be granulated into the standard size 0201 for meeting desired semiconductor package part.In view of this, the semiconductor package of the disclosure
The method for the manufacture semiconductor package part that the structure of piece installing is reflected can make cost efficiency is opposite to be promoted.
In some embodiments, a kind of semiconductor package part is provided.The semiconductor package part has equivalent or is marked more than one
The size of object staff cun 0201.The semiconductor package part includes a crystal grain, has the half less than the standard size 0201
Size；And one be encapsulated part, is encapsulated the crystal grain.
Although the present invention has been combined some embodiments and is illustrated, the present invention is not limited in this specification
Particular form illustrates.On the contrary, the scope of the present invention is only limited by the attached claims.In addition, although inventive features can
Can be described in conjunction with specific embodiment, but those skilled in the art should understand that the various features of described embodiment can
To be combined according to the present invention.In the claims, term "comprising" does not exclude the existence of other components or steps.
In addition, although multiple means, element or method are individually listed, it should be using such as single unit, processor
Or controller is realized.It, should can be by advantageously in addition, although each feature can be contained in different claims
Combination, and be included in different claims and be not meant to that the combination of feature is infeasible and/or advantageous.In addition,
Feature included in a kind of claim is not intended to be limited to the category, but indicates that this feature is equally applicable to other rights
It is required that classification.
In addition, the sequence of feature in the claims is not meant to any particular order having to carry out, and method is weighed
The sequence of each step is not meant to that these steps must sequentially be executed according to this during profit requires.On the contrary, can be to appoint
What suitably sequentially executes these steps.In addition, singular reference be not excluded for it is multiple.Therefore, " one ", " first ", " second " etc.
Term is not precluded multiple.
Although the technology contents and technical characterstic of the disclosure have been disclosed as above, technology in disclosure technical field
Personnel it will be appreciated that defined without departing substantially from appended claim the disclosure design conception and scope in, the teaching of the disclosure and
It is open to make various replacement and modification.For example, above-disclosed many devices or structure can implement in a variety of ways or with
Other structures are replaced, or using the combination of above-mentioned two kinds of modes.
Claims (12)
1. a kind of semiconductor package part, with size equivalent or more than a standard size 0201, which includes：
One crystal grain has the size of the half less than the standard size 0201；And
One is encapsulated part, is encapsulated the crystal grain.
2. semiconductor package part as described in claim 1, further includes：
One first conductive pad is located on the crystal grain, is for electrically connecting to the crystal grain, and be in direct contact the crystal grain；And
One second conductive pad is located on the crystal grain, is for electrically connecting to the crystal grain, and be in direct contact the crystal grain,
Wherein, this is encapsulated a part for part to by electrically isolated second conductive pad of first conductive pad.
3. semiconductor package part as claimed in claim 2, wherein this is encapsulated part around first conductive pad and this is second conductive
Pad, the part for being encapsulated part are located between first conductive pad and second conductive pad.
4. semiconductor package part as claimed in claim 3, further includes：
One first electrode is encapsulated on part and first conductive pad at this, and is electrically connected with first conductive pad；And
One second electrode is encapsulated on part and second conductive pad at this, and is electrically connected with second conductive pad.
5. semiconductor package part as described in claim 1, the wherein size of the crystal grain are standard size 01005.
6. semiconductor package part as described in claim 1, the wherein size of the semiconductor package part are equivalent or are more than a standard
One of size 0402 and a standard size DFN 10.
7. semiconductor package part as described in claim 1, the wherein material for being encapsulated part include polyimides polyimide,
One of epoxy resin epoxy resin, benzocyclobutene resin B CB or high molecular polymer (polymer).
8. semiconductor package part as described in claim 1, further includes：
One substrate, wherein this is encapsulated part and the crystal grain is located on the substrate and is contacted with the substrate.
9. semiconductor package part as claimed in claim 8, the material of the wherein substrate includes glass, printing board PCB, no
Rust steel or high molecular one.
10. semiconductor package part according to any one of claims 8, the wherein substrate include the one of a conducting carrier plate and a non-conductive support plate
Person.
11. semiconductor package part according to any one of claims 10, the wherein conducting carrier plate include a printing board PCB.
12. semiconductor package part as described in claim 1, the wherein crystal grain are one first crystal grain, the semiconductor package part is also
Including：
One second crystal grain, wherein this is encapsulated part and is encapsulated second crystal grain, and first crystal grain and second crystal grain are separated.
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| CN201710196958.6A CN108666278A (en) | 2017-03-29 | 2017-03-29 | Semiconductor package part |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710196958.6A CN108666278A (en) | 2017-03-29 | 2017-03-29 | Semiconductor package part |
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Application publication date: 20181016 |