CN108664212A - The distributed caching of solid storage device - Google Patents

The distributed caching of solid storage device Download PDF

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Publication number
CN108664212A
CN108664212A CN201710219077.1A CN201710219077A CN108664212A CN 108664212 A CN108664212 A CN 108664212A CN 201710219077 A CN201710219077 A CN 201710219077A CN 108664212 A CN108664212 A CN 108664212A
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cpu
buffer unit
write order
application
data
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CN108664212B (en
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侯俊伟
王立辰
孙清涛
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Beijing Memblaze Technology Co Ltd
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Beijing Memblaze Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1458—Management of the backup or restore process
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory

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Abstract

This application provides the method and apparatus of the distributed caching for solid storage device.The method provided includes：Receive the write order from host；Write order is distributed to the first CPU among multiple CPU；First CPU is that write order distributes buffer unit；Distributed buffer unit is written in the data of write order by the first CPU；Buffer unit is all written in response to the write order data to be written, the first CPU is completed to host instruction write order processing.

Description

The distributed caching of solid storage device
Technical field
This application involves technical field of memory, more particularly to the method and dress of distributed caching are provided in storage device It sets.
Background technology
Referring to Fig. 1, the block diagram of storage device is illustrated.Solid storage device 102 is coupled with host, for being carried for host For storage capacity.Host can be coupled in several ways between solid storage device 102, and coupled modes include but not limited to For example, by SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI, Serial Attached SCSI (SAS)), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect Express, PCIe, peripheral component interconnection), NVMe (NVM Express, high speed non-volatile memory), Ethernet, optical fiber it is logical Road, cordless communication network etc. connect host and solid storage device 102.Host can be set through the above way with storage The standby information processing equipment communicated, for example, personal computer, tablet computer, server, portable computer, network exchange Machine, router, cellular phone, personal digital assistant etc..Storage device 102 includes interface 103, control unit 104, one or more A NVM (nonvolatile storage, Non-Volatile Memory) chips 105 and DRAM (Dynamic Random Access Memory, dynamic RAM) 110.Nand flash memory, phase transition storage, FeRAM, MRAM etc. are common NVM.It connects Mouth 103 can adapt to hand over for example, by the modes such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel and host Change data.The data that control unit 104 is used to control between interface 103, NVM chips 105 and firmware memory 110 pass It is defeated, it is additionally operable to storage management, host logical address to flash memory physical address map, erasure balance, bad block management etc..It can be by soft The various ways of part, hardware, firmware or combinations thereof realize control unit 104.Control unit 104 can be FPGA (Field- Programmable gate array, field programmable gate array), ASIC (Application Specific Integrated Circuit, application specific integrated circuit) or a combination thereof form.Control unit 104 can also include place Device or controller are managed, software is executed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle host IO Order.Control unit 104 is additionally coupled to DRAM 110, and may have access to the data of DRAM 110.DRAM can store FTL tables and/ Or the data of the host I/O command of caching.
Control unit 104 includes flash interface controller (or being flash memory channel controller).Flash interface controller coupling NVM chips 105 are closed, and order is sent out to NVM chips 105 in a manner of following the interface protocol of NVM chips 105, with operation NVM chips 105, and receive the command execution results exported from NVM chips 105.The interface protocol of NVM chips 105 includes Interface protocol or standard well known to " Toggle ", " ONFI " etc..
Memory target (Target) is that the shared chip in nand flash memory encapsulation enables (CE, Chip Enable) signal One or more logic units (LUN, Logic UNit).Each logic unit has logical unit number (Logic Unit Number).It may include one or more tube cores (Die) in nand flash memory encapsulation.Typically, logic unit corresponds to single pipe Core.Logic unit may include multiple planes (Plane).Multiple planes in logic unit can be with parallel access, and nand flash memory Multiple logic units in chip can execute order and report state independently of one another.Can be fromhttp：// Www.micron.com/~/media/Documents/Products/Other%20Documents/ONFI3_ 0Gold.ashxIn " the Open NAND Flash Interface Specification (Revision 3.0) " that obtains, carry The meaning about target (target), logic unit, LUN, plane (Plane) has been supplied, has been a part for the prior art.
Solid storage device includes multiple NVM chips.Each NVM chips include one or more tube cores (DIE) or patrol Collect unit (LUN, Logic UNit).Read-write operation can be responded between tube core or logic unit parallel.In same tube core or patrol Multiple reading and writing or the erasing operation sequence collected on unit execute.
Data are usually stored and read on storage medium by page.And data are erased in blocks.Block includes multiple pages.Storage Page (being known as Physical Page) on medium has fixed size, such as 17664 bytes.Physical Page can also have other rulers It is very little.May include multiple data frames (data frame) in Physical Page, data frame has specified size, such as 4096 or 4416 Byte.
In solid storage device, using FTL (Flash Translation Layer, flash translation layer (FTL)) come safeguard from Map information of the logical address to physical address.Logical address constitutes the solid-state that the upper layer software (applications)s such as operating system are perceived and deposits Store up the memory space of equipment.Physical address is the address of the physical memory cell for accessing solid storage device.In existing skill Also implement address of cache using intermediate address form in art.Such as logical address is mapped as intermediate address, and then will be intermediate Address is further mapped as physical address.
The table structure for storing the map information from logical address to physical address is referred to as FTL tables.FTL tables are that solid-state is deposited Store up the important metadata in equipment.The data item of usual FTL tables has recorded the ground in solid storage device as unit of data page Location mapping relations.FTL tables are the important metadata in solid storage device.The data item of usual FTL tables has recorded solid-state storage Address mapping relation in equipment as unit of data page.The FTL tables of solid storage device have larger size, such as several GB grades.And when solid storage device is closed, it needs completely to preserve FTL tables, when solid storage device starts, needs to complete FTL is loaded completely.
FTL tables include multiple FTL table clauses (or list item).In one embodiment, it is had recorded in each FTL table clauses The correspondence of one logical page address and a Physical Page.In another example, it is had recorded in each FTL table clauses continuous Multiple logical page addresses and continuous multiple Physical Page correspondence.In yet another embodiment, in each FTL table clauses Have recorded the correspondence of logical block address and physical block address.In still another embodiment, logical block is recorded in FTL tables The mapping relations of the mapping relations and/or logical page address and physical page address of address and physical block address.
Stand-by power supply is also provided in some solid storage devices, when accident power-off occurs, is set from stand-by power supply to storage It is standby that interim electric energy is provided, for backing up the metadata such as FTL tables and processing still outstanding command.Stand-by power supply includes super Capacitance, aluminum capacitor, tantalum polymer capacitance, lithium battery etc..The log area that the data write-in solid storage device that will be backed up provides. When solid storage device powers on again, restore backed up metadata from log area.
NVMe specifications (http：//nvmexpress.org/wp-content/uploads/NVM_Express_1_2_ 1_Gold_20160603.pdf)Defined in atomic operation (Atomic Operation).Atomic operation includes atomic write life It enables.To execute atom write order, solid storage device ensures to refer to the data shown in atom write order or is all written to solid-state It in storage device or is all not written in solid storage device, without having other Proper Motions.When existing simultaneously to identical Or the identical address in part write-in data two or more atom write orders when, the implementing results of these atom write orders be as It is serially executed with these atomic write orders.
For example, referring to the following table 1, atom write order A writes to logical address (Logic Block Address, LBA) LBA0-3 Enter data, atom write order B (is written with " A " instruction by atom write order A to logical address LBA1-4 write-ins data in table 1 Data, and by " B " instruction by the data of atom write order B write-ins).2nd row of following table and the 3rd row show order A and order B Correct implementing result.Referring to table 1, it is that write order A writes that a kind of possible result, which is LBA 0-3 (as shown in the 2nd row of following table), The data entered, and LBA 4 is the data that write order B is written, in other words, write order B first comes into force, and has updated to atomicity LBA 1-4, following write order A come into force, but atomicity have updated LBA 0-3.Alternatively possible result (such as following table the 3rd Shown in row) be LBA0 it is the data that write order A is written, and LBA 2-4 are the data that write order B is written, and in other words, are write Order A first come into force, have updated to atomicity LBA 0-3, following write order B comes into force, and atomicity have updated LBA 1-4. In addition to two kinds above-mentioned as a result, other any results do not comply with requirement of the NVMe specifications to atom write order.
Table 1
LBA0 LBA1 LBA2 LBA3 LBA4 LBA5 LBA6
Effective result A A A A B
Effective result A B B B B
Null result A A B B B
Solid storage device has high I O process ability, up to a million I/O commands of middle processing per second.Utilizing caching When accelerating IO speed, the performance bottleneck that task is known as solid-state storage performance is cached for every I O process.Further to promote solid-state The performance of storage device needs to break through the performance bottleneck that caching task introduces.
Invention content
The purpose of the application is to provide the method and apparatus of distributed caching in memory, for being promoted at storage device Manage the performance of caching task.
According to the application's in a first aspect, providing the first write command processing method according to the application first aspect, packet It includes：Receive the write order from host；Write order is distributed to the first CPU among multiple CPU；First CPU is write order point With buffer unit；Distributed buffer unit is written in the data of write order by the first CPU；In response to the write order data to be written Buffer unit is all written, the first CPU is completed to host instruction write order processing.
According to the first write command processing method of the first aspect of the application, according to the application first aspect is provided Two write command processing methods further include：According to write order access ranges of logical addresses, by write order distribute to multiple CPU it One.
According to the first or second write command processing method of the first aspect of the application, provide according to the application first party The third write command processing method in face, wherein the logical address space of host accessible, the direction incremental along logical address are divided It is distributed for multiple regions, and the region accessed according to write order, write order is distributed into one of multiple CPU.
According to the third write command processing method of the first aspect of the application, according to the application first aspect is provided Four write command processing methods, wherein each region is distributed to one of multiple CPU in turn.
According to the first or second write command processing method of the first aspect of the application, provide according to the application first party 5th write command processing method in face further includes：The logical address space of host accessible is divided into equal more of same CPU quantity A region, each region are managed by a CPU.
According to the write command processing method of first to one of 5th of the first aspect of the application, provide according to the application 6th write command processing method of first aspect further includes：According to the ranges of logical addresses that write order accesses, write order is distributed To the first CPU in multiple CPU.
According to the 6th write command processing method of the first aspect of the application, according to the application first aspect is provided Seven write command processing methods, wherein if the ranges of logical addresses that write order accesses fully belongs to the first CPU and managed logically Write order is distributed to the first CPU by location range；And if the first part of the ranges of logical addresses of write order access belongs to first The ranges of logical addresses that CPU is managed, and the second part for the ranges of logical addresses that write order accesses belongs to the 2nd CPU and is managed Ranges of logical addresses, the write order is distributed into the first CPU or the 2nd CPU.
According to the 7th write command processing method of the first aspect of the application, according to the application first aspect is provided Eight write command processing methods, if the range for the logical address that write order accesses is more than the ranges of logical addresses that a CPU is managed, In selection multiple CPU corresponding with the range for the logical address that write order accesses, the ranges of logical addresses managed sorts preceding The first CPU write order is handled；And it is patrolled from the first CPU to what other CPU request temporary control and education write orders were accessed Collect address range.
According to the 8th write command processing method of the first aspect of the application, according to the application first aspect is provided Nine write command processing methods, the first CPU include to the ranges of logical addresses needed for the second CPU request temporary control and education write order：The One CPU provides the ranges of logical addresses for belonging to the 2nd CPU for needing to access to the 2nd CPU；And the 2nd CPU according to being received Ranges of logical addresses distributes buffer unit, and record buffer memory unit lends information in its metadata.
According to the write command processing method of first to one of 9th of the first aspect of the application, provide according to the application Tenth write command processing method of first aspect, wherein synchronization, a buffer unit are only used by one of CPU.
According to the 9th or the tenth write command processing method of the first aspect of the application, provide according to the application first party 11st write command processing method in face further includes：In response to receiving the confirmation message of lending of the 2nd CPU, the first CPU is to its yuan Data are modified, to safeguard borrowed buffer unit.
According to the write command processing method of nine to one of 11st of the first aspect of the application, provide according to this Shen Please first aspect the 12nd write command processing method, further include：2nd CPU locks the metadata for the buffer unit lent, Prevent the 2nd CPU from that using the buffer unit lent, can not lend other CPU again by the buffer unit lent again.
According to the write command processing method of nine to one of 12nd of the first aspect of the application, provide according to this Shen Please first aspect the 13rd write command processing method, further include：First CPU is in the buffer unit for having used the 2nd CPU to lend Afterwards, which is returned into the 2nd CPU；And the first CPU and the 2nd CPU respective metadata is also respectively modified, with note Record giving back to the buffer unit that is borrowed.
According to the 8th write command processing method of the first aspect of the application, according to the application first aspect is provided The borrow of 14 write command processing methods, buffer units of each CPU to belonging to other CPU includes：Multiple CPU are arranged Sequence；It is ordered as i-th of CPU and only borrows buffer unit from posterior (i+1) a CPU that sorts；And sort last CPU only Buffer unit is borrowed from the most preceding CPU that sorts, wherein i is positive integer；And each CPU only returns to the CPU for lending buffer unit Also buffer unit.
According to the write command processing method of first to one of 14th of the first aspect of the application, provide according to this Shen Please first aspect the 15th write command processing method, further include：The range for the logical address that first CPU is accessed according to write order And size, determine the quantity of required buffer unit；If the range for the logical address that write order accesses is less than or equal to one and delays Range indicated by memory cell distributes a buffer unit for write order；If the range for the logical address that write order accesses is more than Write order is split as multiple subcommands, the logical address that each subcommand is accessed by the range indicated by one buffer unit Range be no more than the range indicated by buffer unit；And distribute a buffer unit for every sub- write order.
According to the write command processing method of first to one of 15th of the first aspect of the application, provide according to this Shen Please first aspect the 16th write command processing method, each buffer unit can be at different states, and buffer unit can be at State include：" free time " state, is used to indicate buffer unit and is not used by；" occupancy " state, is used to indicate in buffer unit It is cached with data.
According to the write command processing method of first to one of 16th of the first aspect of the application, provide according to this Shen Please first aspect the 17th write command processing method, each CPU, which passes through, safeguards respective metadata management and single using caching Member；And by the part of other CPU " borrow " metadata, managing and using the buffer unit for belonging to other CPU, wherein Record has the feelings that the corresponding logical address of the state of buffer unit, buffer unit, and/or buffer unit are borrowed in metadata Condition.
According to the write command processing method of first to one of 17th of the first aspect of the application, provide according to this Shen Please first aspect the 18th write command processing method, further include：Judgement distributes to whether the buffer unit of write order is that this is write The hit buffer unit of order, wherein if the logical address of write order is the same as the logical address of the metadata record of buffer unit The ranges of logical addresses that identical or write order ranges of logical addresses is buffered the metadata record of unit is included that then this is write The buffer unit is hit in order；If write order hits the buffer unit for distributing to write order, this is written in the data of write order and is delayed Memory cell.
According to the 18th write command processing method of the first aspect of the application, provide according to the application first aspect 19th write command processing method further includes：Check the state of buffer unit；And in buffer unit miss, to write life It enables application not yet be written into the buffer unit in " free time " state of data, or has been written into the buffer unit of data.
According to the 19th write command processing method of the first aspect of the application, provide according to the application first aspect 20th write command processing method is that write order application buffer unit includes：Data in apllied buffer unit are passed through NVM chips are written in " superseded " process；And the buffer unit being emptied is distributed into write order.
According to the 20th write command processing method of the first aspect of the application, provide according to the application first aspect 21st write command processing method, if " superseded " process of waiting is completed and cannot temporarily use buffer unit, pause is to writing life The processing of order.
According to the 18th write command processing method of the first aspect of the application, provide according to the application first aspect 22nd write command processing method, when buffer unit is not ordered, distributing buffer unit for write order includes：From buffer unit pond Middle acquisition buffer unit.
According to the 22nd write command processing method of the first aspect of the application, provide according to the application first aspect The 23rd write command processing method, further include：Give back the buffer unit being emptied to buffer unit pond.
According to the 19th to one of 23 write command processing method of the first aspect of the application, provide according to this Apply first aspect the 24th write command processing method, further include：" superseded " process is actively initiated to buffer unit, so that Being written into the buffer unit of data becomes the buffer unit in " free time " state.
According to the second aspect of the application, the first read command processing method according to the application second aspect is provided, is wrapped It includes：Receive the read command from host；According to the ranges of logical addresses of read command, read command is distributed to the in multiple CPU One CPU；If buffer unit is hit in read command, the first CPU obtains the data that read command is accessed from buffer unit, and is supplied to Host；If read command miss buffer unit, the first CPU is corresponding physically according to the acquisition of the ranges of logical addresses of read command Location, and data are read from memory according to physical address, and it is supplied to host.
According to the first read command processing method of the second aspect of the application, according to the application second aspect is provided Second reading command handling method, if the buffer unit that the first CPU of read command miss is managed, the first CPU distributes for read command Buffer unit is used in combination the data read from memory to replace the data in buffer unit.
According to the first or second read command processing method of the second aspect of the application, provide according to the application second party The third read command processing method in face, if further including that the ranges of logical addresses of read command is managed logically more than the first CPU Location range, the first CPU is to the ranges of logical addresses needed for the second CPU request temporary control and education read command；First CPU checks read command Whether buffer unit that twoth CPU managed has been hit；If the buffer unit that the 2nd CPU of read command hit is managed, first CPU obtains the data that read command is accessed from buffer unit, and is supplied to host.
According to the third read command processing method of the second aspect of the application, according to the application second aspect is provided Four read command processing methods, ask temporary control and education read command needed for ranges of logical addresses include：First CPU is carried to the 2nd CPU For the ranges of logical addresses for belonging to the 2nd CPU for needing to access；2nd CPU checks whether received ranges of logical addresses orders In；If the metadata of the buffer unit of hit is sent to the first CPU by the buffer unit hit that the 2nd CPU is received, the 2nd CPU.
According to the 4th read command processing method of the second aspect of the application, according to the application second aspect is provided Five read command processing methods, if the buffer unit miss that the 2nd CPU is received, the 2nd CPU provides logical address model to the first CPU Enclose the instruction of miss buffer unit.
According to the 4th or the 5th read command processing method of the second aspect of the application, provide according to the application second party The 6th read command processing method in face further includes：If the buffer unit that the 2nd CPU of read command miss is managed, the 2nd CPU are First CPU distributes buffer unit, and the metadata of the buffer unit distributed is sent to the first CPU；And the first CPU according to The ranges of logical addresses of read command obtains corresponding physical address, and data are read from memory according to physical address, provides To host, it is used in combination the data read to replace the data in buffer unit, then the metadata for the buffer unit replaced is sent to 2nd CPU.
According to the 6th read command processing method of the second aspect of the application, seven according to the application second aspect are provided Read command processing method has recorded the logical address of buffer unit in the metadata of buffer unit.
According to the read command processing method of first to one of 7th of the second aspect of the application, provide according to the application 8th read command processing method of second aspect, if the logical address of read command with buffer unit metadata record logically The ranges of logical addresses for the metadata record that location is identical or the ranges of logical addresses of read command is buffered unit included, then this The buffer unit is hit in read command.
According to the read command processing method of first to one of 8th of the second aspect of the application, provide according to the application 9th read command processing method of second aspect further includes：Read command is split as multiple subcommands, the logic of each subcommand Address range is no more than the ranges of logical addresses corresponding to a buffer unit；And each subcommand is handled respectively.
According to the third aspect of the application, the first I/O command processing method according to the application third aspect is provided, is wrapped It includes：According to the address range that write order accesses, write order is distributed to the first CPU in multiple CPU；First CPU is according to described in Address range obtains the right to use of one or more buffer units from the 2nd CPU；First CPU writes the data that write order to be written Enter the buffer unit obtained from the 2nd CPU；Indicate that write order processing is completed；And the first CPU given back to the 2nd CPU from second The right to use for the buffer unit that CPU is obtained.
According to the third aspect the first I/O command processing method of the application, second according to the application third aspect is provided I/O command processing method further includes：First CPU also checks for the right to use of the second buffer unit according to described address range, If the first CPU possesses the right to use of second buffer unit, the second caching of the data that write order to be written write-in Unit.
According to the third aspect the second I/O command processing method of the application, the third according to the application third aspect is provided I/O command processing method further includes：If if the first CPU does not possess the right to use of second buffer unit, suspend to institute State the processing of I/O command.
According to the I/O command processing method of the third aspect first of the application to one of third, provide according to the application 4th I/O command processing method of three aspects, wherein described address is logical address or physical address.
According to the fourth aspect of the application, the first I/O command processing method according to the application fourth aspect is provided, is wrapped It includes：In response to receiving write order, according to the address range that write order accesses, write order is distributed to first in multiple CPU CPU；Write order is divided into one or more sub- write orders by the address accessed according to write order；For every sub- write order distribution caching Unit；If the first buffer unit distributed belongs to the 2nd CPU, the first CPU obtains the use of the first buffer unit from the 2nd CPU Power；Distributed buffer unit is written into every sub- write order data to be written；Indicate that write order processing is completed；And first CPU gives back the right to use of the first buffer unit to the 2nd CPU.
According to the first I/O command processing method of the fourth aspect of the application, according to the application fourth aspect is provided Two I/O command processing methods further include：If the second buffer unit distributed belongs to the first CPU, the first CPU checks the second caching Sub- write order to be written if the first CPU obtains the right to use of second buffer unit for the right to use of unit The second buffer unit is written in data.
According to the second I/O command processing method of the fourth aspect of the application, according to the application fourth aspect is provided Three I/O command processing methods further include：If the first CPU can not obtain the right to use of second buffer unit, pause pair The processing of sub- write order.
According to the first of the fourth aspect of the application to one of third I/O command processing method, provide according to the application 4th I/O command processing method of fourth aspect, wherein a buffer unit belongs to the first CPU more than first, and more than second caching is single Member belongs to the 2nd CPU；And the write order for accessing the first address range is distributed into the first CPU, the second address range will be accessed Write order distribute to the 2nd CPU.
According to the 4th I/O command processing method of the fourth aspect of the application, according to the application fourth aspect is provided Five I/O command processing methods, wherein a buffer unit more than first can only be assigned to the sub- write order for accessing the first address range； And a buffer unit more than second can only be assigned to the sub- write order for accessing the second address range.
According to the I/O command processing method of first to one of 5th of the fourth aspect of the application, provide according to the application 6th I/O command processing method of fourth aspect, wherein described address is physical address.
According to the I/O command processing method of first to one of 5th of the fourth aspect of the application, provide according to the application 7th I/O command processing method of fourth aspect, wherein described address is logical address.
According to the I/O command processing method of five to one of 7th of the fourth aspect of the application, provide according to the application 8th I/O command processing method of fourth aspect, wherein the first address range includes multiple logical address spaces continuously sub- model It encloses, the second address range includes the continuous subrange of multiple logical address spaces；And first address range multiple subranges It is interlaced with one another with multiple subranges of the second address range.
According to the I/O command processing method of five to one of 8th of the fourth aspect of the application, provide according to the application 9th I/O command processing method of fourth aspect, wherein if the first part for the address range that write order accesses belongs to the first ground The write order is distributed to the by location range, and the second part of address range that write order accesses belongs to the second address range One CPU or the 2nd CPU.
According to the I/O command processing method of first to one of 9th of the fourth aspect of the application, provide according to the application Tenth I/O command processing method of fourth aspect, wherein it is single that caching is provided in the memory that the first CPU and the 2nd CPU shares Member；And the first metadata is provided in the memory that the first CPU is monopolized, the state for recording more than first a buffer units； The second metadata is provided in the memory that the 2nd CPU is monopolized, the state for recording more than second a buffer units.
According to the tenth I/O command processing method of the fourth aspect of the application, according to the application fourth aspect is provided 11 I/O command processing methods further include：Record whether corresponding buffer unit can be used in the metadata.
According to the tenth of the fourth aspect of the application the or the 11st I/O command processing method, provide according to the application the 4th 12nd I/O command processing method of aspect further includes：In response to the right to use of the first CPU request third buffer unit, if Three buffer units are in idle condition, and the 2nd CPU corresponding metadata will be supplied to the first CPU with third buffer unit, First CPU uses the third buffer unit according to the corresponding metadata of third buffer unit；2nd CPU also remembers The state that record third buffer unit is borrowed.
According to the tenth of the fourth aspect of the application the or the 11st I/O command processing method, provide according to the application the 4th 13rd I/O command processing method of aspect further includes：In response to the right to use of the first CPU request third buffer unit, if Three buffer units are in seizure condition, and the 2nd CPU initiates selection process to third buffer unit, and third buffer unit is made to become For idle state.
According to the 5th of the application the aspect, the first I/O command processing method according to the 5th aspect of the application, packet are provided It includes：In response to receiving read command, according to the ranges of logical addresses that read command accesses, will read to enable first distributed in multiple CPU CPU；Read command is divided into one or more sub- read commands by the logical address accessed according to read command；For every sub- read command distribution Buffer unit；If the first buffer unit distributed belongs to the 2nd CPU, the first CPU obtains the first buffer unit from the 2nd CPU The right to use；For every sub- read command, if having hit the buffer unit distributed, data are obtained from buffer unit, if caching is single The buffer unit that first miss is distributed obtains data from the corresponding physical address of the logical address of sub- read command；Life is read in instruction Processing is enabled to complete；And the first CPU give back the right to use of the first buffer unit to the 2nd CPU.
According to the first I/O command processing method of the 5th of the application aspect, the according to the 5th aspect of the application is provided Two I/O command processing methods further include：If the buffer unit that buffer unit miss is distributed, from the logical address of sub- read command Corresponding physical address obtains data, and acquired data are written to distributed buffer unit.
According to the first or second I/O command processing method of the 5th of the application the aspect, provide according to the 5th side of the application The third I/O command processing method in face further includes：If the second buffer unit distributed belongs to the first CPU, the first CPU obtains the The right to use of two buffer units.
According to the first of the 5th of the application the aspect to one of third I/O command processing method, provide according to the application 4th I/O command processing method of the 5th aspect, wherein a buffer unit belongs to the first CPU more than first, and more than second caching is single Member belongs to the 2nd CPU；And the first CPU is distributed into the read command for accessing the first ranges of logical addresses, the second logic will be accessed The 2nd CPU is distributed in the read command of address range.
According to one of first to fourth I/O command processing method of the 5th of the application the aspect, provide according to the application 5th aspect the 5th I/O command processing method, further include：In response to the right to use of the first CPU request third buffer unit, institute State the 2nd CPU corresponding metadata will be supplied to the first CPU, the first CPU to be cached according to third with third buffer unit The corresponding metadata of unit uses the third buffer unit；2nd CPU also records the shape that third buffer unit is borrowed State.
According to the 6th of the application the aspect, the first I/O command processing method according to the 6th aspect of the application, packet are provided It includes：In response to receiving read command, according to the address range that read command accesses, will read to enable the first CPU distributed in multiple CPU； Read command is divided into one or more sub- read commands by the address accessed according to read command；It is single for every sub- read command distribution caching Member；If the first buffer unit distributed belongs to the 2nd CPU, the first CPU obtains the use of the first buffer unit from the 2nd CPU Power；For every sub- read command, if having hit the buffer unit distributed, data are obtained from buffer unit, if buffer unit is not The distributed buffer unit of hit obtains data from the address that sub- read command accesses；Indicate that read command processing is completed；And first CPU gives back the right to use of the first buffer unit to the 2nd CPU.
According to the 7th of the application the aspect, the first power down process method according to the 7th aspect of the application, caching are provided The metadata of unit indicates the state of buffer unit address in memory and buffer unit, and this method includes：In response to The prompt of powered-off fault is received, the processing for the I/O command not yet completed is terminated；The state of buffer unit when occurring according to power down Identification needs the buffer unit backed up；It will need the buffer unit backed up and its metadata that NVM chips are written.
According to the first power down process method of the 7th of the application the aspect, second according to the 7th aspect of the application is provided Power down process method, the state that buffer unit can be at include：" free time " state, is used to indicate buffer unit and is not used by；It " accounts for With " state, it is used to indicate in buffer unit and is cached with data.
According to the second power down process method of the 7th of the application the aspect, the third according to the 7th aspect of the application is provided Power down process method, wherein the buffer unit in " occupancy " state needs to back up；Buffer unit in " free time " state without It is backed up.
According to second or third power down process method of the 7th of the application the aspect, provide according to the 7th aspect of the application The 4th power down process method, the state that buffer unit can be at further includes " eliminate in " state, in response to by " occupancy " state The process of data write-in NVM chips that is cached of buffer unit start, buffer unit enters " eliminate in " state；And response NVM chips are written into the data that buffer unit is cached, buffer unit reenters " free time " state.
According to the 4th power down process method of the 7th of the application the aspect, the 5th according to the 7th aspect of the application is provided Power down process method, wherein the buffer unit in " in eliminating " state needs to back up.
According to the 5th power down process method of the 7th of the application the aspect, the 6th according to the 7th aspect of the application is provided Power down process method, wherein when the buffer unit in " in eliminating " state is without being backed up；The method further includes：At waiting Become " free time " state in the buffer unit of " in eliminating " state.
According to the power down process method of first to one of 6th of the 7th of the application aspect, provide according to the application the Seven aspect its power down process method, further include：The buffer unit and its metadata that will back up are stored in the finger of memory Determine memory space, then by the designated memory space monolithic backup of memory to NVM chips.
According to the power down process method of first to one of 7th of the 7th of the application aspect, provide according to the application the 8th power down process method of seven aspects, wherein each CPU manages multiple buffer units, this method further includes：Each CPU will be borrowed The metadata of buffer unit returns to the CPU for lending buffer unit；In response to receiving the metadata given back, sequence it is multiple Each CPU in CPU in addition to the last CPU that sorts identifies that itself needs the quantity of the buffer unit backed up, and will back up The quantity of buffer unit notify next CPU in the sequence of multiple CPU；The most preceding CPU of sequence in multiple CPU is by specific bit The initial address as backup buffer unit is set, and backs up buffer unit；The posterior CPU of sequence in multiple CPU is according to preceding It is big to calculate buffering areas of the previous CPU for backing up needed for buffer unit for the buffer unit quantity that the needs that CPU is provided back up It is small, and determine the initial address of itself backup buffer unit, and back up buffer unit.
According to the 8th power down process method of the 7th of the application the aspect, the 9th according to the 7th aspect of the application is provided Power down process method further includes：The needs that each CPU in multiple CPU of sequence in addition to the most preceding CPU that sorts will be received The buffer unit quantity of backup and itself buffer unit quantity to back up are cumulative, and under informing in multiple CPU sequences One CPU.
According to the 8th or the 9th power down process method of the 7th of the application the aspect, provide according to the 7th aspect of the application The tenth power down process method, further include：After completing the backup to buffer unit in response to all CPU, power down process is indicated It completes.
According to the power down process method of eight to one of tenth of the 7th of the application aspect, provide according to the application the Seven aspect the 11st power down process method, further include：Each CPU after completing to the backup of buffer unit, complete by just backup It informs next CPU in multiple CPU sequences, and confirms that the backup of all CPU is completed by the last CPU that sorts in multiple CPU.
According to the power down process method of eight to one of tenth of the 7th of the application aspect, provide according to the application the Seven aspect the 12nd power down process method, further include：One of multiple CPU are specified to collect the backup progress of buffer unit, other Each CPU informs specified CPU, and confirm that backup is completed by specified CPU after completing buffer unit backup.
According to the power down process method of first to one of 7th of the 7th of the application aspect, provide according to the application the Seven aspect the 13rd power down process method, further include：The metadata of borrow is returned to the CPU for lending metadata by CPU；Response In receiving the metadata given back, CPU, which is identified, itself needs the quantity of the buffer unit backed up, and itself is needed the caching backed up The quantity of unit notifies next CPU in the sequence of multiple CPU；The buffer unit that CPU is backed up according to the needs that previous CPU is provided Quantity calculates and is used to back up the buffer size needed for buffer unit in preceding CPU, and determines rising for itself backup buffer unit Beginning address, and back up buffer unit.
According to the 13rd power down process method of the 7th of the application aspect, the according to the 7th aspect of the application is provided 14 power down process methods further include：Buffer unit quantity that CPU backs up the needs received and itself is to back up Buffer unit quantity is cumulative, and informs next CPU in multiple CPU sequences.
According to the 13rd or the 14th power down process method of the 7th of the application the aspect, provide according to the application the 7th 15th power down process method of aspect further includes：CPU after completing to the backup of buffer unit, complete to inform finger by just backup Next CPU in fixed CPU or multiple CPU sequences.
According to the 15th power down process method of the 7th of the application aspect, the according to the 7th aspect of the application is provided 16 power down process methods further include：Last CPU in the sequence of multiple CPU is referred to based on the backup completion that other CPU are provided Show, confirms that the backup of all CPU is completed.
According to the power down process method of eight to one of 16th of the 7th of the application the aspect, provide according to the application 17th power down process method of the 7th aspect, wherein the buffer unit that CPU is borrowed according to the metadata identification of buffer unit.
According to the eighth aspect of the application, the first atom write order side of execution according to the application eighth aspect is provided Method, including：Atom write order is received, according to the address range of atomic write command access, atom write order is split as multiple sons Order；Pending subcommand is obtained, and buffer unit is distributed for subcommand；Request is that the corresponding buffer unit of subcommand adds Lock；In response to being locked successfully for the corresponding buffer unit of subcommand, the data of subcommand are written to distributed buffer unit.
According to the first atomic write command executing method of the eighth aspect of the application, provide according to the application eighth aspect The second atomic write command executing method, wherein subcommand access address range be less than or equal to buffer unit address model It encloses.
According to the first or second atomic write command executing method of the eighth aspect of the application, provide according to the application Eight aspect third atomic write command executing method, further include：If subcommand distribution buffer unit failure, suspend to the sub- life The processing of order.
According to the first of the eighth aspect of the application to one of third atomic write command executing method, provide according to this Apply eighth aspect the 4th atomic write command executing method, further include：Judge whether to be to belong to same atom write order The corresponding buffer unit of multiple subcommands all locks；If all locking, multiple subcommands to the atom write order are completed Processing；If not locking all, next subcommand in multiple subcommands of the atom write order is obtained.
According to the 4th atomic write command executing method of the eighth aspect of the application, provide according to the application eighth aspect The 5th atomic write command executing method, buffer unit is all written in the corresponding data of all subcommands of the atom write order Afterwards, indicate that the atomic write command process is completed to host.
According to the atomic write command executing method of first to one of 5th of the eighth aspect of the application, provide according to this Apply eighth aspect the 6th atomic write command executing method, further include：For the subcommand of acquisition, check whether it is affiliated Atom write order multiple still untreated subcommands in, by the subcommand that address sort is most preceding；And only when the son of acquisition Order is Subcommand distributes buffer unit.
According to the atomic write command executing method of first to one of 5th of the eighth aspect of the application, provide according to this Apply eighth aspect the 7th atomic write command executing method, further include：For the subcommand of acquisition, check whether it is affiliated Atom write order multiple still untreated subcommands in, by the subcommand that address sort is most preceding；And only when the son of acquisition Order when by the most preceding subcommand of address sort, is just asked in multiple still untreated subcommands of affiliated atom write order It asks and is locked for the corresponding buffer unit of subcommand.
According to the atomic write command executing method of first to one of 5th of the eighth aspect of the application, provide according to this Apply eighth aspect the 8th atomic write command executing method, further include：Obtain multiple still untreated sons of atom write order In order, by the subcommand that address sort is most preceding；And request is that the corresponding buffer unit of the subcommand locks.
According to the atomic write command executing method of first to one of 5th of the eighth aspect of the application, provide according to this Apply eighth aspect the 9th atomic write command executing method, by the address of multiple subcommands of atom write order value it is suitable Sequence is distributed buffer unit for each subcommand, and is locked to buffer unit, and only after locking successfully, the value of address is pressed in just processing Next subcommand of sequence.
According to the atomic write command executing method of six to one of 9th of the eighth aspect of the application, provide according to this Apply eighth aspect the tenth atomic write command executing method, further include：Multiple subcommands of atom write order are arranged by address Sequence is the descending sort of the ascending sort or address value according to address value.
According to the atomic write command executing method of first to one of tenth of the eighth aspect of the application, provide according to this Apply eighth aspect the 11st atomic write command executing method, further include：In response to adding for the corresponding buffer unit of subcommand It locks successfully, also updates the state of buffer unit；And the address model that subcommand is accessed is recorded in the metadata of buffer unit It encloses.
According to the atomic write command executing method of first to one of 11st of the eighth aspect of the application, basis is provided The sub- write order of the twelve source acupoint of the application eighth aspect executes method, further includes：In all subcommands pair of the atom write order After all buffer unit is written in the data answered, the lock of the corresponding buffer unit of all subcommands with the atom write order is discharged.
According to the 9th of the application the aspect, the execution of the first atom write order of the 9th aspect according to the application is provided Method, including：Receive atom write order；Atom write order is distributed to the first CPU in multiple CPU；According to atom write order Atom write order is split as multiple subcommands by the address range of access；Pending subcommand is obtained, and is distributed for subcommand Buffer unit；The buffer unit to be distributed is asked to lock；In response to being locked successfully for the buffer unit that is distributed, subcommand Distributed buffer unit is written in data.
According to the execution method of the first atom write order of the 9th of the application the aspect, the 9th according to the application is provided The execution method of second atom write order of aspect further includes：According to the address range that write order accesses, write order is distributed to The first CPU in multiple CPU.
According to the execution method of the first or second atom write order of the 9th of the application the aspect, provide according to the application The 9th aspect third atom write order execution method, wherein if write order access address range fully belong to first Write order is distributed to the first CPU by the address range that CPU is managed.
According to the execution method of the first or second atom write order of the 9th of the application the aspect, provide according to the application The 9th aspect the 4th atom write order method of the execution method 16. according to claim 13 or 14, wherein if writing The first part of the address range of command access belongs to the address range that the first CPU is managed, and the address model that write order accesses The second part enclosed belongs to the address range that the 2nd CPU is managed, and the write order is distributed to the first CPU or the 2nd CPU.
According to the execution method of one of first to fourth atom write order of the 9th of the application the aspect, basis is provided The application the 9th aspect the 5th atom write order execution method, further include：Fail if subcommand distribution buffer unit, Suspend the processing to the subcommand.
According to the execution method of the atom write order of first to one of 5th of the 9th of the application the aspect, basis is provided The application the 9th aspect the 6th atom write order execution method, further include：Acquisition belongs to same atom write order not The most preceding subcommand of address sort, handles the subcommand in processed multiple subcommands.
According to the execution method of the atom write order of first to one of 5th of the 9th of the application the aspect, basis is provided The application the 9th aspect the 7th atom write order execution method, further include：For the subcommand of acquisition, whether it is checked For in multiple still untreated subcommands of affiliated atom write order, by the subcommand that address sort is most preceding；And only when obtaining The subcommand taken is in multiple still untreated subcommands of affiliated atom write order, by the subcommand that address sort is most preceding When, just buffer unit is distributed for subcommand.
According to the execution method of the atom write order of first to one of 5th of the 9th of the application the aspect, basis is provided The application the 9th aspect the 8th atom write order execution method, further include：For the subcommand of acquisition, whether it is checked For in multiple still untreated subcommands of affiliated atom write order, by the subcommand that address sort is most preceding；And only when obtaining The subcommand taken is in multiple still untreated subcommands of affiliated atom write order, by the subcommand that address sort is most preceding When, just request is that the corresponding buffer unit of subcommand locks.
According to the execution method of the atom write order of first to one of 5th of the 9th of the application the aspect, basis is provided The application the 9th aspect the 9th atom write order execution method, further include：The multiple of atom write order are obtained not yet to locate In the subcommand of reason, by the subcommand that address sort is most preceding；And request is that the corresponding buffer unit of the subcommand locks.
According to the execution method of the atom write order of six to one of 9th of the 9th of the application the aspect, basis is provided The application the 9th aspect the tenth atom write order execution method, further include：Multiple subcommands of atom write order are pressed Address sort is the descending sort of the ascending sort or address value according to address value.
According to the execution method of the atom write order of first to one of tenth of the 9th of the application the aspect, basis is provided The application the 9th aspect the 11st atom write order execution method, further include：If the address model of subcommand to be processed It encloses and belongs to the range that the first CPU is managed, be that subcommand to be processed distributes buffer unit, and asks to be divided by the first CPU The buffer unit matched locks.
According to the execution method of the atom write order of first to one of 11st of the 9th of the application the aspect, root is provided According to the execution method of the sub- write order of the twelve source acupoint of the 9th aspect of the application, further include：If the address of subcommand to be processed Range is not belonging to the range that the first CPU is managed, the first CPU according to subcommand to be processed address range belonging to it Two CPU borrow buffer unit.
According to the execution method of the sub- write order of the twelve source acupoint of the 9th of the application aspect, the according to the application is provided Nine aspect the 13rd atom write order execution method, further include：If the address range of subcommand to be processed is not belonging to The range that one CPU is managed, the first CPU obtain member according to the 2nd CPU of the address range belonging to it of subcommand to be processed Data have recorded buffer unit index in metadata；And the first CPU according to acquired metadata be subcommand to be processed Buffer unit is distributed, and the buffer unit to be distributed is asked to lock.
According to the execution method of the sub- write order of the twelve source acupoint of the 9th of the application aspect, the according to the application is provided Nine aspect the 14th atom write order execution method, further include：If the address range of subcommand to be processed is not belonging to The range that one CPU is managed, the first CPU obtain slow according to the 2nd CPU of the address range belonging to it of subcommand to be processed Memory cell；And the first CPU be the acquired buffer unit of subcommand to be processed distribution, and ask the caching list to be distributed Member locks.
According to the execution method of the atom write order of first to one of 14th of the 9th of the application the aspect, root is provided According to the execution method of the 15th atom write order of the 9th aspect of the application, distributing buffer unit for subcommand includes：Slow When memory cell is hit, for the buffer unit of subcommand distribution hit, wherein if the address of subcommand is the same as the metadata of buffer unit The address range for the metadata record that the address of record is identical or the address range of subcommand is buffered unit included, then this Subcommand hits the buffer unit；And in buffer unit miss, for the subcommand application buffer unit.
According to the execution method of the 15th atom write order of the 9th of the application aspect, the according to the application is provided The execution method of 16th atom write order of nine aspects is not yet written into buffer unit miss for write order application The buffer unit in " free time " state of data, or it has been written into the buffer unit of data.
According to the execution method of the 15th or 16 atom write orders of the 9th of the application the aspect, provide according to this Shen The execution method of 17th atom write order of the 9th aspect please is that write order application buffer unit includes：It will be apllied NVM chips are written by " superseded " process in data in buffer unit, with the unit that empties the cache；And the caching list that will be emptied Member distributes to write order.
According to the execution method of the 17th atom write order of the 9th of the application aspect, the according to the application is provided The execution method of 18th atom write order of nine aspects, if " superseded " process of waiting is completed and temporarily caching cannot be used single Member suspends the processing to write order.
According to the execution method of the atom write order of 16 to one of 18th of the 9th of the application the aspect, provide According to the execution method of the 19th atom write order of the 9th of the application the aspect, further include：Buffer unit is actively initiated " to wash in a pan Eliminate " process, so that being written into the buffer unit of data becomes the buffer unit in " free time " state.
According to the execution method of the atom write order of first to one of 19th of the 9th of the application the aspect, root is provided According to the execution method of the 20th atom write order of the 9th aspect of the application, further include：Judge whether to be atomic write life The corresponding buffer unit of all subcommands enabled all locks；If being that the corresponding buffer unit of the atom write order all adds Lock, is all written into buffer unit in response to the data corresponding to all subcommands, indicates that the atomic write command process is complete to host At.
According to the execution method of the 20th atom write order of the 9th of the application aspect, the according to the application is provided Nine aspect the 21st atom write order execution method, further include：If not being the corresponding buffer unit of atom write order It all locks, obtains next subcommand in multiple subcommands of the atom write order.
According to the execution method of the 20th or 21 atom write order of the 9th of the application the aspect, basis is provided The application the 9th aspect the sub- write order of second twelve source acupoint execution method, further include：In all sons of the atom write order After ordering corresponding data that buffer unit all is written, the lock of all buffer units of the atom write order is distributed in release.
According to the execution method of the 12nd to one of 22 atom write order of the 9th of the application the aspect, provide According to the execution method of the 23rd atom write order of the 9th of the application the aspect, further include：For the buffer unit of borrow, After the lock of the buffer unit is released, borrowed buffer unit is given back.
According to the execution method of the 23rd atom write order of the 9th of present application the aspect, provide according to the application's The execution method of 24th atom write order of the 9th aspect, giving back borrowed buffer unit includes：First CPU is to second CPU indicates the metadata of borrowed buffer unit；In response to receiving the buffer unit borrowed indicated by the first CPU Metadata, the 2nd CPU restore the management to the buffer unit lent.
According to the tenth of present application the aspect, the first write order processing unit according to the tenth aspect of the application, packet are provided It includes：Order receiver module, for receiving the write order from host；Order distribution module, it is multiple for distributing to write order The first CPU among CPU；Buffer unit distribution module, for making the first CPU be that write order distributes buffer unit；Data are written Module, for making the first CPU that the data of write order to be written to distributed buffer unit；Command process completes indicating module, uses Buffer unit is all written in the data to be written in response to write order, the first CPU is made to have been handled to host instruction write order At.
On the one hand according to the tenth of the application the, it provides to be handled according to the first read command of the tenth one side of the application and fill It sets, including：Order receiver module, for receiving the read command from host；Order distribution module, for patrolling according to read command Address range is collected, read command is distributed to the first CPU in multiple CPU；Data acquisition module, for making the first CPU from caching The data that read command is accessed are obtained in unit, and are supplied to host；Data acquisition module, if it is slow to be additionally operable to read command miss Memory cell makes the first CPU obtain corresponding physical address according to the ranges of logical addresses of read command, and according to physical address from depositing Data are read in reservoir, and are supplied to host.
According to the 12nd of the application the aspect, provides and dress is handled according to the first I/O command of the 12nd aspect of the application It sets, including：Write order is distributed to the in multiple CPU by order distribution module, the address range for being accessed according to write order One CPU；Buffer unit right to use acquisition module, for make the first CPU according to described address range from the 2nd CPU obtain one or The right to use of multiple buffer units；Data write. module, for making the write-in of the first CPU data that write order to be written from second The buffer unit that CPU is obtained；Command process indicating module is used to indicate write order processing and completes；And the buffer unit right to use Module is given back, for making the first CPU give back to the 2nd CPU the right to use from the 2nd CPU buffer units obtained.
According to the 13rd of the application the aspect, provides and dress is handled according to the first I/O command of the 13rd aspect of the application It sets, including：Order distribution module, in response to receiving write order, according to the address range that write order accesses, write order to be divided The first CPU in the multiple CPU of dispensing；Order splits module, and write order is divided into one by the address for being accessed according to write order Or multiple sub- write orders；Buffer unit distribution module, for distributing buffer unit for every sub- write order；The buffer unit right to use Acquisition module makes the first CPU obtain the first caching from the 2nd CPU if the first buffer unit for being distributed belongs to the 2nd CPU The right to use of unit；Data write. module, for distributed buffer unit to be written in every sub- write order data to be written； Command process indicating module is used to indicate write order processing and completes；And the buffer unit right to use gives back module, for making first CPU gives back the right to use of the first buffer unit to the 2nd CPU.
According to the fourteenth aspect of the application, provides and dress is handled according to the first I/O command of the application fourteenth aspect It sets, including：Order distribution module, in response to receiving read command, according to the ranges of logical addresses that read command accesses, will read to enable Distribute to the first CPU in multiple CPU；It orders and splits module, the logical address for being accessed according to read command divides read command For one or more sub- read commands；Buffer unit distribution module, for distributing buffer unit for every sub- read command；Buffer unit Right to use acquisition module makes the first CPU obtain the from the 2nd CPU if the first buffer unit for being distributed belongs to the 2nd CPU The right to use of one buffer unit；Data acquisition module is used for for every sub- read command, if having hit the caching list distributed Member obtains data, if the buffer unit that buffer unit miss is distributed, from the logical address pair of sub- read command from buffer unit The physical address answered obtains data；Command process indicating module is used to indicate read command processing and completes；And buffer unit uses Power gives back module, for making the first CPU give back the right to use of the first buffer unit to the 2nd CPU.
According to the 15th of the application the aspect, provides and dress is handled according to the first I/O command of the 15th aspect of the application It sets, including：Order distribution module, in response to receiving read command, according to the address range that read command accesses, will read to enable distribution To the first CPU in multiple CPU；Order split module, for according to read command access address by read command be divided into one or Multiple sub- read commands；Buffer unit distribution module, for distributing buffer unit for every sub- read command；The buffer unit right to use obtains Modulus block makes the first CPU obtain the first caching list from the 2nd CPU if the first buffer unit for being distributed belongs to the 2nd CPU The right to use of member；Data acquisition module is used for for every sub- read command, if having hit the buffer unit distributed, from caching Unit obtains data, if the buffer unit that buffer unit miss is distributed, data are obtained from the address that sub- read command accesses；Life Processing indicating module is enabled, read command processing is used to indicate and completes；And the buffer unit right to use gives back module, for making first CPU gives back the right to use of the first buffer unit to the 2nd CPU.
According to the 16th of the application the aspect, the first power down process device according to the 16th aspect of the application is provided, The metadata of buffer unit indicates the state of buffer unit address in memory and buffer unit, which includes：Life Processing module is enabled, for the prompt in response to receiving powered-off fault, terminates the processing for the I/O command not yet completed；It is to be backed up slow Memory cell identification module, the buffer unit that the state recognition needs of buffer unit back up when for occurring according to power down；Data are write Enter module, NVM chips are written in the buffer unit and its metadata for that will need to back up.
According to the 17th of the application the aspect, holding according to the first atom write order in terms of the application the 17th is provided Luggage is set, including：Order receiver module, for receiving atom write order, the address range according to atomic write command access；Order Module is split, for atom write order to be split as multiple subcommands；Order acquisition module, for obtaining pending son life It enables；Buffer unit distribution module, for distributing buffer unit for subcommand；Module is locked, is that subcommand is corresponding for asking Buffer unit locks；Command processing module, in response to being locked successfully for the corresponding buffer unit of subcommand, by subcommand Distributed buffer unit is written in data.
According to the 18th of the application the aspect, holding according to the first atom write order in terms of the application the 18th is provided Luggage is set, including：Order reception device, for receiving atom write order；Order distribution module, for distributing atom write order To the first CPU in multiple CPU；Order splits module, and for the address range according to atomic write command access, atomic write is ordered Order is split as multiple subcommands；Order acquisition module, for obtaining pending subcommand；Buffer unit distribution module, is used for Buffer unit is distributed for subcommand；Module is locked, for the buffer unit locking to be distributed；Data write. module, for ringing The buffer unit that Ying Yuwei is distributed locks successfully, and distributed buffer unit is written in the data of subcommand.
According to the 19th of the application the aspect, the first solid storage device according to the 19th aspect of the application is provided, Including control unit and NVM chips, the control unit includes host interface and the Media Interface Connector for accessing memory, host Interface is used for host exchange command and data, and control unit further includes distributor and multiple CPU, and distributor is coupled to host and connects Mouthful, the I/O command of storage device is sent to for receiving host, and I/O command is distributed into one of multiple CPU；Control unit is also It is coupled to external memory, external memory provides buffer unit；Control unit is additionally coupled to NVM chips, and wherein CPU is for holding Row is according to the application first aspect, the method for second aspect, the third aspect, fourth aspect, the 5th aspect or the 6th aspect.
According to the 20th of the application the aspect, the first solid storage device according to the 20th aspect of the application is provided, Including multiple CPU and external memory, external memory provides buffer unit, and each CPU manages multiple buffer units, and caching is single The state of buffer unit address in memory and buffer unit is had recorded in the metadata of member, CPU is in response to receiving The prompt of powered-off fault terminates the processing for the I/O command not yet completed；The state recognition of buffer unit needs when occurring according to power down The buffer unit to be backed up；And needing the buffer unit backed up and its metadata that NVM chips are written, wherein CPU is for holding Row is according to the method in terms of the application the 7th.
On the one hand according to the 20th of the application the, it provides and is set according to the first solid-state storage of the 20th one side of the application It is standby, including control unit and NVM chips, control unit includes distributor and multiple CPU, and distributor is coupled to host interface, is used In reception I/O command, and I/O command is distributed into one of multiple CPU；Control unit is additionally coupled to external memory, external storage Device provides buffer unit；Control unit is additionally coupled to NVM chips, and wherein CPU is for executing according to the application eighth aspect or the The method of nine aspects.
According to the 22nd of present application the aspect, a kind of program including program code is provided, wherein control unit is used for Execute the write command processing method according to the application first aspect.
According to the 23rd of the application the aspect, a kind of program including program code is provided, wherein control unit is used for Execute the read command processing method according to the application second aspect.
According to the twenty-fourth aspect of the application, a kind of program including program code is provided, wherein control unit is used for Execute the I/O command processing method according to the application third aspect.
According to the 25th of the application the aspect, a kind of program including program code is provided, wherein control unit is used In execution according to the I/O command processing method of the application fourth aspect.
According to the 26th of the application the aspect, a kind of program including program code is provided, wherein control unit is used In execution according to the I/O command processing method of the 5th aspect of the application.
According to the 27th of the application the aspect, a kind of program including program code is provided, wherein control unit is used In execution according to the I/O command processing method of the 6th aspect of the application.
According to the twenty-eighth aspect of the application, a kind of program including program code is provided, wherein control unit is used In execution according to the power down process method of the 7th aspect of the application.
According to the 29th of the application the aspect, a kind of program including program code is provided, wherein control unit is used In execution according to the atomic write command executing method of the application eighth aspect.
According to the 30th of the application the aspect, a kind of program including program code is provided, wherein control unit is used for Execute the atomic write command executing method according to the 9th aspect of the application.
Description of the drawings
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, will be described below to embodiment Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the application Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these Figure obtains other attached drawings.
Fig. 1 is the block diagram of storage device in the prior art；
Fig. 2 is the block diagram according to the control unit of the embodiment of the present application；
Fig. 3 is the schematic diagram distributed according to the I/O command of the embodiment of the present application；
Fig. 4 is the schematic diagram according to the metadata of the buffer unit of the embodiment of the present application；
Fig. 5 is the state diagram according to the buffer unit of the embodiment of the present application；
Fig. 6 is the schematic diagram borrowed according to the buffer unit of the embodiment of the present application；
Fig. 7 is the flow chart according to the processing write order of the embodiment of the present application；
Fig. 8 is the flow chart according to the processing write order of the another embodiment of the application；
Fig. 9 is the flow chart according to the processing read command of the embodiment of the present application；
Figure 10 is the flow chart according to the power down process of the embodiment of the present application；
Figure 11 is the flow chart according to the processing atom write order of the embodiment of the present application；
Figure 12 is the flow chart according to the processing atom write order of the another embodiment of the application；
Figure 13 is the schematic diagram according to the atomic commands of the embodiment of the present application；
Figure 14 is the schematic diagram according to the buffer unit of the embodiment of the present application；
Figure 15 is the schematic diagram according to the buffer unit of the embodiment of the present application；
Figure 16 is the schematic diagram according to the atomic commands of the another embodiment of the application；
Figure 17 is the schematic diagram according to the buffer unit of the another embodiment of the application；
Figure 18 is the schematic diagram according to the buffer unit of the another embodiment of the application；
Figure 19 is the schematic diagram according to the buffer unit of the another embodiment of the application.
Specific implementation mode
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete Site preparation describes, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on this Shen Please in embodiment, every other implementation obtained by those of ordinary skill in the art without making creative efforts Example, shall fall in the protection scope of this application.
Embodiment one
Fig. 2 is the block diagram according to the control unit of the embodiment of the present application.Control unit 104 shown in Figure 2 includes host Interface 210, distributor 230, multiple CPU (CPU0, CPU1, CPU2 and CPU3) for handling caching task and for accessing The Media Interface Connector 220 of NVM chips 105.
Host interface 210 is used for host exchange command and data.In one example, host passes through with storage device NVMe/PCIe protocol communications, host interface 210 handle PCIe protocol data packet, extract NVMe protocol commands, and return to host Return the handling result of NVMe protocol commands.
Distributor 230 is coupled to host interface 210, is sent to the I/O command of storage device for receiving host, and by IO One of multiple CPU for handling caching task are distributed in order.Distributor 230 can be realized by CPU or specialized hardware.
Control unit 104 is additionally coupled to external memory (for example, DRAM) 110.Referring to Fig. 2, the portion of external memory 110 Point space (buffer unit 0, buffer unit 1, buffer unit 2 and buffer unit 3) is used as caching.For handling caching task The distribution and use of multiple CPU management front end caching.For write order, under the instruction of CPU, the data that will be written pass through master Machine interface 210 is transferred to the buffer unit in DRAM 110 from host, and also connects the data in buffer unit by medium Mouth 220 is transferred to NVM chips 105.Optionally, the data of write order can also be transmitted directly to NVM chips 105, and without slow Memory cell.For read command, whether CPU identification buffer units hit, if buffer unit is hit, under the instruction of CPU, from caching Unit obtains data and is sent to host.If buffer unit miss, obtains data from NVM chips 105 and be sent to host, Yi Jike Selection of land, with the data replaced from the data that NVM chips 105 obtain in buffer unit.
It can be communicated with one another between multiple CPU for handling caching task to exchange information.For example, CPU 0 is asked to CPU 1 CPU 1 is asked to manage the metadata of buffer unit so that the operable buffer units managed by CPU 1 of CPU 0.CPU 1 is to CPU 2 Ask the metadata of CPU2 management buffer units so that the operable buffer units managed by CPU 2 of CPU 1.
Control unit 104 further includes FTL module (not shown), for the logical address of flash memory visit order to be converted to object Address is managed, and flash memory is implemented to manage, the services such as abrasion equilibrium, garbage reclamation are provided.,
Embodiment two
Fig. 3 illustrates the schematic diagram distributed according to the I/O command of the embodiment of the present application.Solid storage device is shown to host Addressable logical address.In figure 3, along the incremental direction of logical address, logical address space is divided into multiple regions (302,304......324), each region are assigned to one of multiple CPU (CPU0, CPU1, CPU2 and CPU3) management.
Optionally, one of CPU is distributed into each region in turn.For example, CPU 0 is distributed in region 302, by region 304 It distributes to CPU 1 and CPU 2 is distributed into region 306, CPU 3 is distributed into region 308.Next it unrolls, by region 310 Distribute to CPU0 so that the I/O command from host is equally distributed to multiple CPU as possible.The size in each region can match It sets.For example, each region is 1MB.It avoids being arranged too small by region.Region is arranged too small, can lead to more I/O command The ranges of logical addresses of access crosses over 2 or multiple regions, and increases the expense of synchronous metadata between CPU.As an example, Host provide I/O command access logical address range be no more than 128KB, if by region be set greater than 128KB (for example, 1MB), then so that LBA (logical address) range that I/O command accesses at most is covered two regions, and then two CPU is only needed to synchronize member Data also make the ranges of logical addresses that more I/O commands access only in a region, and are handled by single CPU.
It is to be appreciated that logical address space has other dividing modes.For example, logical address space is divided into same CPU numbers Identical region is measured, each region is managed by a CPU.No matter the LBA range of I/O command, and I/O command is distributed in turn To CPU.
Optionally, solid storage device illustrates addressable physical address to host.I/O command indicates physical address.With And physical address is divided into multiple regions, each region is assigned one of multiple CPU management.Logical address region to be distributed To the same or similar strategy of CPU, physical address area is distributed into CPU.For accessing the physics of instruction solid storage device Physical address can be used directly to access NVM chips for the I/O command of address, and need not use FTL tables.Optionally, to I/O command Physical address is mapped, with the address after being mapped, and for accessing NVM chips.
DRAM 110 provides buffer unit, and the size of each buffer unit is such as 4KB.CPU manages point of buffer unit With with use.Synchronization, a buffer unit are only used by one of CPU.
Embodiment three
Fig. 4 illustrates the schematic diagram of the metadata of the buffer unit according to the embodiment of the present application.Each CPU safeguards respective Cache metadata.For example, referring to Fig. 4, CPU0 safeguards that metadata 0, CPU 1 safeguard metadata 1.......Metadata size compared with It is small, it is storable in the memory inside CPU, to which CPU can with low latency access metadata.
Metadata indicates the buffer unit in DRAM 110.For example, referring to Fig. 4, metadata 0 is to be used for buffer unit 402,404,406 and 408 metadata；Metadata 1 is the metadata for buffer unit 412,414,416 and 418.Pass through dimension Metadata is protected, CPU manages and use buffer unit.And by the way that the part of other CPU " borrow " metadata, one of CPU is managed It manages and using the buffer unit for belonging to other CPU.
Wherein, each buffer unit may include multiple caching subelements.As an example, each caching subelement size is 1KB, and the size of each buffer unit is 4KB.Obviously, buffer unit can have other sizes with caching subelement.It is preferred that Ground, the size for caching subelement is equal to the minimum data cell size that host is sent to the I/O command of solid storage device, and delays The size of memory cell is the data unit size corresponding to the physical address of an entry in FTL tables.
According to an embodiment of the present application, by comparing the logical address recorded in the logical address of I/O command and metadata, Determine whether buffer unit hits.As another example, recording physical address in metadata, by comparing the physics of I/O command The physical address recorded in address and metadata, determines whether buffer unit hits.
Buffer unit stores the data corresponding to I/O command.For example, for write order, buffer unit record host is sent The data of NVM chips are written, and provide what write order processing was completed to host after buffer unit is written in the data of write order Instruction, to reduce write order processing delay.Optionally, buffer unit also acts as the cache for accelerating read operation.
Example IV
Fig. 5 illustrates the state diagram of the buffer unit according to the embodiment of the present application.Each of buffer unit can be at a variety of Different conditions.The state of each buffer unit of metadata record, the corresponding logical address of buffer unit, buffer unit are borrowed The caching subelement of situation, and/or buffer unit is by service condition.
Referring to Fig. 5, the state of buffer unit, including " free time ", " occupancy " and " superseded ".Optionally, can also include " busy It is commonplace " state.Wherein, " free time " state instruction is that the buffer unit is not used by, and is not delayed in the buffer unit of " free time " state Deposit valid data.After being written with data to the buffer unit of " free time " state, buffer unit becomes " occupying " state, to refer to Show and has stored data in buffer unit.Optionally, since data procedures " occupancy " certain time is written, thus, by " busy It is commonplace " state instruction started the state not yet completed of process that data are written to buffer unit but data are written.
In addition, the process referred to as " superseded " of NVM chips is written in the data that the buffer unit of " occupancy " state is cached.It rings Ying Yu " superseded " process starts, and buffer unit enters state " in eliminating ".In response to the end of buffer unit " superseded " process, delay The data that memory cell is cached are written into NVM chips, and buffer unit reenters " free time " state." superseded " process is also referred to as " emptying " process.
Embodiment five
Fig. 6 illustrates the schematic diagram borrowed according to the buffer unit of the embodiment of the present application.Pass through dimension referring also to Fig. 4, CPU0 Protect metadata 0 manage buffer unit 402,404,406 and 408, CPU1 by safeguard metadata 1 management buffer unit 412,414, 416 and 418.
In figure 6, to handle I/O command, CPU 0 is needed using the buffer unit 412 and 414 belonged to originally in CPU 1.CPU 0 Message is sent to CPU1 to ask to obtain buffer unit 412 and 414.Metadata 1 is revised as metadata 1 ' by the modifications of CPU 1, with Record buffer memory unit 412 is borrowed with 414, and CPU 1 loses the right to use to buffer unit 412 and 414 temporarily.And in response to The confirmation to lending buffer unit of CPU 1, CPU 0 also change metadata 0 and obtain metadata 0 ', to be safeguarded by metadata 0 ' Buffer unit 412 and 414.
According to an embodiment of the present application, buffer unit 412 and 414, CPU 0 is being used also to be given back CPU 1.To return Also buffer unit, CPU 0 and CPU 1 also change respective metadata, are given back with 414 yuan to caching single 412 with record.
In one embodiment, multiple CPU (CPU 0, CPU 1, CPU 2 and CPU 3) have sequence.CPU i only from CPU i+1 borrow buffer unit (i takes 0,1 or 2).And the last CPU (for example, CPU 3) that sorts is only from the most preceding CPU that sorts (for example, CPU 0) borrows buffer unit.And CPU only gives back buffer unit to the CPU for lending buffer unit.
Embodiment six
Fig. 7 is the flow chart according to the processing write order of the embodiment of the present application.Referring also to Fig. 2, distributor 230 connects from host The write order from host is received, according to the logical address that write order is accessed, write order is distributed to and is appointed for handling caching One of CPU of business is (referring to Fig. 7, step 710).As an example, the ranges of logical addresses that write order accesses, which is fallen completely within, (includes In) ranges of logical addresses that is managed of CPU 0, thus the write order is distributed to CPU 0 and handled by distributor 230.
Next, CPU 0 is that write order distributes buffer unit (referring to Fig. 7, step in DRAM 110 (referring also to Fig. 2) 720).The ranges of logical addresses and size that CPU 0 is accessed according to write order determine required buffer unit quantity.In some feelings Under condition, the ranges of logical addresses that write order accesses is less than the range indicated by a buffer unit.For example, buffer unit accommodates The range of 4KB logical addresses, and data are written in 2KB of the write order into the 4KB ranges.One buffer unit of distribution can accommodate The write order.In still other situations, the ranges of logical addresses (for example, 128KB) that write order accesses is more than patrolling for buffer unit It collects address range (for example, 4KB) and write order is split as multiple subcommands, what each subcommand was accessed patrols in the case Collect the ranges of logical addresses that address range is no more than a buffer unit.For example, write order accesses the logical address model of 0-7KB It enclosing, two buffer units is distributed for write order, first buffer unit is used to accommodate the data of 0-3KB ranges of logical addresses, and Second buffer unit is used to accommodate the data of 4-7KB LBA ranges.As another example, write order accesses patrolling for 2-9KB Address range is collected, distributes three buffer units for write order, first buffer unit is for accommodating 2-3KB ranges of logical addresses Data, and second buffer unit is used to accommodate the data of 4-7KB ranges of logical addresses, third buffer unit is for accommodating 8- The data of 9KB ranges of logical addresses.Similarly or read command distributes buffer unit.
Wherein, the logical address corresponding to buffer unit (that is, logical address indicated by the metadata of buffer unit) model It encloses and is aligned (its initial address is located at the integral multiple address of 4KB, for example, 0,4KB, 8KB) by such as 4KB, buffer unit institute Corresponding logical address space size is such as 4KB.The size of the ranges of logical addresses of atom write order is the same as the big of buffer unit Small (such as 4KB) can be different.
According to an embodiment of the present application, by the ranges of logical addresses of write order, write order is divided into one or more Subcommand, the ranges of logical addresses that each subcommand is accessed are no more than the ranges of logical addresses corresponding to a buffer unit. And distribute a buffer unit for each subcommand.As an example, write order accesses the logical address space of 1KB-10KB, and Each buffer unit corresponds to 4KB address spaces.Write order is split into subcommand S1, subcommand S2 and subcommand S3.Subcommand The size that S1 accesses 1KB-3KB is 3KB ranges of logical addresses, the logical address that the size that subcommand S2 accesses 4KB-7KB is 4KB Range, the address range that the size that subcommand S3 accesses 8KB-10KB is 3KB.
Optionally, the logical address space corresponding to write order is without continuous and subcommand logical address space Without continuous.
Optionally, to distribute buffer unit, CPU 0 also checks for the state of buffer unit.Distribute to write order or its sub- life The buffer unit of order can be the buffer unit that the write order or its subcommand are hit, in the feelings of any buffer unit of miss Under condition, (it is referred to as " write order ") application buffer unit for the write order or its subcommand.
Next, by comparing the logical address recorded in the logical address and buffer unit metadata of write order, come true Determine whether buffer unit hits.If the logical address of write order is identical with the logical address of the metadata record of buffer unit, or The ranges of logical addresses that the ranges of logical addresses of write order is buffered the metadata record of unit is included that then the write order is hit The buffer unit.
Wherein, the buffer unit for being write order application can be the caching in " free time " state for being not yet written into data Unit can also be the buffer unit in " occupancy ", " busy " or " superseded " for being written into data.If buffer unit is not To apply for buffer unit NVM chips are written by " superseded " process, then will in data in apllied buffer unit by hit The buffer unit being emptied distributes to write order.Optionally, if due to waiting " superseded " process or other operations are completed temporarily not Buffer unit can be used, suspends the processing to write order, for example, waiting list is added in write order.
It is to be appreciated that if write order is split as multiple subcommands, these subcommands can all hit buffer unit, Can also be a part of subcommand hit buffer unit, and another part subcommand miss buffer unit, and not order The subcommand application buffer unit of middle buffer unit.
In one embodiment, buffer unit is distributed for the subcommand of any buffer unit of miss for convenience, is Buffer unit in " free time " state establishes buffer unit pond, is the caching list in " free time " state in buffer unit pond Member.When any buffer unit of subcommand miss, buffer unit is obtained from the buffer unit pond, thus, it is possible to convenient for Subcommand distributes buffer unit.Further, the buffer unit being emptied can be given back to the buffer unit pond.
Next, after being assigned with buffer unit for write order, the data write-in which to be written is distributed Buffer unit (referring to Fig. 7, step 730).For example, dma operation is initiated between host and storage device, the number that will be written According to the buffer unit moved from host to DRAM.Buffer unit is all written in response to the write order data to be written, to Host indicates that write order processing is completed (referring to Fig. 7, step 740).At this point, although data corresponding to write order may not yet by Write-in NVM chips then notify host but as long as these data have been written in buffer unit, and write order processing is completed.This Advantageously reduce the delay of write order processing.
Optionally, " superseded " process is actively also initiated to buffer unit, the buffer unit release of data will be written into, made It becomes the buffer unit in " free time " state.
Embodiment seven
Fig. 8 is the flow chart according to the processing write order of the another embodiment of the application.Distributor 230 receives to come from host Write order is distributed into the CPU for handling caching task according to the logical address that write order is accessed from the write order of host One of (referring to Fig. 8, step 810).As an example, the ranges of logical addresses that write order accesses falls completely within what CPU 0 was managed Ranges of logical addresses, thus the write order is distributed to CPU 0 and handled by distributor 230.As another example, write order accesses Ranges of logical addresses fall into ranges of logical addresses (for example, region 302) that CPU 0 is managed and CPU 1 managed The write order is distributed to patrolling for its access of management by ranges of logical addresses (for example, region 304) (referring also to Fig. 3), distributor 230 Collect one of CPU 0 and CPU 1 of address range processing.As an example, distributor 230 selects in two or more CPU, is managed Ranges of logical addresses sort preceding that CPU (for example, CPU 0) to handle the write order.
Next, CPU 0 checks whether the ranges of logical addresses of write order to be processed has exceeded patrolling of oneself being managed Address range is collected (referring to Fig. 8, step 820).If the ranges of logical addresses of write order falls completely within and (is contained in) itself and managed Ranges of logical addresses, CPU 0 in DRAM for write order distribute buffer unit (referring to Fig. 8, step 830), by write order pair The data answered are written distributed buffer unit and (referring to Fig. 8, step 832), and complete (ginseng to host instruction write order processing See Fig. 8, step 834).
If the ranges of logical addresses of write order has surmounted the ranges of logical addresses that CPU 0 is managed itself, CPU 0 to other Ranges of logical addresses needed for CPU request temporary control and education write order is (referring to Fig. 8, step 840).For example, write order will also access Logical address region 304 (referring also to Fig. 3), one or more buffer units of the CPU 0 to the requests of CPU 1 for region 304.
According to an embodiment of the present application, in order to ask buffer unit, CPU 0 is provided to CPU 1 needs what is accessed to belong to area The ranges of logical addresses in domain 304 (referring also to Fig. 3).CPU 1 is one or more slow according to the ranges of logical addresses distribution received Memory cell (referring to Fig. 8, step 842), and records these buffer units by " borrow " (to CPU in the metadata of CPU 11 0).Optionally, CPU 0 distributes buffer unit from the buffer unit of borrow.
Optionally, to lend buffer unit, CPU 1 also checks for the state of buffer unit.The buffer unit lent can be The buffer unit that the ranges of logical addresses is hit.In the case of any buffer unit of miss, for the ranges of logical addresses Apply for buffer unit.CPU 1 is also borrowed to the instructions of CPU 0 to the buffer unit of CPU 0, for example, instruction buffer unit is in DRAM In storage location and buffer unit state.For example, by being locked for the metadata for the buffer unit lent so that CPU1 cannot use the buffer unit lent, and can not these buffer units be lent other CPU again.
Optionally, if by the buffer unit of " borrow " be written into data be in " occupancy ", " busy " or " superseded " In buffer unit (referring to Fig. 5), CPU 0 or CPU 1 initiate " superseded " process also on these buffer units so that these Buffer unit becomes " free time " state (referring also to Fig. 5).
Optionally, CPU 0 is in response to the response of CPU 1, the buffer unit that record obtains in metadata 0 (referring to Fig. 4), And the buffer unit of " borrow " is used as to distribute to the buffer unit of write order.
Next, distributed buffer unit is written (referring to Fig. 8, step in the data that the write order to be written of CPU 0 844).Buffer unit is all written in response to the write order data to be written, is completed to host instruction write order processing.It can With understand ground, some write orders use multiple buffer units, after all buffer unit is written in the total data of write order, just to Host indicates that write order processing is completed (referring to Fig. 8, step 848).
Optionally, after all buffer unit is written in the total data of write order, CPU 0 also returns the buffer unit of borrow Also CPU 1.CPU 0 indicates given back buffer unit to CPU 1.CPU 1 is in response to the instruction from CPU 0, in metadata 1 The middle state for updating the buffer unit being returned is (referring to Fig. 8, step 846), to which CPU 1 possesses these buffer units again The right to use can be used or lend again these buffer units (for example, the metadata to buffer unit unlocks).CPU 1 is also to CPU 0 confirmation buffer unit give back and CPU 0 removes these buffer units in metadata 0, or mark these buffer units It is returned.To which CPU 0 has the right to use of these buffer units no longer.
Optionally, to give back buffer unit, what CPU 0 was indicated to CPU 1 be buffer unit metadata information (for example, Address of the buffer unit in DRAM).It may also be stored with the data being written into the buffer unit being returned, and be in and " account for With ", " busy " or " superseded " state.The metadata information that CPU 1 is provided according to CPU 0, continues to be managed buffer unit.
Embodiment eight
Fig. 9 is the flow chart according to the processing read command of the embodiment of the present application.Distributor 230 is received from host and is come from The read command of host, the logical address accessed according to read command, by read command distribute to the CPU for handling caching task it One (referring to Fig. 9, step 910).As an example, the ranges of logical addresses that read command accesses falls completely within and (belongs to) CPU 0 and managed The ranges of logical addresses of reason, thus the write order is distributed to CPU 0 and handled by distributor 230.As another example, read command The ranges of logical addresses of access falls into the ranges of logical addresses (for example, region 302) that CPU 0 is managed and CPU 1 is managed The ranges of logical addresses (for example, region 304) (referring also to Fig. 3) of reason, distributor 230, which distributes to the read command, manages its access One of the CPU 0 and CPU 1 of ranges of logical addresses processing.
Next, CPU 0 checks whether the ranges of logical addresses of read command to be processed has exceeded patrolling of oneself being managed Address range is collected (referring to Fig. 9, step 920).If the ranges of logical addresses of read command falls completely within itself and is managed logically Location range, then continue checking for whether read command has hit buffer unit that CPU 0 is managed (referring to Fig. 9, step 930).Pass through The logical address of the ranges of logical addresses and buffer unit that compare read command identifies whether read command hits buffer unit.It can be with Understand that ground, read command can be split as multiple subcommands, the ranges of logical addresses of each subcommand is no more than a buffer unit Corresponding ranges of logical addresses.
If read command or its subcommand (hereinafter referred to as " read command ") have hit buffer unit, obtains and read from buffer unit The accessed data of order, and it is supplied to host (referring to Fig. 9, step 932).For example, by between DRAM 110 and host Initiate DMA transfer.It is corresponding physically according to the acquisition of the ranges of logical addresses of read command if read command miss buffer unit Location (referring to Fig. 9, step 940), and reads data from NVM chips according to physical address and is supplied to host (referring to Fig. 9, step It is rapid 942).And optionally, buffer unit also is distributed for read command, the data read from NVM chips is used in combination to replace buffer unit In data (referring to Fig. 9, step 944).
And if the ranges of logical addresses of read command has exceeded the ranges of logical addresses that CPU 0 is managed itself, CPU 0 to its Ranges of logical addresses needed for his CPU request temporary control and education read command is (referring to Fig. 9, step 950).In order to ask buffer unit, CPU 0 provides the ranges of logical addresses for belonging to region 304 (referring also to Fig. 3) for needing to access to CPU 1.Next, CPU 1 is examined Look into whether received ranges of logical addresses has hit one or more buffer units (referring to Fig. 9, step 960).And CPU 1 The metadata (including address in DRAM, state etc.) of the buffer unit of hit is sent to CPU 0.If CPU 1 is received Some or all of ranges of logical addresses miss buffer unit, to CPU 0 provide ranges of logical addresses miss buffer unit Instruction.
For the buffer unit (either CPU 0 oneself maintenances or from the borrows of CPU 1) of hit, CPU 0 is postponed The read command data to be accessed are obtained in memory cell, and are supplied to host (referring to Fig. 9, step 962).Miss is cached single The ranges of logical addresses (subcommand from read command or read command) of member, then according to the acquisition pair of the ranges of logical addresses of read command The physical address answered (referring to Fig. 9, step 970), and reads data from NVM chips according to physical address and is supplied to host (referring to Fig. 9, step 972).
And optionally, the ranges of logical addresses that buffer unit is asked in response to CPU 0, for miss buffer unit Ranges of logical addresses, CPU 1 also distributes buffer unit for it, and the metadata of the buffer unit distributed is sent to CPU 0. CPU 0 reads data from NVM chips and is supplied to host in response to buffer unit miss, and with being read from NVM chips The data that data are replaced in buffer unit (referring to Fig. 9, step 974), then give back buffer unit to CPU 1 (referring to Fig. 9, step 964)。
Embodiment nine
Figure 10 is the flow chart according to the power down process of the embodiment of the present application.According to an embodiment of the present application, in " occupancy " Stored in the buffer unit of state be not yet written into NVM chips but to host acknowledgement write order processing complete data ( Referring to Fig. 5).When solid storage device meets with unexpected power down, the data in backup buffer unit are needed, and also need to back up The metadata of buffer unit, after having restored Backup Data, buffer unit can be reused.
When being abnormal power down, each CPU will receive the instruction to powered-off fault.Each CPU terminates not yet processing and completes (example Such as, not yet indicate that processing is completed to host) read/write command processing, and start power down process flow.
In power down process flow, NVM cores are written in the respective buffer unit for needing to back up and its metadata by each CPU The log area of piece.Buffer unit needs in " occupancy " state back up.And be in the buffer unit of " free time " state because Without containing valid data without backup.For being in the buffer unit of " busy " state, data therein correspond to not yet to The data of the write order of host acknowledgement, thus need not backup.For being in the buffer unit of state " in eliminating ", may wait for eliminating Process is completed, and buffer unit becomes " free time " state, and need not backup；Also it can stop selection process, and by the shape of buffer unit State is set as " occupying ", and needs to back up it.It is to be appreciated that can be that buffer unit safeguards other in other embodiments State, the buffer unit in other states may need backup or nothing to be backed up (referring also to Fig. 5).
Referring to Figure 10, if there is the metadata borrowed from other CPU in the respective metadata of CPU, after power down flow starts, The metadata of borrow is given back first.For example, CPU 0 gives back the metadata borrowed from CPU 1 to CPU 1 (referring to Figure 10, step P1), CPU 1 gives back the metadata borrowed from CPU 2 to CPU 2 (referring to Figure 10, step P2), and CPU 2 will be borrowed from CPU 0 Metadata gives back CPU 0 (referring to Figure 10, step P3).The metadata of borrow is the metadata for the buffer unit that instruction borrows, It include the state of the address and buffer unit in DRAM 110 of the buffer unit borrowed.
By taking CPU 0 as an example, in response to receive CPU 2 return metadata, CPU 0 by itself metadata 0 (referring also to Fig. 4) it can recognize that itself needs the quantity of the buffer unit backed up (referring to Figure 10, step P3).Need the buffer unit backed up, example It is in the buffer unit of " occupancy " state in this way.Itself is needed the quantity of the buffer unit backed up to notify multiple CPU's by CPU 0 Next CPU (for example, CPU 1) (referring to Figure 10, step P4) in sequence.
Inform the quantity for the buffer unit that next CPU is backed up itself, it is therefore intended that next CPU is made to know to wait for for storing The log area of the buffer unit of backup or the initial address of memory space.According to an embodiment of the present application, multiple CPU share day Will area.Most preceding CPU (for example, CPU 0) is sorted in multiple CPU using the designated position of log area as of backup buffer unit Beginning address.And the buffer unit quantity that CPU 1 is backed up according to the needs that CPU 0 is provided, calculate CPU 0 for back up caching singly The required buffer size of member, and determine the initial address from the backup buffer unit in log area.And CPU 1 will be received The buffer unit quantity that backs up of needs and itself buffer unit quantity to back up it is cumulative, and inform in multiple CPU Next CPU (for example, CPU 2).By this method, each CPU will know the starting of the backup buffer unit certainly in log area Address.Last CPU (for example, CPU 2 in Figure 10) identification storage units to be backed up in multiple CPU and according to from previous The number of memory cells to be backed up that CPU (for example, CPU 1) is obtained determines the starting point of the backup buffer unit in log area Location, and buffer unit (referring to Figure 10, step P5) is backed up, and need not identify or accumulate number of memory cells to be backed up and transmission Give other CPU.
Knowing from after the initial address of backup buffer unit in log area, CPU backs up buffer unit, such as Buffer unit content and its metadata the write-in NVM chips that will be backed up.It optionally, will for handling the CPU of caching task Designated memory space of buffer unit and its metadata backup of backup in DRAM 110.Again by the specified storage of DRAM 110 sky Between monolithic backup to log area.
Each CPU for handling caching task, after all completing the backup to buffer unit, the power down of the embodiment of the present application Process flow is completed.For example, each CPU informs next CPU after completing to the backup of buffer unit, and sort in multiple CPU Last CPU (for example, CPU 2) confirms that the backup of all CPU for handling caching task is completed (referring to Figure 10, step P6 Or step P7).As another example, CPU 2 is specified to collect the backup progress of buffer unit.Other each CPU complete to delay After memory cell backup, CPU 2 is informed so that CPU 2 knows the backup progress of multiple CPU, and confirms that backup is completed.
Embodiment ten
Solid storage device receives I/O command from host.I/O command may indicate that it is atomic operation.Alternatively, host may indicate that Solid storage device meets atomicity requirement, for example, the general atomicity defined in NVMe agreements when handling I/O operation And/or power down atomicity.
Power down atomicity (AWUPF, the Atomic Write Unit Power Fail) requirement of NVMe agreements, solid-state storage Equipment ensures, if because power down or other error conditions cause command process to fail, to being associated with the logic unsuccessfully ordered The follow-up read command of address will obtain：(1) all legacy datas (original number in logical address that the write order being interrupted accesses According to)；Or the new data (total data that the write order being interrupted is written) that (2) are all.
The general atomicity (AWUN, Atomic Write Unit Normal) of NVMe agreements defines order and executes relatively In the atomicity of other orders, it is ensured that write order has atomicity relative to other read commands or write order.In addition to requiring to be written The data of NVM chips will not include the partial data of the partial data of newer command and other orders except newer command simultaneously, also Need to ensure will not include simultaneously in the data that the read command that host is sent out is read newer command partial data and newer command except Other order partial datas.
Figure 11 is write order (referred to as " the atomic write life for needing to meet atomicity according to the processing of the embodiment of the present application Enable ") flow chart.Solid storage device receives atom write order from host.According to the ranges of logical addresses accessed, atomic write is ordered Order is split as multiple subcommands so that the ranges of logical addresses that each subcommand accesses is no more than a buffer unit logically Location range.Next, obtaining pending subcommand (referring to Figure 11, step 1110).Subcommand may be from waiting list, Or split the obtained subcommand of atom write order.For the subcommand of acquisition, check whether it is affiliated write order In multiple still untreated subcommands, sort most preceding subcommand by logical address.Only when the subcommand of acquisition is affiliated writes In multiple still untreated subcommands of order, when subcommand most preceding by logical address sequence, just to the subcommand at Reason.To handle the subcommand, buffer unit is distributed for the subcommand, and lock the buffer unit of distribution (referring to Figure 11, step It is rapid 1120).The buffer unit being locked is no longer available for servicing the processing to other atom write orders, can not be assigned to it His buffer unit.Before locking operation success, which is not handled, also do not existed to the sequence of the atom write order Other subcommands after the subcommand are handled.
Distribution buffer unit failure is distributed if subcommand, for example, buffer unit is all locked, buffer unit is in " in eliminating " state or buffer unit have been locked, and suspend the processing to the subcommand, for example, by belonging to subcommand or its Write order be added waiting list.
In response to locking successfully, subcommand is handled, for example, initiate DMA transfer, by the corresponding data of subcommand from Host is transmitted to buffer unit, and the state of buffer unit is set as " occupying " or " busy ", also in the member of buffer unit The ranges of logical addresses that record subcommand is accessed in data is (referring to Figure 11, step 1130).
Next, it is determined whether being the corresponding buffer unit whole locking (ginseng of all subcommands of the atom write order See Figure 11, step 1140).If not locking all, according to the sequence of the logical address of not processed multiple subcommands, obtain Next subcommand is (referring to Figure 11, step 1110).It is all assigned with buffer unit if all subcommands of the atom write order And corresponding buffer unit is all locked, then can continue to complete the processing to these multiple subcommands (referring to Figure 11, step 1150) it, such as by the corresponding data of subcommand is moved from host to buffer unit, and in all sub- lives of the atom write order After enabling corresponding data that buffer unit all is written, indicate that the atomic write command process is completed to host.In the atom write order After all buffer unit is written in the corresponding data of all subcommands, the lock of all buffer units of the atom write order is distributed in release (referring to Figure 11, step 1160), to which these buffer units can be assigned to other atom write orders.
Optionally, step 1130 can be exchanged with the sequence of step 1140.In step 1130, for the preceding subcommand that sorts Buffer unit lock after, it is pending can other subcommands directly to be judged whether there is by step 1140.And return to step 1110 It is next subcommand distribution buffer unit in the multiple subcommands to sort with step 1120.And its buffer unit is locked successfully One or more subcommands, by execute step 1130 subcommand is handled.And step 1160, then it needs to be happened at step Judge in rapid 1140 be the atom write order the corresponding buffer unit of all subcommands all lock after.
According to an embodiment of the present application ten, when handling each atom write order, meet two conditions：
(1) sequence for pressing the value of the logical address of multiple subcommands of atom write order, for each subcommand distribution caching Unit simultaneously locks buffer unit, and only after locking successfully, next subcommand that the value of logical address sorts is pressed in just processing；
(2) after all buffer unit is written in data according to all subcommands of atom write order, just release is the same as the atom The lock of the corresponding buffer unit of all subcommands of write order.
Optionally, if during handling atom write order, pending atom read command or its subcommand are then being handled Also need not be processing atom read command or its subcommand without checking whether related cache unit is locked when atom read command And related cache unit is locked.It still optionally, also can be in the case where obtaining lock, just to original when handling atomic commands Sub- read command is handled.
Optionally, it sorts by logical address order for multiple subcommands to atom write order, it can be by logical address number The ascending sort of value, can also be by the descending sort of logical address numerical value.No matter use which kind of mode as the foundation of sequence, it is right In multiple atom write orders of processing, identical sortord is used.
According to an embodiment of the present application, in the case where meeting above-mentioned two condition, multiple atomic writes can be ordered The multiple subcommand parallel processings enabled.
Optionally, if atom write order indicate the physical address to be accessed, by the embodiment according to Figure 11 to logically The operation of location accordingly replaces with physical address.
Embodiment 11
Figure 12 is the write order flow chart for needing to meet atomicity according to the processing of the another embodiment of the application.Distributor 230 (referring also to Fig. 2) receive the atom write order from host from host, are accessed logically according to atom write order Atom write order is distributed to one of CPU for handling caching task (referring to Figure 12, step 1210) by location.As an example, former The ranges of logical addresses that sub- write order accesses falls into the ranges of logical addresses for (being less than or equal to) CPU 0 and having been managed (for example, area Domain 302) and the ranges of logical addresses (for example, region 304) (referring also to Fig. 3) that is managed of CPU 1, distributor 230 is by the original Sub- write order distributes to one of CPU 0 and CPU 1 of ranges of logical addresses for managing that it is accessed processing (for example, CPU 0).
Next, ranges of logical addresses of the CPU 0 according to access, multiple subcommands are split as by atom write order.Every time It obtains to sort in the not processed multiple subcommands for belonging to an atom write order and be handled (referring to figure in most preceding subcommand 12, step 1220).If the subcommand obtained not sorts in most preceding subcommand, suspend the processing to the subcommand, for example, It is added into waiting list.
Next, CPU 0 checks whether the ranges of logical addresses of subcommand to be processed has exceeded patrolling of oneself being managed Address range is collected (referring to Figure 12, step 1230).If the ranges of logical addresses of subcommand falls completely within the logic itself managed Address range, CPU 0 distribute buffer unit in DRAM for subcommand, and the buffer unit to be distributed locks (referring to Figure 12, step It is rapid 1240).In response to locking successfully, distributed buffer unit is written into (referring to Figure 12, step in the corresponding data of subcommand 1250)。
If the ranges of logical addresses of subcommand has surmounted the ranges of logical addresses that CPU 0 is managed itself, CPU 0 to other Ranges of logical addresses needed for CPU request temporary control and education write order is (referring to Figure 12, step 1232).For example, subcommand will access Logical address region 304, buffer units of the CPU 0 to the requests of CPU 1 for region 304.Buffer unit is being obtained from CPU 1 Afterwards, which is distributed to subcommand by CPU 0, and the buffer unit to be distributed locks (referring to Figure 12, step 1240), sound Distributed buffer unit should be written into (referring to Figure 12, step 1250) in the corresponding data of subcommand in locking successfully.
To distribute buffer unit, also CPU 0 also checks for the state of buffer unit (referring also to Fig. 5).If the logic of subcommand Address range has hit buffer unit, then is the buffer unit of subcommand distribution hit.In the feelings of any buffer unit of miss Under condition, (it is referred to as " write order ") application buffer unit for the write order or its subcommand.
Next, it is determined whether being the corresponding buffer unit whole locking (ginseng of all subcommands of the atom write order See Figure 12, step 1260).If not locking all, the not processed multiple subcommands for belonging to same atom write order are obtained The most preceding next subcommand of sequence of logical address simultaneously handles next subcommand (referring to Figure 12, step 1220).If this All subcommands of atom write order are all assigned with buffer unit and corresponding buffer unit is all locked, in response to all Data corresponding to subcommand are all written into buffer unit, indicate that the atomic write command process is completed (referring to Figure 12, step to host It is rapid 1280).After all buffer unit is written in the corresponding data of all subcommands of the atom write order, the atom is distributed in release The lock of all buffer units of write order (referring to Figure 12, to which these buffer units can be assigned to other write by step 1270) Order.And the buffer unit for being borrowed from other CPU, after the lock of buffer unit is released, CPU 0 returns to other CPU The buffer unit also borrowed is (referring to Figure 12, step 1290).
It should be understood that give back buffer unit, what CPU 0 was indicated to CPU 1 is the metadata information (example of buffer unit Such as, address of the buffer unit in DRAM).It may also be stored with the data being written into the buffer unit being returned, and be in " occupancy ", " busy " or " superseded " state.The metadata information that CPU 1 is provided according to CPU 0 continues to carry out pipe to buffer unit It manages (referring also to Fig. 4).
Optionally, if atom write order indicate the physical address to be accessed, by the embodiment according to Figure 12 to logically The operation of location accordingly replaces with physical address.
Embodiment 12
Figure 13 is the schematic diagram according to the atomic commands of the embodiment of the present application.Figure 14 and Figure 15 is the atomic write for handling Figure 13 The schematic diagram of buffer unit in command procedure.Referring to Figure 13, solid storage device receives atom write order A and original from host Sub- write order B.Atom write order A includes 3 subcommands (X (t1), X+1 (t5) and X+2 (t3)), and atom write order B includes 3 Subcommand (X (t4), X+1 (t2) and X+2 (t6)).In fig. 13, subcommand is indicated by each box, for example, being indicated with X (t1) One of subcommand, X indicate the logical address that subcommand accesses, the time of the t1 instruction acquisitions subcommand, and number Size indicates chronological order.
The t1 moment obtains the subcommand X (t1) of atom write order A.By logical address order processing atom write order A's Multiple subcommands.Due to subcommand X (t1) be atom write order A not yet processed multiple subcommands in logical address sort Most preceding subcommand can be handled subcommand X (t1).According to logical address X applications to buffer unit 910, to caching (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240) unit 910 locks.In Figure 14, buffer unit 1410 is right The lock A (t1) answered indicates that the lock of the buffer unit belongs to atom write order A, also records it in the metadata of buffer unit 1410 Logical address is X.It is to be appreciated that the lock recorded in the metadata can only indicate the existence of lock, without indicating the lock institute The object of category.
Optionally, it locks for application buffer unit 1410 and to buffer unit 1410, is initiated on buffer unit 1410 Selection process, buffer unit 1410 are changed into " free time " state (referring also to Fig. 5).
The t2 moment obtains the subcommand X+1 (t2) of atom write order B.By logical address order processing atom write order B Multiple subcommands.Since in multiple subcommands of atom write order B, logical address sorts preceding subcommand X (t4) not yet It is handled, is unable to start to process subcommand X+1 (t2) at this time.
The t3 moment obtains the data of the subcommand X+2 (t3) of atom write order A.Atom is handled by logical address order Multiple subcommands of write order A.Due in multiple subcommands of atom write order A, logical address sorts preceding subcommand X+1 (t5) still not processed, it is unable to start to process subcommand X+2 (t3) at this time.
The t4 moment obtains the subcommand X (t4) of atom write order B.It is more by logical address order processing atom write order B A subcommand.Subcommand X (t4) is in not yet processed multiple subcommands of atom write order B, before logical address sequence most Subcommand, thus subcommand X (t4) can be handled.Apply for buffer unit for subcommand X (t4).Since subcommand X (t4) is visited It asks logical address X, has hit buffer unit 1410, but at this point, the buffer unit 1410 is locked A (t1), thus be son life The lock failure for enabling X (t4) request buffer units 1410, is unable to start to process subcommand X (t4) at this time.
The t5 moment receives the subcommand X+1 (t5) of atom write order A.By logical address order processing atom write order A's Multiple subcommands.Since subcommand X+1 (t5) is the most preceding son that sorts in the not yet processed multiple subcommands of atom write order A Order, thus buffer unit 1412 is arrived for subcommand X+1 (t5) applications, buffer unit 1412 is locked (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240).The corresponding lock A (t5) of buffer unit 1412 indicates that the lock of the buffer unit belongs to former Sub- write order A.
Since the 2nd subcommand X+1 (t5) application by logical address sequence for atom write order A is to lock, next The 3rd subcommand X+2 (t3) of atom write order A can be handled.Apply for buffer unit 1414 for subcommand X+2 (t3), and right Buffer unit 1414 locks (referring also to Figure 11, step 1120；Or referring to Figure 12, step 1240).
So far, all subcommands of atom write order A have all applied for buffer unit, and all lock success to buffer unit. (referring also to Figure 11, step after being all written into each buffer unit to the data corresponding to all subcommands of atom write order A 1150), indicate that (referring to Figure 12, step 1280), atomic write life is distributed in release for atom write order A processing completion to host Enable the lock of all buffer units of A (referring also to Figure 11, step 1160, or referring to Figure 12, step 1270), to these cachings Unit can be assigned to other write orders.
Next, the subcommand X (t4) of atom write order B is obtained, by the more of logical address order processing atom write order B A subcommand.Due to its be atom write order B multiple subcommands in logical address sort most preceding subcommand, be subcommand X (t4) apply buffer unit 1410, and lock successfully (referring to the lock B (t4) of Figure 15) (referring also to Figure 11, step 1120, Huo Zhecan See Figure 12, step 1240).Since the buffer unit application of the 1st subcommand X (t4) for atom write order B is to lock, next The 2nd subcommand X+1 (t2) that atom write order B can be handled arrives buffer unit 1412 for its application, and locks successfully (ginseng See the lock B (t2) of Figure 15) (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240).
Next the subcommand X+2 (t6) of atom write order B is got at the t6 moment.It is arrived for subcommand X+2 (t6) applications Buffer unit 1414 and lock successfully (referring to the lock B (t6) of Figure 15) (referring also to Figure 11, step 1120, or referring to Figure 12, step It is rapid 1240).
So far, all subcommands of atom write order B have all applied for buffer unit, and all lock success to buffer unit. (referring also to Figure 11, step after being all written into each buffer unit to the data corresponding to all subcommands of atom write order B 1150), indicate that (referring also to Figure 12, step 1280), the atomic write is distributed in release for atom write order B processing completion to host Order the lock of all buffer units of B (referring also to Figure 11, step 1160, or referring to Figure 12, step 1270).
Referring to table 2, the second row of table 2 shows effective result after the completion of the A execution of atom write order：In logical address It is that the data X (t1) that atom write order A is written (uses subcommand X here respectively in LBA (x), LBA (x+1) and LBA (x+2) (t1) data that the subcommand is written are indicated), X+1 (t5) and X+2 (t3).The third line of table 2 shows that atom write order B is held Effective result after the completion of row：It is that atom write order B is write respectively in logical address LBA (x), LBA (x+1) and LBA (x+2) The data X (t4) entered, X+1 (t2) and X+2 (t6).Be not in part thus it is guaranteed that in logical address X to X+2 ranges Logical address be the data of atom write order A write-in and part logical address be the B write-ins of atom write order data situation, it is real The atomicity of atomic write command process is showed.
Table 2
Embodiment 13
Figure 16 is the schematic diagram according to the atom write order of the another embodiment of the application.Figure 17, Figure 18 and Figure 19 are processing The schematic diagram of buffer unit in the atomic write command procedure of Figure 16.The original received from host referring to Figure 16, solid storage device Sub- write order C, atom write order D and atom write order E.Atom write order C is split as 3 subcommands (X (t1), X+1 (t5) With X+2 (t6)), atom write order D is divided into 3 subcommands (X (t7), X+1 (t8) and X+2 (t9)), and atom write order E is divided For 3 subcommands (X+1 (t2), X+2 (t3) and X+3 (t4)).
The t1 moment obtains the subcommand X (t1) of atom write order C.By logical address order processing atom write order C's Multiple subcommands.Due to subcommand X (t1) be atom write order C not yet processed multiple subcommands in logical address sort Most preceding subcommand can be handled subcommand X (t1).According to logical address X applications to buffer unit 1710, to caching (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240) unit 1710 locks.In Figure 17, buffer unit 1710 is right The lock C (t1) answered indicates that the lock of the buffer unit belongs to atom write order C, also records it in the metadata of buffer unit 1710 Logical address is X.
The t2 moment obtains the subcommand X+1 (t2) of atom write order E.By logical address order processing atom write order E Multiple subcommands.Due to subcommand X+1 (t2) be atom write order E not yet processed multiple subcommands in logical address The most preceding subcommand of sequence, can be handled subcommand X+1 (t2).Apply for buffer unit 1712 according to logical address X+1, And (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240) (referring to Figure 17) is locked to buffer unit 1712.Figure In 17, the corresponding lock E (t2) of buffer unit 1712 indicates that the lock of the buffer unit belongs to atom write order E, also in buffer unit It is X+1 that its logical address is recorded in 1712 metadata.
The t3 moment obtains the subcommand X+2 (t3) of atom write order E.By logical address order processing atom write order E Multiple subcommands.It, can since subcommand X+2 (t3) is the not yet processed subcommand of the last one of atom write order E To handle subcommand X+2 (t3).Apply for buffer unit 1714 according to logical address X+2, and buffer unit 1714 is added Lock (referring to Figure 17) (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240).In Figure 17, buffer unit 1714 is right The lock E (t3) answered indicates that the lock of the buffer unit belongs to atom write order E, also records it in the metadata of buffer unit 1714 Logical address is X+2.
The t4 moment obtains the subcommand X+3 (t4) of atom write order E.By logical address order processing atom write order E Multiple subcommands.Due to subcommand X+3 (t4) be atom write order E not yet processed multiple subcommands in logical address The most preceding subcommand of sequence, can be handled subcommand X+3 (t4).According to logical address X+3 applications caching single 1716, and (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240) (referring to Figure 17) is locked to buffer unit 1716.Figure 17 In, the corresponding lock E (t4) of buffer unit 1716 indicates that the lock of the buffer unit belongs to atom write order E, also in buffer unit It is X+3 that its logical address is recorded in 1716 metadata.
So far, all subcommands for being atom write order E have all applied for buffer unit, and are all locked into buffer unit Work(.Data corresponding to all subcommands to atom write order E are all written into each buffer unit (referring also to Figure 11, step It is rapid 1150) after, indicate that atom write order E processing completes that (referring also to Figure 12, step 1280), the original is distributed in release to host The lock of all buffer units of sub- write order E is (referring also to Figure 11, step 1160, or referring to Figure 12, step 1270), to this A little buffer units can be assigned to other write orders.
The t5 moment obtains the subcommand X+1 (t5) of atom write order C.By logical address order processing atom write order C Multiple subcommands.Due to subcommand X+1 (t5) be atom write order C not yet processed multiple subcommands in logical address The most preceding subcommand of sequence, can be handled subcommand X+1 (t5).Apply for buffer unit 1712 according to logical address X+1, And (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240) (referring to Figure 18) is locked to buffer unit 1712.Figure In 18, the corresponding lock C (t5) of buffer unit 1712 indicates that the lock of the buffer unit belongs to atom write order C, also in buffer unit It is X+1 that its logical address is recorded in 1712 metadata.
The t6 moment obtains the subcommand X+2 (t6) of atom write order C.By logical address order processing atom write order C Multiple subcommands.Due to subcommand X+2 (t6) be atom write order C not yet processed multiple subcommands in logical address The most preceding subcommand of sequence, can be handled subcommand X+2 (t6).Apply for buffer unit 1714 according to logical address X+2, And (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240) (referring to Figure 18) is locked to buffer unit 1714.Figure In 18, the corresponding lock C (t6) of buffer unit 1714 indicates that the lock of the buffer unit belongs to atom write order C, also in buffer unit It is X+2 that its logical address is recorded in 1714 metadata.
So far, all subcommands for being atom write order C have all applied for buffer unit, and are all locked into buffer unit Work(.Data corresponding to all subcommands to atom write order C are all written into each buffer unit (referring also to Figure 11, step It is rapid 1150) after, indicate that atom write order C processing completes that (referring also to Figure 12, step 1280), the original is distributed in release to host The lock of all buffer units of sub- write order C, to these buffer units can be assigned to other write orders (referring also to Figure 11, Step 1160, or referring to Figure 12, step 1270).
The T7 moment obtains the subcommand X (t7) of atom write order D.By logical address order processing atom write order D's Multiple subcommands.Due to subcommand X (t7) be atom write order D not yet processed multiple subcommands in logical address sort Most preceding subcommand can be handled subcommand X (t7).Apply for buffer unit 1710 according to logical address X, and to caching Unit 1710 locks (referring to Figure 19) (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240).In Figure 19, caching The corresponding lock D (t7) of unit 1710 indicates that the lock of the buffer unit belongs to atom write order D, also in first number of buffer unit 1710 It is X that its logical address is recorded in.
The T8 moment obtains the subcommand X+1 (t8) of atom write order D.By logical address order processing atom write order D Multiple subcommands.Due to subcommand X+1 (t8) be atom write order D not yet processed multiple subcommands in logical address The most preceding subcommand of sequence, handles subcommand X+1 (t8).Apply for buffer unit 1712 according to logical address X+1, and right Buffer unit 1712 locks (referring to Figure 19) (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240).In Figure 19, The corresponding lock D (t8) of buffer unit 1712 indicates that the lock of the buffer unit belongs to atom write order D, also in buffer unit 1712 It is X+1 that its logical address is recorded in metadata.
The T9 moment obtains the subcommand X+2 (t9) of atom write order D.By logical address order processing atom write order D Multiple subcommands.Due to subcommand X+2 (t9) be atom write order D not yet processed multiple subcommands in logical address The most preceding subcommand of sequence, handles subcommand X+2 (t9).Apply for buffer unit 1714 according to logical address X+2, and right Buffer unit 1714 locks (referring to Figure 19) (referring also to Figure 11, step 1120, or referring to Figure 12, step 1240).In Figure 19, The corresponding lock D (t9) of buffer unit 1714 indicates that the lock of the buffer unit belongs to atom write order D, also in buffer unit 1714 It is X+2 that its logical address is recorded in metadata.
So far, all subcommands for being atom write order D have all applied for buffer unit, and are all locked into buffer unit Work(.Data corresponding to all subcommands to atom write order D are all written into each buffer unit (referring also to Figure 11, step It is rapid 1150) after, indicate that atom write order D processing completes that (referring also to Figure 12, step 1280), the original is distributed in release to host The lock of all buffer units of sub- write order D, to these buffer units can be assigned to other write orders (referring also to Figure 11, Step 1160, or referring to Figure 12, step 1270).
Referring to table 3, effective result after the completion of the second row atom write order E execution of table 3：In logical address LBA (X+ 1), in LBA (X+2) and LBA (X+3) it is respectively data X+1 (t2), X+2 (t3) and X+3 (t4) that atom write order E is written, And it is then the data X (t1) that atom write order C is written in logical address LBA (X).The third line of table 3 shows atomic write Effective result after the completion of ordering C to execute：It is atom write order respectively in logical address LBAX, LBA (X+1) and LBA (X+2) The data X (t1) that C is written, X+1 (t5) and X+2 (t6), and atom write order E is then remained at logical address LBA (X+3) The data X+3 (t4) being written.The fourth line of table 3 shows effective result after the completion of the D execution of atom write order：Logically It is the data X (t7), X+1 (t8) and X+2 that atom write order D is written respectively in location LBA (X), LBA (X+1) and LBA (X+2) (t9), the data X+3 (t4) that atom write order E is written and at logical address LBA (X+3) is then remained.
Table 3
Optionally if during handling atom write order, need to be located according to the embodiments herein of combination Fig. 7-Figure 19 Whether the atom read command of reason or its subcommand are locked then when handling atom read command without inspection related cache unit, Also related cache unit need not be locked for processing atom read command or its subcommand.Optionally, in processing atom read command When, just atom read command can also be handled in the case where obtaining lock.
By handling atom write order in a manner of disclosed above, disclosure satisfy that in NVMe agreements to power down atomicity The requirement of (AWUPF, Atomic Write Unit Power Fail), guarantee has been interrupted in power down or other error conditions writes behaviour When making, processing behavior of the solid storage device to write operation.Solid storage device ensures, if because of power down or other error conditions Command process is caused to fail, then will be obtained to the follow-up read command for being associated with the logical address unsuccessfully ordered：(1) all old Data (initial data in logical address that the write order being interrupted accesses)；Or (what is be interrupted writes the new data that (2) are all Order total data be written).
The above, the only specific implementation mode of the application, but the protection domain of the application is not limited thereto, it is any Those familiar with the art can easily think of the change or the replacement in the technical scope that the application discloses, and should all contain It covers within the protection domain of the application.Therefore, the protection domain of the application should be subject to the protection scope in claims.

Claims (10)

1. a kind of write command processing method, which is characterized in that including：
Receive the write order from host；
Write order is distributed to the first CPU among multiple CPU；
First CPU is that write order distributes buffer unit；
Distributed buffer unit is written in the data of write order by the first CPU；
Buffer unit is all written in response to the write order data to be written, the first CPU has been handled to host instruction write order At.
2. according to the method described in claim 1, it is characterized in that, further including：
According to the ranges of logical addresses that write order accesses, write order is distributed to the first CPU in multiple CPU.
3. according to the method described in claim 2, it is characterized in that, wherein,
If the ranges of logical addresses that write order accesses fully belongs to the ranges of logical addresses that the first CPU is managed, by write order point The first CPU of dispensing；And
If the first part for the ranges of logical addresses that write order accesses belongs to the ranges of logical addresses that the first CPU is managed, and writes The second part of the ranges of logical addresses of command access belongs to the ranges of logical addresses that the 2nd CPU is managed, by the write order Distribute to the first CPU or the 2nd CPU.
4. a kind of read command processing method, which is characterized in that including：
Receive the read command from host；
According to the ranges of logical addresses of read command, read command is distributed to the first CPU in multiple CPU；
If buffer unit is hit in read command, the first CPU obtains the data that read command is accessed from buffer unit, and is supplied to master Machine；
If read command miss buffer unit, the first CPU obtains corresponding physical address according to the ranges of logical addresses of read command, And data are read from memory according to physical address, and it is supplied to host.
5. according to the method described in claim 4, it is characterized in that, further including
If the ranges of logical addresses of read command is more than the ranges of logical addresses that the first CPU is managed, the first CPU is asked to the 2nd CPU Seek the ranges of logical addresses needed for temporary control and education read command；
First CPU checks whether read command has hit the buffer unit that the 2nd CPU is managed；If the 2nd CPU institutes are hit in read command The buffer unit of management, then the first CPU obtains the data that read command is accessed from buffer unit, and is supplied to host.
6. a kind of I/O command processing method, which is characterized in that including：
According to the address range that write order accesses, write order is distributed to the first CPU in multiple CPU；
First CPU obtains the right to use of one or more buffer units according to described address range from the 2nd CPU；
The buffer unit obtained from the 2nd CPU is written in the data that write order to be written by the first CPU；
Indicate that write order processing is completed；And
First CPU gives back the right to use from the 2nd CPU buffer units obtained to the 2nd CPU.
7. a kind of write order processing unit, which is characterized in that including：
Order receiver module, for receiving the write order from host；
Order distribution module, for write order to be distributed to the first CPU among multiple CPU；
Buffer unit distribution module, for making the first CPU be that write order distributes buffer unit；
Data write. module, for making the first CPU that the data of write order to be written to distributed buffer unit；
Command process completes indicating module, and buffer unit is all written for the data to be written in response to write order, makes the One CPU is completed to host instruction write order processing.
8. a kind of solid storage device, including control unit and NVM chips, the control unit includes host interface and for visiting Ask the Media Interface Connector of memory, host interface is used for host exchange command and data, which is characterized in that control unit further includes Distributor and multiple CPU, distributor are coupled to host interface, the I/O command of storage device are sent to for receiving host, and will I/O command distributes to one of multiple CPU；Control unit is additionally coupled to external memory, and external memory provides buffer unit；Control Component processed is additionally coupled to NVM chips.
9. solid storage device according to claim 8, which is characterized in that including：
Write order for receiving the write order from host, and is distributed to the first CPU among multiple CPU by distributor；
First CPU, for distributing buffer unit for write order；The data of write order are written to distributed buffer unit；And Buffer unit is all written in response to the write order data to be written, is completed to host instruction write order processing.
10. solid storage device according to claim 8 or claim 9, which is characterized in that control unit is for executing according to right It is required that the method described in one of 1-6.
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