CN108647168A - A kind of analog acquisition control system and method based on CPCI - Google Patents
A kind of analog acquisition control system and method based on CPCI Download PDFInfo
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- CN108647168A CN108647168A CN201810384293.6A CN201810384293A CN108647168A CN 108647168 A CN108647168 A CN 108647168A CN 201810384293 A CN201810384293 A CN 201810384293A CN 108647168 A CN108647168 A CN 108647168A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
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Abstract
The present invention relates to a kind of analog acquisition control system and method based on CPCI belong to aerospace test and emission control technical field.The present invention uses the SOPC design methods based on FPGA, realizes multinuclear data processing and parallel computation with one piece of FPGA, largely improves data operation efficiency and processing capacity；Soft-core processor and traditional fpga logic resource are subjected to interconnected by internal bus, bus piece inner sealing has high reliability height and stronger environmental suitability.
Description
Technical field
The present invention relates to a kind of analog acquisition control system and method based on CPCI belong to aerospace test and hair
Penetrate control technology field.
Background technology
With the raising of electric information product miniaturization and integration degree, high-precision control is increasingly becoming at this stage with acquisition
The trend of spacecraft development, high-accuracy data acquisition and control system can perceive tiny signal, be convenient for veneer and system
Grade fault diagnosis and health control；Constantly increase with load capacity in face of spacecraft volume simultaneously, is transmitted control by voltage merely
Signal will face the limitations such as cable is long, and transmission pressure drop is big.
Invention content
Present invention solves the technical problem that being：A kind of analog quantity based on CPCI is overcome the deficiencies of the prior art and provide to adopt
Collect control system and method, acquisition control precision is high, largely increases perception and controls the ability of tiny signal.
The technical scheme is that：
A kind of analog acquisition control system based on CPCI, the acquisition control system include FPGA, FPGA configuration circuit,
Power module, plug-and-play circuit, A/D converter circuit, DA conversion circuits and pci bus；DA conversion circuits include filtered electrical
Road；
The FPGA includes system clock generation module, Nios II embedded softwares core processor, AVALON buses and each
Class Interface IP Core；
All kinds of Interface IP Cores include PCI IP kernels, AD control IP kernels and DA control IP kernels, PCI IP kernels, AD controls
AVALON bus interface is carried on IP kernel and DA control IP kernels, for being connected with AVALON buses；
The system clock generation module is for receiving onboard crystal oscillator clock, and the onboard crystal oscillator clock to receiving point
Multiplex operation clock is generated after frequency or frequency multiplication, work clock of the first via as PCI IP kernels in multiplex operation clock；Multichannel
The second tunnel in work clock controls the work clock of IP kernel as AD, and the third road in multiplex operation clock controls IP as DA
The work clock of core；Work clock of the 4th tunnel as Nios II embedded software core processors in multiplex operation clock；
AD control IP kernels acquire the voltage data in A/D converter circuit under the frequency of the second road work clock, and will adopt
The voltage data collected carries out data validity differentiation, if differentiating that result is that data are effective, by collected voltage data
By AVALON bus transfers to Nios II embedded software core processors the electricity is rejected if differentiation result is invalid data
It is acquired next time after pressure data；
The voltage data received is passed sequentially through AVALON buses, PCI by the Nios II embedded softwares core processors
IP kernel and pci bus are transmitted to CPCI controllers；CPCI controllers are according to the corresponding control of voltage data output received
Obtained control signal is passed sequentially through pci bus, PCI IP kernels and AVALON bus transfers extremely by signal, CPCI controllers again
The control signal received is carried out digital quantity by Nios II embedded software core processors, Nios II embedded softwares core processor again
Output controls IP kernel to DA after change；
DA controls IP kernel by the control signal transmission after the digital quantization received to DA conversion circuits, DA conversion circuits pair
Output current signal after control signal after the digital quantization received carries out DA conversions and filters；
The power module is used to convert electricity to FPGA, FPGA configuration circuit, plug-and-play circuit, A/D converter circuit and DA
Road powers；
The plug-and-play circuit is for protecting pci bus；
The FPGA configuration circuit is for providing required corresponding control signal and journey during FPGA electrifying startups
Sequence is moved.
A kind of the step of analog acquisition control method based on CPCI, this method includes：
(1) CPCI controllers initiate analog acquisition instruction set, and it includes analog acquisition that analog acquisition, which instructs set content,
The enabled instruction of mode, analog acquisition, analog acquisition instruction set is successively by pci bus, PCI IP kernels and AVALON buses
Nios II embedded software core processors are transmitted to, Nios II embedded softwares core processors pass through this analog acquisition instruction set
After local decoded operation, it is sent to AD control IP kernels；
(2) AD controls the transformation result that IP kernel acquires A/D converter circuit according to analog acquisition mode；
Analog acquisition mode includes single channel acquisition and circle collection, and it is logical can to carry out specified multi-channel A/D for wherein circle collection
Road cycle conversion；
(3) AD controls IP kernel and the transformation result of collected A/D converter circuit is passed sequentially through Nios II Embedded Soft Cores
Processor, AVALON buses, PCI IP kernels, pci bus are finally transmitted to CPCI controllers；
(4) according to the AD conversion received as a result, exporting corresponding control signal, control signal leads to CPCI controllers successively
Pci bus, PCI IP kernels and AVALON bus transfers are crossed to Nios II embedded software core processors；
(5) Nios II embedded softwares core processor by the control signal received by local decoded operation after, be sent to
DA controls IP kernel；
(6) DA controls IP kernel control DA conversion circuits start DA conversions according to control signal, and after DA is converted, DA is converted
DA is converted signal and exports by circuit controls IP kernel to DA, and DA controls IP kernel, and that DA converted signal is embedding by Nios II
Enter formula soft-core processor, AVALON buses, PCI IP kernels, pci bus and is finally transmitted to CPCI controllers；So far a secondary control is completed
Period processed.
The advantages of the present invention over the prior art are that：
(1) present invention uses the SOPC design methods based on FPGA, with one piece of FPGA realization multinuclear data processing and parallel
It calculates, largely improves data operation efficiency and processing capacity；By internal bus by soft-core processor with tradition
Fpga logic resource carries out interconnected, and bus piece inner sealing has high reliability height and stronger environmental suitability；
(2) data can be routed directly to place by all kinds of interface control methods by the form of encapsulation IP kernel in the present invention
It manages inside device, the efficient control of peripheral hardware is directly carried out by processor, whole development is integrated in inside one piece of FPGA, and processor calculates
Part configures flexibly, can be reconstructed according to demand and monokaryon support operating system, high cohesion lower coupling, flexibility are strong；
(3) present invention carries out data acquisition and distinguishing validity using high frequency clock in piece, largely improves number
According to the reliability of acquisition；By highly-precise filtering circuit, DA conversion circuit output accuracies are improved, to largely improve control
Efficiency processed；Pci bus control is realized in the way of IP kernel, is compared compared with conventional method and is avoided using interface control chip, reduced
System cost；
(4) A grades of hot plug acquisition and control cards of the μ that the present invention relates to a kind of based on CPCI, including CPCI interface modules, FPGA
Configuration circuit, FPGA embedded software core processor Nios II modules, power module, high-precision DA conversion circuits, multi-channel A/D acquisition
Circuit forms；High-precision D/A module is connected by spi bus interface with FPGA with multichannel A/D module, is run in FPGA
All kinds of IP kernels are unified to be controlled by SOPC embedded software core processors NiosII, and wherein AD/DA control IP kernels are received from PCI
It is acquired or exports after the trigger signal of bus, PCI IP kernels are responsible for completing the local decoding of pci bus.
A kind of A grades of high-precision controls of μ based on CPCI are designed to realize based on 4-20mA electric current loop precision controls with analog input card
System, control accuracy is up to 0.05%, by way of current loop control, realizes that long distance multi-channel is controlled without crushing parallel, simultaneously
It by high-accuracy voltage acquisition channel, detects and is controlled voltage, with corresponding rapid fire and test；
System sends control instruction to corresponding using the Nios II soft-core processors based on FPGA according to actual demand timesharing
IP kernel, IP kernel carries out data acquisition according to control, and the data of acquisition are transmitted to internal bus by internal bus interconnection module
AVALON is transmitted to soft-core processor by internal bus AVALON, and application layer program, which writes data into, is pre-designed address
In register, when pci interface read-write arrives, pci interface IP kernel is controlled, pci bus is sent data to.
Further, further include all kinds of Interface IP Cores, including ADC interface IP kernel, DAC Interface IP Cores, pci interface IP kernel.
Further, multi-channel A/D control IP kernel is acquired by the way of configurable acquisition mode, can be configured to single-pass
Road acquisition, circle collection both of which, wherein circulation pattern can carry out the acquisition conversion of multi-channel A/D channel cycle, and circle collection is logical
Road starting channel can be configured by application layer program.
Further, IP kernel is controlled using being acquired by way of can configure acquisition mode multi-channel A/D, can be configured to
Single channel acquisition, circle collection both of which, wherein circulation pattern can carry out the acquisition conversion of multi-channel A/D channel cycle, and cycle is adopted
Collection channel starting channel can be configured by application layer program.
Further, system clock generation module is worked using multiplex operation clock is generated after external crystal-controlled oscillation frequency dividing per road
Work clock of the clock as all kinds of Interface IP Cores, all kinds of Interface IP Cores carry out data acquisition under this clock frequency, will acquire
Data be compared, judge whether comparing result meets data validity criterion, if satisfied, comparison result is then passed through inside
Bus bar module transfer is to internal bus AVALON；Otherwise, the data of acquisition are regarded as invalid data, are carried out next time after rejecting
Acquisition.
A kind of A grades of hot plug acquisition and control cards of μ based on CPCI, including FPGA, FPGA configuration circuit, power module, heat
Plug circuit module, multichannel A/D converter circuit, high-precision DA conversion circuits and pci bus module；FPGA is completed to multi-channel A/D
The control of conversion circuit, high-precision DA conversion circuits, while realizing that pci bus interface, power module are completed according to standard time sequence
The onboard secondary power supply power supply of acquisition and control card, FPGA configuration circuit provide required corresponding control during FPGA electrifying startups
Signal processed and program are moved；The hot plugging protection of acquisition and control card is realized by plug-and-play circuit；
Including system clock generation module, embedded software core processor Nios II, application layer program, internal bus
AVALON and all kinds of Interface IP Cores composition；Nios II are bridged by internal bus AVALON and Interface IP Core；System clock is given birth to
At module, for system, other building blocks provide work clock；Run on the application layer program in the soft-core processor of Nios II
Control instruction is sent to corresponding IP kernel according to actual demand, and IP kernel carries out data acquisition according to control, and the data of acquisition pass through
Internal bus interconnection module is transmitted to internal bus AVALON, and soft-core processor is transmitted to by internal bus AVALON, application
Layer program writes data into the register for being pre-designed address, when pci interface read-write arrives, controls pci interface IP
Core sends data to pci bus.
All kinds of Interface IP Cores include ADC interface IP kernel, DAC Interface IP Cores, pci interface IP kernel.
Multi-channel A/D is controlled IP kernel and is acquired by the way of configurable acquisition mode, be can be configured to single channel acquisition, is followed
Ring acquires both of which, and wherein circulation pattern can carry out the acquisition conversion of multi-channel A/D channel cycle, and the starting of circle collection channel is logical
Road can be configured by application layer program.
System clock generation module after external crystal-controlled oscillation frequency dividing using multiplex operation clock is generated, per road work clock as each
The work clock of class Interface IP Core, all kinds of Interface IP Cores carry out data acquisition under this clock frequency, and the data of acquisition are carried out
It compares, judges whether comparing result meets data validity criterion, if satisfied, comparison result is then passed through the mutual gang mould of internal bus
Block is transmitted to internal bus AVALON；Otherwise, the data of acquisition are regarded as invalid data, are acquired next time after rejecting.
Design high-precision filter ensures that DA output accuracies can reach A grades of μ.
Hot plug protection circuit is designed, the Hot Plug Capability of board is realized on the basis of ensureing board safety.
Description of the drawings
Fig. 1 is the system composition schematic diagram of the present invention.
Specific implementation mode
Below in conjunction with the accompanying drawings and example elaborates to the present invention.
A grades of hot plug acquisition and control card designs of μ based on CPCI are as shown in Figure 1, total system completes aircraft data
Acquisition and testing and control, system include system clock generation module (System Clock Generator), at Embedded Soft Core
Manage device (Nios II), sorts of systems and User Defined IP kernel.Wherein embedded software core processor is for controlling all kinds of interface IP
Core, to obtain required Various types of data source in pci bus.
FPGA drives each module to work by external 50MB system clocks, since clock needed for each module is different, by adopting
50MB external clocks are divided with system clock generation module (System Clock Generator, abbreviation SCG), are provided
Go out all kinds of frequency clocks to be used for each module in the inside FPGA, wherein provide all the way 150MB clocks for AVALON buses and interior
Portion's interconnection uses, remaining provides frequency-dividing clock for increasing reliability according to each Interface IP Core situation.
Internal system, as external interface control unit, completes the driving of all kinds of interfaces using Nios II soft-core processors
Control and data routing, data include radar seeker analog acquisition, the control of master/slave driving motor.Soft-core processor with it is each
It is bridged by internal bus master controller (AVALON Master) between class IP kernel.
Interface IP Core part includes from the interface IP of controller (AVALON Slave) based on AVALON buses using all kinds of
Multi-channel A/D C control interfaces IP, high-precision DAC control interfaces IP, pci bus interface, wherein ADC interface IP need to carry out in data
Hold verification, if institute's gathered data meets external voltage range, the data are effective.
The advantage of the design is embodied in：
(1) passed through using Nios II soft-core processors are added inside FPGA by the SOPC design methods based on FPGA
Soft-core processor completes the routing and operation to external data, and development cost is low；
(2) soft-core processor supports all kinds of IP kernels, interface IP can be cut and be reconstructed according to service condition, centainly
The versatility of hardware is realized in degree, while can directly operate peripheral hardware by processor, and control link is simplified efficiently；
(3) reliability design is carried out to all kinds of interface IP and data validity differentiates, largely improved data and adopt
The reliability of collection；
(4) global design is realized that development cost is low based on one piece of FPGA, and top level application program is with user logic IP's
Co-development can be more efficient completion embedded computer design and debugging efforts.
Embodiment
A kind of analog acquisition control system based on CPCI is as shown in Figure 1, for completing each analoglike before target seeker is penetrated
Measure examination and antenna transposition control, the acquisition control system include FPGA, FPGA configuration circuit, power module, plug-and-play circuit,
A/D converter circuit, DA conversion circuits and pci bus；DA conversion circuits include filter circuit；
The FPGA includes system clock generation module, Nios II embedded softwares core processor, AVALON buses and each
Class Interface IP Core；
All kinds of Interface IP Cores include PCI IP kernels, AD control IP kernels and DA control IP kernels, PCI IP kernels, AD controls
AVALON bus interface is carried on IP kernel and DA control IP kernels, for being connected with AVALON buses；
The system clock generation module is used to receive onboard 50MB crystal oscillator clocks, and when the onboard crystal oscillator to receiving
Multiplex operation clock is generated after clock frequency dividing, work clock of the first via as PCI IP kernels in multiplex operation clock；Multichannel work
Make the work clock that the second tunnel in clock controls IP kernel as AD, the third road in multiplex operation clock controls IP kernel as DA
Work clock；To generating the work clock of Nios II embedded software core processors after the onboard crystal oscillator clock frequency multiplication that receives；
AD control IP kernels acquire the voltage data in A/D converter circuit, data packet under the frequency of the second road work clock
Radar seeker supply voltage 12V, radar seeker supply voltage -12V, radar seeker supply voltage 3.3V, radar is included to lead
Take the lead supply voltage 5V, radar seeker supply voltage+15V, radar seeker supply voltage -15V, video voltage, straight
Stream amplifier zero drift, master/slave motor angle sensor voltage, by collected voltage data with reference to the normal voltage of precognition
Range carries out distinguishing validity (in ± 10% range of nominal voltage), will be collected if differentiating that result is that data are effective
Voltage data is by AVALON bus transfers to Nios II embedded software core processors, if differentiation result is invalid data,
It is acquired next time after rejecting the voltage data；
The AD acquisition translative mode supports single channel and circulation canal acquisition, single channel only to acquire fixed a certain logical
Road analog data；Circulation canal acquisition i.e. all analog datas of circle collection target seeker successively.
It is total that the target seeker voltage data received is passed sequentially through AVALON by the Nios II embedded softwares core processors
Line, PCI IP kernels and pci bus are transmitted to CPCI controllers；CPCI controllers are answered according to the voltage data the output phase received
Control signal, as controller receive radar seeker supply voltage 12V, radar seeker supply voltage -12V, radar guiding
Head supply voltage 3.3V, radar seeker supply voltage 5V, radar seeker supply voltage+15V, radar seeker power supply electricity
It is defeated after pressure -15V, video voltage, dc amplifier zero drift voltage, master/slave motor angle sensor voltage are normal
Go out corresponding target seeker main drive motor transposition control signal, " control target seeker rotates 5 ° 3 ' ", this control signal passes sequentially through PCI
Bus, PCI IP kernels and AVALON bus transfers are to Nios II embedded software core processors, at Nios II Embedded Soft Cores
It manages output after the control signal received is carried out digital quantization by device again and controls IP kernel to DA；
DA controls IP kernel and the target seeker main motor received is rotated to the control signal after 5 ° of 3 ' corresponding digital quantization
DA conversion circuits are transmitted to, output current signal, the current signal correspond to DA conversion circuits by this progress DA conversion and after filtering
Target seeker main motor rotates 5 ° 3 '；
The power module is used to convert electricity to FPGA, FPGA configuration circuit, plug-and-play circuit, A/D converter circuit and DA
Road powers；
The plug-and-play circuit is for protecting pci bus, for protecting CPCI modules in swapping process, with
Backboard pci bus connection control signal, data address line and power supply signal not because occur overvoltage or overcurrent in the case of burn
System；
The FPGA configuration circuit is for providing required corresponding control signal and journey during FPGA electrifying startups
Sequence is moved.
A kind of the step of analog acquisition control method based on CPCI, this method includes：
(1) CPCI controllers initiate analog acquisition instruction set, and it includes analog acquisition that analog acquisition, which instructs set content,
Mode, that is, single channel acquisition or the enabled instruction of circle collection, analog acquisition, enable each of the corresponding target seeker to be tested of instruction
Respectively enabled radar seeker supply voltage 12V, a analog quantity channel enabled radar seeker supply voltage -12V, enables
Radar seeker supply voltage 3.3V, enabled radar seeker supply voltage 5V, enabled radar seeker supply voltage+15V, make
Can radar seeker supply voltage -15V, enabled video voltage, enabled dc amplifier zero drift voltage, it is enabled it is main/
Auxiliary-motor angle-sensor voltage, analog acquisition instruction set is successively by pci bus, PCI IP kernels and AVALON bus transfers
To Nios II embedded software core processors, this analog acquisition instruction set is passed through local by Nios II embedded softwares core processors
After decoded operation, it is sent to AD control IP kernels；
(2) AD controls the transformation result that IP kernel acquires A/D converter circuit according to analog acquisition mode, i.e. radar seeker
Supply voltage 12V, radar seeker supply voltage -12V, radar seeker supply voltage 3.3V, radar seeker supply voltage
5V, radar seeker supply voltage+15V, radar seeker supply voltage -15V, video voltage, dc amplifier zero-bit
Drift voltage and master/slave motor angle sensor voltage；
(3) AD controls IP kernel and the transformation result of collected A/D converter circuit is passed sequentially through Nios II Embedded Soft Cores
Processor, AVALON buses, PCI IP kernels, pci bus are finally transmitted to CPCI controllers；
(4) CPCI controllers are differentiated according to the AD conversion result received, if there is the state of analog quantity exception,
Tester is then notified in a manner of alarm and stops current testing process；If all kinds of analog quantitys are normal, output is corresponding
Control signal, control master/slave driving motor and rotate different indexings according to the rotational angle flow being pre-designed, control signal according to
It is secondary to pass through pci bus, PCI IP kernels and AVALON bus transfers to Nios II embedded software core processors；
(5) Nios II embedded softwares core processor by the control signal received by local decoded operation after, be sent to
DA controls IP kernel；
(6) DA controls IP kernel control DA conversion circuits start DA conversions according to control signal, the corresponding rotational angle of output
Current signal is to master/slave driving motor, after DA is converted, DA conversion circuits by DA convert signal export give DA control IP
Core, DA control IP kernel by DA convert signal by Nios II embedded softwares core processor, AVALON buses, PCI IP kernels,
Pci bus is finally transmitted to CPCI controllers, and CPCI controllers, which receive, to be converted signal and represent master/slave motor according to control
Instruction turns to corresponding indexing, so far completes a controlling cycle.
(7) after master/slave motor goes to corresponding indexing, CPCI controllers initiate next period and initiate analog acquisition instruction
Collection carries out AD analog quantity differentiations again.
Unspecified part of the present invention belongs to common sense well known to those skilled in the art.
Claims (10)
1. a kind of analog acquisition control system based on CPCI, it is characterised in that：The acquisition control system includes FPGA, FPGA
Configuration circuit, power module, plug-and-play circuit, A/D converter circuit, DA conversion circuits and pci bus；
The FPGA includes system clock generation module, Nios II embedded softwares core processor, AVALON buses and all kinds of connects
Mouth IP kernel；
All kinds of Interface IP Cores include that PCI IP kernels, AD control IP kernels and DA control IP kernels, PCI IP kernels, AD control IP kernel
AVALON bus interface is carried on DA control IP kernels.
2. a kind of analog acquisition control system based on CPCI according to claim 1, it is characterised in that：DA conversion electricity
Road includes filter circuit.
3. a kind of analog acquisition control system based on CPCI according to claim 1 or 2, it is characterised in that：It is described
System clock generation module for receiving onboard crystal oscillator clock, and it is raw after the frequency dividing of the onboard crystal oscillator clock to receiving or frequency multiplication
At multiplex operation clock, work clock of the first via as PCI IP kernels in multiplex operation clock；In multiplex operation clock
Second tunnel controls the work clock of IP kernel as AD, when the third road in multiplex operation clock controls the work of IP kernel as DA
Clock；Work clock of the 4th tunnel as Nios II embedded software core processors in multiplex operation clock.
4. a kind of analog acquisition control system based on CPCI according to claim 3, it is characterised in that：AD controls IP
Core acquires the voltage data in A/D converter circuit under the frequency of the second road work clock, and by collected voltage data into
Row data distinguishing validity is passed collected voltage data by AVALON buses if differentiating that result is that data are effective
Transport to Nios II embedded software core processors, if differentiation result is invalid data, reject carry out after the voltage data it is next
Secondary acquisition.
5. a kind of analog acquisition control system based on CPCI according to claim 3, it is characterised in that：Described
It is total that the voltage data received is passed sequentially through AVALON buses, PCI IP kernels and PCI by Nios II embedded softwares core processors
Line is transmitted to CPCI controllers；CPCI controllers are according to the corresponding control signal of voltage data output received, CPCI controls
It is embedded to Nios II that obtained control signal is passed sequentially through pci bus, PCI IP kernels and AVALON bus transfers by device again
Soft-core processor, output is to DA after the control signal received is carried out digital quantization by Nios II embedded softwares core processor again
Control IP kernel.
6. a kind of analog acquisition control system based on CPCI according to claim 3, it is characterised in that：DA controls IP
Core is by the control signal transmission after the digital quantization received to DA conversion circuits, and DA conversion circuits are to the digital quantization that receives
Output current signal after control signal afterwards carries out DA conversions and filters.
7. a kind of analog acquisition control system based on CPCI according to claim 3, it is characterised in that：The electricity
Source module is used to power to FPGA, FPGA configuration circuit, plug-and-play circuit, A/D converter circuit and DA conversion circuits.
8. a kind of analog acquisition control system based on CPCI according to claim 3, it is characterised in that：The heat
Plug circuit is for protecting pci bus.
9. a kind of analog acquisition control system based on CPCI according to claim 3, it is characterised in that：Described
FPGA configuration circuit is moved for providing required corresponding control signal and program during FPGA electrifying startups.
10. a kind of analog acquisition control method based on CPCI, it is characterised in that the step of this method includes：
(1) CPCI controllers initiate analog acquisition instruction set, and analog acquisition instruction set is successively by pci bus, PCI IP kernels
And AVALON bus transfers are to Nios II embedded software core processors, Nios II embedded softwares core processors are by this analog quantity
After acquisition instructions collection is by local decoded operation, it is sent to AD control IP kernels；
(2) AD controls transformation result of the IP kernel according to analog acquisition instruction set acquisition A/D converter circuit；
(3) AD controls IP kernel and the transformation result of collected A/D converter circuit is passed sequentially through the processing of Nios II Embedded Soft Cores
Device, AVALON buses, PCI IP kernels, pci bus are finally transmitted to CPCI controllers；
(4) according to the AD conversion received as a result, exporting corresponding control signal, control signal passes sequentially through CPCI controllers
Pci bus, PCI IP kernels and AVALON bus transfers are to Nios II embedded software core processors；
(5) Nios II embedded softwares core processor by the control signal received by local decoded operation after, be sent to DA control
IP kernel processed；
(6) DA controls IP kernel control DA conversion circuits start DA conversions, after DA is converted, DA conversion circuits according to control signal
It DA is converted into signal exports and control IP kernel to DA, DA controls IP kernel, and that DA converted signal is embedded by Nios II
Soft-core processor, AVALON buses, PCI IP kernels, pci bus are finally transmitted to CPCI controllers, and the analog quantity for completing CPCI is adopted
Collection control.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110704353A (en) * | 2019-09-30 | 2020-01-17 | 北京航空航天大学 | CPCI-ARINC429 hot plug system |
| CN110907693A (en) * | 2019-12-10 | 2020-03-24 | 航天新长征大道科技有限公司 | Compact peripheral interconnection bus board card |
| CN112941677A (en) * | 2021-01-29 | 2021-06-11 | 河南光远新材料股份有限公司 | Twisting machine voltage frequency division control method |
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| CN112941677B (en) * | 2021-01-29 | 2022-09-16 | 河南光远新材料股份有限公司 | Twisting machine voltage frequency division control method |
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