CN108631900A - The preposition of High Precision Time Stamps beats stamp method and system - Google Patents
The preposition of High Precision Time Stamps beats stamp method and system Download PDFInfo
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- CN108631900A CN108631900A CN201810817049.4A CN201810817049A CN108631900A CN 108631900 A CN108631900 A CN 108631900A CN 201810817049 A CN201810817049 A CN 201810817049A CN 108631900 A CN108631900 A CN 108631900A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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Abstract
Preposition the invention discloses High Precision Time Stamps beats stamp method and system, includes the following steps：When S1 data transmissions, detection data packet frame head；With S2 when detecting that frame head terminates to mark and do not start to received data packet content, just take the real time clock value at the moment as timestamp；By way of carrying out playing stamp before received data packet content, it avoids since traditional postposition beats the time fluctuation that stamp mode is brought since data packet length differs, the method of the present invention is also unified to beat stamp time standard simultaneously, reduce the differentiation come due to different data packet length different band, in addition, using high-precision crystal oscillator as counter, again to which timestamp be calculated indirectly when school, the accuracy of timestamp and stability greatly promote, the accuracy requirement for meeting modern information technologies for data of being more convenient for.
Description
Technical field
The present invention relates to network communication technology field, it particularly relates to High Precision Time Stamps it is preposition beat stamp method and
System.
Background technology
In current network communication, usually after the completion of data receiver, that is, after receiving a complete data packet, reading should
Time be used as " timestamp ", it is this beat stamp mode can be referred to as " postposition plays stamp ", and due to the length of data packet be with
Machine, it grows sometimes, short sometimes, " postposition plays stamp " just changes back and forth therewith in this way；With in network video and
Audio-frequency information increases, and it is more and more to greatly enhance frame so that the drawbacks of " postposition plays stamp " is also more and more obvious.
For the problems in the relevant technologies, currently no effective solution has been proposed.
Invention content
For above-mentioned technical problem in the related technology, the present invention proposes that the preposition of High Precision Time Stamps beats stamp method.
The technical proposal of the invention is realized in this way：
A kind of the preposition of High Precision Time Stamps beats stamp method, includes the following steps：When S1 data transmissions, detection data packet frame head；
With
S2 just takes the real time clock value at the moment when detecting that frame head terminates to mark and do not start to received data packet content
As timestamp.
Further, in step S1, realize that frame head synchronizes and frame head terminates to detect by high speed FPGA.
Further, in step S2, when detecting end level, three tasks of parallel starting：Read real time clock value
As timestamp, start the data that CRC check calculates, preparation record acquires.
Further, the frame head terminates 1,1 labeled as two neighboring high level in frame head.
Further, the real time clock value includes by IRIG-B codes decoding circuit from exterior I RIG-B code format clocks
The first time value section for the year, month, day, hour, min, seconds value that source resolution is got and pass through high-precision oscillating circuit provide clock
Realize the millisecond counted, microsecond, the second time value section of nanosecond value.
Further, the FPGA by FPGA carry two-port RAM respectively from the IRIG-B codes decoding circuit with
High-precision oscillating circuit reads real time clock value.
Further, the exterior I RIG-B codes format clock source is one in Beidou navigation, GPS, atomic clock, timing radio station
Kind.
Further, the resolution ratio of the high-precision oscillating circuit was 100 nanoseconds, primary described every the update of 100 nanoseconds
Second time value section, and be written in the real time clock value.
A kind of the preposition of High Precision Time Stamps beats stamp system, including following device：
Device is used for the detection data packet frame head in data transmission；With
Device is used to, when detecting that frame head terminates to mark and do not start to received data packet content, take the moment
Real time clock value is as timestamp.
Fpga chip on a kind of high-accuracy data collection card comprising a kind of the preposition of High Precision Time Stamps beats stamp system
System, which includes following device：
Device is used for the detection data packet frame head in data transmission；With
Device is used to, when detecting that frame head terminates to mark and do not start to received data packet content, take the moment
Real time clock value is as timestamp.
Beneficial effects of the present invention：By way of carrying out playing stamp before received data packet content, avoid due to passing
System postposition beats the time fluctuation that stamp mode is brought since data packet length differs, while the method for the present invention is also unified to beat stamp time mark
Standard reduces the differentiation come due to different data packet length different band, in addition, using high-precision crystal oscillator as counting
Device, then to which timestamp be calculated indirectly when school, the accuracy of timestamp and stability greatly promote, and are more convenient for meeting modern
Accuracy requirement of the information technology for data.
Description of the drawings
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is to play frame structure schematic diagram in stamp method and system according to the preposition of High Precision Time Stamps of the present invention；
Fig. 2 is to beat stamp method comparison schematic diagram with existing postposition according to the preposition stamp method of beating of High Precision Time Stamps of the present invention；
Fig. 3 is to beat stamp method in different frame lengths from existing postposition according to the preposition stamp method of beating of High Precision Time Stamps of the present invention
Beat stamp effect diagram；
Fig. 4 is the preposition reading structural representation for beating real time clock value in stamp method and system according to High Precision Time Stamps of the present invention
Figure.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained belong to what the present invention protected
Range.
As shown in Figs 1-4, a kind of the preposition of High Precision Time Stamps according to the ... of the embodiment of the present invention beats stamp method, including following
Step：When S1 data transmissions, detection data packet frame head；With
S2 just takes the real time clock value at the moment when detecting that frame head terminates to mark and do not start to received data packet content
As timestamp.
In the present embodiment, in step S1, realize that frame head synchronizes and frame head terminates to detect by high speed FPGA.
In the present embodiment, in step S2, when detecting end level, three tasks of parallel starting：Read real-time clock
It is worth as timestamp, the data for starting CRC check calculating, preparing record acquisition.
In the present embodiment, the frame head terminates 1,1 labeled as two neighboring high level in frame head.
In the present embodiment, the real time clock value include by IRIG-B codes decoding circuit from exterior I RIG-B code formats when
The first time value section for the year, month, day, hour, min, seconds value that clock source resolution is got and pass through high-precision oscillating circuit provide pulse
Realize the millisecond counted, microsecond, the second time value section of nanosecond value in source.
In the present embodiment, the two-port RAM that the FPGA is carried by FPGA is respectively from the IRIG-B codes decoding circuit
Real time clock value is read with high-precision oscillating circuit.
In the present embodiment, the exterior I RIG-B codes format clock source is in Beidou navigation, GPS, atomic clock, timing radio station
It is a kind of.
In the present embodiment, the resolution ratio of the high-precision oscillating circuit was 100 nanoseconds, updated primary institute every 100 nanoseconds
The second time value section is stated, and is written in the real time clock value.
A kind of the preposition of High Precision Time Stamps beats stamp system, including following device：
Device is used for the detection data packet frame head in data transmission；With
Device is used to, when detecting that frame head terminates to mark and do not start to received data packet content, take the moment
Real time clock value is as timestamp.
Fpga chip on a kind of high-accuracy data collection card comprising a kind of the preposition of High Precision Time Stamps beats stamp system
System, which includes following device：
Device is used for the detection data packet frame head in data transmission；With
Device is used to, when detecting that frame head terminates to mark and do not start to received data packet content, take the moment
Real time clock value is as timestamp.
As shown in Figure 1, frame head is continuous alternate 0 and 1 composition, frame head terminates to be continuous two high level " 1,1 "；Subsequently
It is the packet contents such as destination address；It attached 32 Frame Check Sequences behind frame；
As shown in Fig. 2, " preposition to play stamp " method of the invention is with current " postposition plays stamp " method, difference lies in the present invention is " preposition
Play stamp " method plays stamp by being carried out before received data packet content, and current " postposition plays stamp " method is in data packet
Appearance carries out playing stamp after finishing receiving, and it is exactly data in fact to receive same data packet and carry out the stamp lead time of beating that two kinds are beaten stamp mode
The duration of packet content, and the duration is then closely bound up with the length of data packet；
As shown in figure 3, shortest frame length is 64 bytes on Ethernet at present, maximum frame length is 1514 bytes, difference more than 20
Times.Certainly different network types, maximum length can be different, from " preposition to play stamp " method of the invention and current " postposition plays stamp "
Method is lower to different frame elongate member when playing stamp, and it is apparent that the beating of " postposition plays stamp " method stabs time difference alienation；
Specifically, showing frame head after recognizing the 8th byte 10101011B of frame head in " preposition to play stamp " method of the invention
Terminate, needs to play stamp immediately；This reaction speed requires very high, it is necessary to real-time tracking.To execute 3 operations parallel at this time：
Timestamp is beaten, starts CRC check calculating, prepare record data；Using high speed FPGA, by programming in logic, realize that frame head synchronizes
Terminate to detect with frame head；When detecting that frame head terminates to mark（Terminate level）When, three tasks of parallel starting：Read real-time clock
It is worth as timestamp, the data for starting CRC check calculating, preparing record acquisition；The real time clock value read i.e. current time
Timestamp of the absolute time as " preposition to play stamp "；
Secondly, during reading real time clock value as timestamp, as shown in figure 4, the two-port RAM carried using FPGA, high
Speed is realized the reading of real time clock value and is write；Clock circuit be analyzed and acquired by from IRIG-B code formats accurate year, month, day, when,
Minute, second value.Second millisecond below, microsecond, nanosecond value then pass through high-precision oscillating circuit and provide clock realization counting, best result
100 nanosecond of resolution.A real time clock value is just updated every this time, new value is written.
It can be seen that by means of the above-mentioned technical proposal of the present invention, stamp is played by being carried out before received data packet content
Mode, avoid since traditional postposition beats the time fluctuation that stamp mode is brought since data packet length differs, while the present invention
Method is also unified to beat stamp time standard, reduces the differentiation come due to different data packet length different band, in addition, using high-precision
Crystal oscillator is as counter, then to which timestamp be calculated indirectly when school, and the accuracy of timestamp and stability are significantly
It is promoted, the accuracy requirement for meeting modern information technologies for data of being more convenient for.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention god.
Claims (10)
1. a kind of the preposition of High Precision Time Stamps beats stamp method, which is characterized in that include the following steps：When S1 data transmissions, inspection
Measured data packet frame head；With
S2 just takes the real time clock value at the moment when detecting that frame head terminates to mark and do not start to received data packet content
As timestamp.
2. the preposition of High Precision Time Stamps according to claim 1 beats stamp method, which is characterized in that in step S1, pass through
High speed FPGA realizes that frame head synchronizes and frame head terminates to detect.
3. the preposition of High Precision Time Stamps according to claim 2 beats stamp method, which is characterized in that in step S2, work as inspection
When measuring end level, three tasks of parallel starting：Real time clock value is read to calculate, prepare as timestamp, startup CRC check
Record the data of acquisition.
4. the preposition of High Precision Time Stamps according to claim 3 beats stamp method, which is characterized in that the frame head terminates to mark
It is denoted as 1,1 of two neighboring high level in frame head.
5. the preposition of High Precision Time Stamps according to claim 3 beats stamp method, which is characterized in that the real time clock value
It include the year, month, day, hour, min being analyzed and acquired by from exterior I RIG-B code format clock sources by IRIG-B codes decoding circuit, second
The first time value section of value and by high-precision oscillating circuit provide clock realize the millisecond counted, microsecond, nanosecond value the
Two time value sections.
6. the preposition of High Precision Time Stamps according to claim 5 beats stamp method, which is characterized in that the FPGA passes through
Two-port RAM included FPGA reads real time clock value from the IRIG-B codes decoding circuit and high-precision oscillating circuit respectively.
7. the preposition of High Precision Time Stamps according to claim 5 beats stamp method, which is characterized in that the exterior I RIG-B
Code format clock source is one kind in Beidou navigation, GPS, atomic clock, timing radio station.
8. the preposition of High Precision Time Stamps according to claim 6 beats stamp method, which is characterized in that the high-precision concussion
The resolution ratio of circuit was 100 nanoseconds, when updating the primary second time value section 100 nanoseconds, and be written to described real-time
In clock value.
9. a kind of the preposition of High Precision Time Stamps beats stamp system, which is characterized in that including following device：
Device is used for the detection data packet frame head in data transmission；With
Device is used to, when detecting that frame head terminates to mark and do not start to received data packet content, take the moment
Real time clock value is as timestamp.
10. the fpga chip on a kind of high-accuracy data collection card, which is characterized in that before it includes a kind of High Precision Time Stamps
It sets and beats stamp system, which includes following device：
Device is used for the detection data packet frame head in data transmission；With
Device is used to, when detecting that frame head terminates to mark and do not start to received data packet content, take the moment
Real time clock value is as timestamp.
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| CN201810817049.4A CN108631900B (en) | 2018-07-24 | 2018-07-24 | Pre-stamping method and system of high-precision timestamp |
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| CN201810817049.4A CN108631900B (en) | 2018-07-24 | 2018-07-24 | Pre-stamping method and system of high-precision timestamp |
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| CN108631900A true CN108631900A (en) | 2018-10-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109828447A (en) * | 2018-12-26 | 2019-05-31 | 中核控制系统工程有限公司 | A kind of gateway communication data time synchronization method based on FPGA+ARM framework |
| CN109917637A (en) * | 2019-03-13 | 2019-06-21 | 清华四川能源互联网研究院 | A kind of data collecting card high precision time service method |
| CN110109673A (en) * | 2019-04-25 | 2019-08-09 | 武汉大学 | A kind of compiler detection device and method based on Beidou subnanosecond grade high-precision time service |
| CN111791232A (en) * | 2020-06-03 | 2020-10-20 | 中南民族大学 | Robot chassis control system and method based on time hard synchronization |
| WO2021238724A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Method and apparatus for transmitting timestamp information, and device and storage medium |
| CN114363390A (en) * | 2022-01-21 | 2022-04-15 | 西安羚控电子科技有限公司 | Unmanned aerial vehicle ground control system and control method |
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| CN109828447A (en) * | 2018-12-26 | 2019-05-31 | 中核控制系统工程有限公司 | A kind of gateway communication data time synchronization method based on FPGA+ARM framework |
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| CN111791232A (en) * | 2020-06-03 | 2020-10-20 | 中南民族大学 | Robot chassis control system and method based on time hard synchronization |
| CN114363390A (en) * | 2022-01-21 | 2022-04-15 | 西安羚控电子科技有限公司 | Unmanned aerial vehicle ground control system and control method |
| CN114363390B (en) * | 2022-01-21 | 2023-09-12 | 西安羚控电子科技有限公司 | Unmanned aerial vehicle ground control system and control method |
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