CN108630687B - Memory cell and nonvolatile memory - Google Patents
Memory cell and nonvolatile memory Download PDFInfo
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- CN108630687B CN108630687B CN201710152613.0A CN201710152613A CN108630687B CN 108630687 B CN108630687 B CN 108630687B CN 201710152613 A CN201710152613 A CN 201710152613A CN 108630687 B CN108630687 B CN 108630687B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
Abstract
The invention discloses a storage unit and a nonvolatile memory, wherein the storage unit comprises: a semiconductor substrate including an active region; the source region is positioned in the semiconductor substrate of the active region; the gate region comprises a floating gate and a control gate which are sequentially stacked on the source region and are insulated from each other, wherein at least part of the floating gate is positioned in the semiconductor substrate, and integral tunneling oxide layers are formed on two sides of the floating gate in the semiconductor substrate and between the floating gate and the source region; and the first drain region and the second drain region are respectively positioned in the semiconductor substrate of the active region at two sides of the floating gate. The invention solves the problem of large occupied area of the memory cell and can reduce the size of the nonvolatile memory.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor storage, in particular to a storage unit and a nonvolatile memory.
Background
The gate region of a conventional NOR flash memory cell is located between the source and drain regions, and the semiconductor layer between the source and drain regions may form a channel. When the NOR flash memory is programmed, high voltage is simultaneously applied to a control gate and a drain region of a memory cell for a certain time, a channel is conducted, and carriers in the channel jump to a floating gate through hot electron injection under the action of a transverse electric field and a longitudinal electric field. Since the occurrence of hot electron injection requires the memory cell to operate in a high voltage state, the channel length of the memory cell cannot be too short, limiting further scaling of the memory cell in the channel length direction.
In addition, in order to distinguish the different states of the memory cells "0" and "1" and to ensure that the memory cells have a sufficient retention and erase operation times at high temperatures for a long time, the memory cells are required to supply a sufficient current in the erased state ("1"), which requires the active regions of the memory cells to be large enough, thereby limiting further shrinkage of the memory cells in the channel width direction.
Disclosure of Invention
In view of the above, the present invention provides a memory cell and a nonvolatile memory, so as to reduce the area occupied by the memory cell and reduce the size of the nonvolatile memory.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, an embodiment of the present invention provides a memory cell, including:
a semiconductor substrate including an active region;
the source region is positioned in the semiconductor substrate of the active region;
the gate region comprises a floating gate and a control gate which are sequentially stacked on the source region and are insulated from each other, wherein at least part of the floating gate is positioned in the semiconductor substrate, and integral tunneling oxide layers are formed on two sides of the floating gate in the semiconductor substrate and between the floating gate and the source region;
and the first drain region and the second drain region are respectively positioned in the semiconductor substrate of the active region at two sides of the floating gate.
Further, the upper surface of the floating gate is flush with the upper surface of the semiconductor substrate.
Furthermore, the thickness of the floating gate is 100-350 nm.
Further, the width of the gate region is 20-80 nm along the arrangement direction of the first drain region, the gate region and the second drain region.
Further, the width of the active region is 28-65 nm in the direction perpendicular to the arrangement direction of the first drain region, the gate region and the second drain region.
Furthermore, the control gate and the word line of the nonvolatile memory are arranged in the same layer, and the control gate and the word line are integrally formed.
Further, the control gate and the semiconductor substrate are covered with insulating layers;
bit lines of the nonvolatile memory are arranged on the insulating layer;
the first drain region and the second drain region are electrically connected to the same bit line through a bit line contact hole.
Furthermore, an interlayer dielectric layer is arranged between the control gate and the floating gate.
Further, the interlayer dielectric layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially stacked.
Furthermore, side walls are formed on two sides of the control gate and the interlayer dielectric layer.
In another aspect, an embodiment of the present invention provides a nonvolatile memory, including:
a plurality of memory cells as described in the above aspect arranged in an array;
a plurality of word lines extending in a row direction and arranged in a column direction, each word line being electrically connected to control gates of the memory cells in the same row;
and a plurality of bit lines extending along the column direction and arranged along the row direction, wherein each bit line is electrically connected with the first drain region and the second drain region of the memory cell in the same column.
Further, the first drain region and the second drain region are electrically connected to the bit line through bit line contact holes; and one drain region and the corresponding bit line contact hole are shared between any two adjacent memory cells along the column direction.
The invention has the beneficial effects that: according to the storage unit and the nonvolatile memory provided by the invention, at least part of a floating gate of the storage unit in the nonvolatile memory is arranged in a semiconductor substrate, a source region is formed below the floating gate, tunneling oxide layers are formed on two sides of the floating gate in the semiconductor substrate and between the floating gate and the source region, and a first drain region and a second drain region are respectively formed in the semiconductor substrate on two sides of the floating gate, so that channels can be respectively formed between the first drain region and the source region and between the second drain region and the source region when the nonvolatile memory works, and therefore, a horizontal channel of the existing storage unit is converted into a vertical channel, namely, the length of an original horizontal channel is replaced by a vertical channel depth, and further the area occupied by the storage unit is further reduced in the length direction of the original horizontal channel; meanwhile, channels are formed on two sides of the floating gate, and one storage unit is formed by connecting two sub-storage units in parallel, so that almost twice current in an erasing state can be supplied, the area of an active region can be reduced, and the area occupied by the storage unit is further reduced in the width direction of the original horizontal channel. Therefore, the memory cell and the nonvolatile memory provided by the embodiment of the invention break through the restriction of two-dimensional size reduction of the memory cell on the horizontal plane, so that the nonvolatile memory can be possible to be 45nm or 32nm or even smaller.
Drawings
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
FIG. 1a is a schematic plan view of a conventional NOR-type flash memory;
FIG. 1b is a cross-sectional view of the NOR flash memory of FIG. 1a along line A-A';
FIG. 2 is a schematic cross-sectional view of a memory cell according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of a memory cell according to a second embodiment of the present invention;
fig. 4a is a schematic plan view of a memory cell array of a NOR flash memory according to a third embodiment of the present invention;
FIG. 4B is a cross-sectional view of the NOR flash memory of FIG. 4a along line B-B'.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
FIG. 1a is a schematic plan view of a conventional NOR-type flash memory; FIG. 1b is a cross-sectional view of the NOR flash memory of FIG. 1a along line A-A'. With reference to fig. 1a and 1B, the NOR flash memory includes a plurality of memory cells 10 (e.g., two adjacent memory cells a1 and B1 in a column) arranged in an array; a plurality of word lines 20 extending in the row direction and arranged in the column direction, each word line 20 being electrically connected to the control gates 16 of the memory cells 10 in the same row; and a plurality of bit lines 30 extending in the column direction and arranged in the row direction, wherein each bit line 30 is electrically connected with the drain regions D of the memory cells 10 in the same column through bit line contact holes 40. Wherein each memory cell may include a semiconductor substrate 11 including an active region 12; the gate region comprises a tunneling oxide layer 13, a floating gate 14, an interlayer dielectric layer 15 and a control gate 16 which are sequentially stacked on the semiconductor substrate 11; and the source region S and the drain region D are respectively positioned in the semiconductor substrate 11 of the active region 12 at two sides of the grid region. When programming a NOR flash memory, a high voltage is applied to the control gate 16 and the drain D of the memory cell 10 for a certain time, a horizontal channel between the source S and the drain D is turned on, and carriers in the horizontal channel jump to the floating gate 14 by hot electron injection under the action of a transverse electric field and a longitudinal electric field. Since the occurrence of hot electron injection requires the memory cell 10 to operate in a high voltage state, the channel length of the memory cell 10 cannot be too short, and further reduction of the memory cell in the channel length direction, i.e., reduction of the gate width W1(80 to 150nm), is restricted.
In addition, in order to distinguish the different states of the memory cells "0" and "1" and to ensure that the memory cell 10 has a sufficiently long retention and erase operation times at high temperatures, it is required that the memory cell 10 can supply a sufficiently large current in the erased state ("1"), which requires that the active region 12 of the memory cell 10 be sufficiently large, thereby limiting further shrinkage of the memory cell in the channel width direction, i.e., limiting the shrinkage of the active region width L1(70nm or 90nm, etc.).
In order to solve the above problems, the present invention provides a memory cell and a nonvolatile memory, and the solution of the present invention can be applied to various types of nonvolatile memories, and for example, a NOR flash memory is taken as an example for description, and the specific embodiments are as follows.
Example one
Fig. 2 is a schematic cross-sectional view of a memory cell according to an embodiment of the invention. As shown in fig. 2, the memory cell includes:
a semiconductor substrate 101 including an active region (not shown);
a source region 103 located in the semiconductor substrate 101 of the active region;
a gate region including a floating gate 104 and a control gate 105 which are sequentially stacked on the source region 103 and are insulated from each other, wherein at least a part of the floating gate 104 is located in the semiconductor substrate 101, and an integrated tunneling oxide layer 106 is formed on two sides of the floating gate 104 in the semiconductor substrate 101 and between the floating gate 104 and the source region 103;
and a first drain region 107 and a second drain region 108 respectively located in the semiconductor substrate 101 of the active region at both sides of the floating gate 104.
Illustratively, as shown in fig. 2, the floating gate 104 of the present embodiment may be partially located in the semiconductor substrate 101, and the thickness of the floating gate may be 100 to 350 nm; when the NOR flash memory works, vertical channels can be respectively formed between the first drain region 107 and the source region 103 and between the second drain region 108 and the source region 103, so that a horizontal channel of an existing memory cell is converted into a vertical channel, the length of the original horizontal channel is replaced by the vertical channel depth, and the occupied area of the memory cell can be further reduced in the length direction of the original horizontal channel; meanwhile, vertical channels are formed on both sides of the floating gate 104, and one memory cell 10 of the present invention can be formed by connecting two left and right sub-memory cells in parallel, and can provide almost twice current in an erase state, so that the area of an active region can be reduced, that is, the area occupied by the memory cell 10 is further reduced in the width direction of the original horizontal channel. Therefore, the memory cell provided by the embodiment of the invention can be reduced in two-dimensional size on the horizontal plane.
In addition, in the present embodiment, an interlayer dielectric layer 109 may be disposed between the control gate 105 and the floating gate 104 to insulate the control gate 105 from the floating gate 104. The interlayer dielectric layer may include a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked.
In the memory cell provided in the first embodiment of the present invention, at least a portion of a floating gate of a memory cell in a nonvolatile memory is disposed in a semiconductor substrate, a source region is formed below the floating gate, tunneling oxide layers are formed on two sides of the floating gate and between the floating gate and the source region in the semiconductor substrate, and a first drain region and a second drain region are respectively formed in the semiconductor substrate on two sides of the floating gate, so that when the nonvolatile memory operates, channels can be respectively formed between the first drain region and the source region and between the second drain region and the source region, and thus a horizontal channel of an existing memory cell is converted into a vertical channel, i.e., the length of an original horizontal channel is replaced by a vertical channel depth, and further an area occupied by the memory cell can be further reduced in a length direction of the original horizontal channel; meanwhile, channels are formed on two sides of the floating gate, and one storage unit is formed by connecting two sub-storage units in parallel, so that almost twice current in an erasing state can be supplied, the area of an active region can be reduced, and the area occupied by the storage unit is further reduced in the width direction of the original horizontal channel. Therefore, the memory cell and the nonvolatile memory provided by the embodiment of the invention break through the restriction of two-dimensional size reduction of the memory cell on the horizontal plane, so that the nonvolatile memory can be possible to be 45nm or 32nm or even smaller.
Example two
Fig. 3 is a schematic cross-sectional view of a memory cell according to a second embodiment of the invention. The embodiment is optimized based on the first embodiment, and the floating gate is just completely arranged in the semiconductor substrate, namely the upper surface of the floating gate is flush with the upper surface of the semiconductor substrate, so that the vertical channel depth is increased. As shown in fig. 3, the memory cell may include:
a semiconductor substrate 101 including an active region (not shown);
a source region 103 located in the semiconductor substrate 101 of the active region;
a gate region, including a floating gate 104 and a control gate 105 which are sequentially stacked on the source region 103 and are insulated from each other, wherein the upper surface of the floating gate 104 is flush with the upper surface of the semiconductor substrate 101, and a tunneling oxide layer 106 is formed on two sides of the floating gate 104 and between the floating gate 104 and the source region 103;
and a first drain region 107 and a second drain region 108 respectively located in the semiconductor substrate 101 of the active region at both sides of the floating gate 104.
In this embodiment, the control gate 105 and the word line (not shown) of the nonvolatile memory may be disposed in the same layer, and optionally, the control gate 105 and the word line are integrally formed to save the etching process.
Exemplarily, the control gate 105 and the semiconductor substrate 101 are covered with an insulating layer 110; a bit line 300 of a nonvolatile memory is disposed on the insulating layer 110; the first drain region 107 and the second drain region 108 are electrically connected to the same bit line 300 through bit line contact holes, optionally, the bit line contact holes corresponding to the first drain region 107 and the second drain region 108 are different, and the first drain region 107 and the second drain region 108 are electrically connected to the same bit line 300 through the bit line contact holes corresponding to the first drain region 107 and the second drain region 108, respectively.
In addition, sidewalls 112 may be formed on both sides of the control gate 105 and the interlayer dielectric layer 109 in this embodiment to better isolate the control gate 105 from the first drain region 107 and the second drain region 108.
Details that are not described in detail in this embodiment may refer to the above embodiments, and are not described herein again.
In the memory cell provided by the embodiment, the upper surface of the floating gate is flush with the upper surface of the semiconductor substrate, so that the floating gate is completely arranged in the semiconductor substrate, the depth of a vertical channel can be increased, and the size of the memory cell in the length direction of the original horizontal channel can be further reduced.
EXAMPLE III
The present implementation provides a non-volatile memory, which may optionally be a NOR type flash. Fig. 4a is a schematic plan view of a memory cell array of a NOR flash memory according to a third embodiment of the present invention; FIG. 4B is a cross-sectional view of the NOR flash memory of FIG. 4a along line B-B'. As shown in fig. 4a and 4b, the nonvolatile memory of the present embodiment may include:
a plurality of memory cells 100 as described in the above embodiments arranged in an array;
a plurality of word lines 200 extending in the row direction and arranged in the column direction, each word line being electrically connected to the control gates 105 of the memory cells 100 in the same row;
a plurality of bit lines 300 extending in the column direction and arranged in the row direction, each bit line 300 being electrically connected to the first drain region 107 and the second drain region 108 of the same column of memory cells 100.
Optionally, the first drain region and the second drain region are electrically connected to the bit line through a bit line contact hole; one drain region and the corresponding bit line contact hole are shared between any two adjacent memory cells along the column direction. For example, two adjacent memory cells A2 and B2 in the same column share the drain region 108 and the corresponding bit line contact hole 111.
The nonvolatile memory provided by the third embodiment of the invention comprises the storage unit provided by the third embodiment of the invention, and has corresponding functions and beneficial effects.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A memory cell, comprising:
a semiconductor substrate including an active region;
the source region is positioned in the semiconductor substrate of the active region;
the gate region comprises a floating gate and a control gate which are sequentially stacked on the source region and are insulated from each other, wherein at least part of the floating gate is positioned in the semiconductor substrate, and integral tunneling oxide layers are formed on two sides of the floating gate in the semiconductor substrate and between the floating gate and the source region;
the first drain region and the second drain region are respectively positioned in the semiconductor substrate of the active region at two sides of the floating gate;
the upper surface of the floating gate is flush with the upper surface of the semiconductor substrate;
the control gate and the semiconductor substrate are covered with insulating layers;
bit lines of the nonvolatile memory are arranged on the insulating layer;
the first drain region and the second drain region are electrically connected to the same bit line through a bit line contact hole.
2. The memory cell of claim 1, wherein the floating gate has a thickness of 100 to 350 nm.
3. The memory cell according to claim 1, wherein the width of the gate region is 20 to 80nm in the arrangement direction of the first drain region, the gate region and the second drain region.
4. The memory cell of claim 1, wherein the width of the active region is 28-65 nm in a direction perpendicular to the arrangement direction of the first drain region, the gate region and the second drain region.
5. The memory cell of claim 1, wherein the control gate is disposed in a same layer as a word line of the nonvolatile memory, and the control gate is integrally formed with the word line.
6. The memory cell of claim 1, wherein an interlayer dielectric layer is disposed between the control gate and the floating gate.
7. The memory cell of claim 6, wherein the interlevel dielectric layer comprises a first oxide layer, a nitride layer, and a second oxide layer stacked in that order.
8. The memory cell of claim 7, wherein sidewalls are formed on both sides of the control gate and the interlayer dielectric layer.
9. A non-volatile memory, comprising:
a plurality of memory cells according to any one of claims 1 to 8 arranged in an array;
a plurality of word lines extending in a row direction and arranged in a column direction, each word line being electrically connected to control gates of the memory cells in the same row;
and a plurality of bit lines extending along the column direction and arranged along the row direction, wherein each bit line is electrically connected with the first drain region and the second drain region of the memory cell in the same column.
10. The nonvolatile memory according to claim 9, wherein the first drain region and the second drain region are electrically connected to the bit line through a bit line contact hole;
and one drain region and the corresponding bit line contact hole are shared between any two adjacent memory cells along the column direction.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992233A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Flash memory device having vertical split gate structure and method for manufacturing the same |
| CN101692450A (en) * | 2009-10-13 | 2010-04-07 | 上海宏力半导体制造有限公司 | HIMOS FLASH memory unit structure and manufacturing method thereof |
| CN101800199A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Method for manufacturing flash memory |
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| US7005338B2 (en) * | 2002-09-19 | 2006-02-28 | Promos Technologies Inc. | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate |
| CN102315252B (en) * | 2011-09-28 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | Flash cell of shared source line and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992233A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Flash memory device having vertical split gate structure and method for manufacturing the same |
| CN101692450A (en) * | 2009-10-13 | 2010-04-07 | 上海宏力半导体制造有限公司 | HIMOS FLASH memory unit structure and manufacturing method thereof |
| CN101800199A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Method for manufacturing flash memory |
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Address after: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
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