CN108630661A - The forming method of semiconductor element pattern - Google Patents
The forming method of semiconductor element pattern Download PDFInfo
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- CN108630661A CN108630661A CN201710180930.3A CN201710180930A CN108630661A CN 108630661 A CN108630661 A CN 108630661A CN 201710180930 A CN201710180930 A CN 201710180930A CN 108630661 A CN108630661 A CN 108630661A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 74
- 239000000463 material Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000012546 transfer Methods 0.000 claims abstract description 10
- 238000005520 cutting process Methods 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000003909 pattern recognition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 206010067482 No adverse event Diseases 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention discloses a kind of forming method of semiconductor element pattern, including：There is provided a substrate material layer has a first area and second area；Multiple first mandrels are set above substrate material layer and correspond to first area；Multiple second mandrels are set above substrate material layer and correspond to second area；The first side wall spacer is formed in the side wall of the first mandrel, and second sidewall spacer is formed in the side wall of the second mandrel, wherein those the first side wall spacers form one first pattern, those second sidewall spacers form one second pattern, and the second sidewall spacer between adjacent two second mandrels merges each other；With transfer include the first pattern and those second sidewall spacers of those the first side wall spacers the second pattern to substrate material layer, to form a patterned substrate material layer.
Description
Technical field
The present invention relates to a kind of pattern forming methods, and more particularly to a kind of semiconductor element that can generate easy identification pattern
The forming method of part pattern.
Background technology
Semiconductor device dimensions increasingly reduce in recent years.For semiconductor technology, persistently reduce semiconductor structure size,
Improve rate, enhanced performance, improve density and reduce the cost of per unit integrated circuit, becomes the important development of semiconductor technology
Target.With the diminution of semiconductor device dimensions, the characteristic electron of device must also maintain even to be improved, to meet city
To the requirement of applying electronic product on field.For example, each layer structure of semiconductor device and affiliated element be for example defective or damage, meeting
To the influence that the characteristic electron of device causes not ignoring, therefore it is one of the major issue that manufactures semiconductor device and should be noted.
With the manufacturing technology of patterns of semiconductor element such as fin field-effect transistor manufacture craft (FinFETprocess)
For, make fin-shaped usually using one side wall image transfer (a sidewall image transfer, SIT) manufacture craft
Structure.Wherein the pattern of mandrel is used for defining coherent element in active area (such as fin) and the Cutting Road of neighboring area
Related mark pattern.In existing mandrel layout designs, the boundary of indentation pattern is too small so that optical sensor is detected
When it is difficult, and this problem make small size semiconductor element when can become more serious.Identification is not in manufacture craft
Good mark pattern probably can influence product yield.
Invention content
The present invention provides a kind of forming method of semiconductor element pattern, and the identification for the pattern to be detected to be formed can be improved
Degree.
According to an embodiment, a kind of forming method of semiconductor element pattern is proposed, including：One substrate material layer tool is provided
There are a first area and second area；Multiple first mandrels are set above substrate material layer and correspond to first area；Setting
Multiple second mandrels are above substrate material layer and correspond to second area；The first side wall spacer is formed in the side of the first mandrel
Wall, and second sidewall spacer is formed in the side wall of the second mandrel, wherein those the first side wall spacers form one first pattern,
Those second sidewall spacers form one second pattern, and the second sidewall spacer between adjacent two second mandrels is each other
Mutually fusion (merge)；Include the first pattern and those second sidewall spacers of those the first side wall spacers with transfer
Second pattern is to substrate material layer, to form a patterned substrate material layer.
More preferably understand in order to which the above-mentioned and other aspect to the present invention has, special embodiment below, and appended by cooperation
Attached drawing is described in detail below.However, protection scope of the present invention should be subject to what the appended claims were defined.
Description of the drawings
Figure 1A~Fig. 1 G are a kind of schematic diagram of the forming method of semiconductor element pattern of one embodiment of the invention；
Fig. 2 is the identification pattern top view of one of which application examples of the present invention；
Fig. 3 is the top view of multiple second mandrels in one of which application examples of the present invention；
Fig. 4 A are the top view of multiple second mandrels in another application examples of the present invention；
Fig. 4 B are another structural schematic diagram along the second mandrel shown in Fig. 4 A middle conductors 4B-4B.
Symbol description
A1：First area
A2、A2’：Second area
11：Substrate material layer
11’：Patterned substrate material layer
131-133：First mandrel
131a-133a：The upper surface of first mandrel
141-143、441、442、443、444、445、446：Second mandrel
141a-143a：The upper surface of second mandrel
443g、444g：The away minor segment of second mandrel
S1：First gap
S2：Second gap
CD1：First critical dimension
CD2：Second critical dimension
15：Layer of spacer material
t1：The thickness of layer of spacer material
17：Gap file layer
17’：Gap filling pattern
17a：The upper surface of gap filling pattern
151-153、36、46：The first side wall spacer
151a-153a：The upper surface of the first side wall spacer
161-163：Second sidewall spacer
161a-163a：The upper surface of second sidewall spacer
18：First groove
19：Second groove
t2：The width of second groove
B1：First block
B2：Second block
B3：Third block
M2-1：First group of the second mandrel
M2-2：Second group of the second mandrel
M2-3：The third group of second mandrel
D1：First direction
D2：Second direction
Specific implementation mode
In content as disclosed below, coordinate attached drawing a kind of pattern forming method that embodiment is proposed is described in detail,
In particular to a kind of forming method for the semiconductor element pattern that can generate recognizable pattern.The formation side of embodiment
The semiconductor element that method can be applied to many different aspects be, for example, (but do not limit be) fin field-effect transistor manufacture craft or
It is the pattern recognition in other manufacture crafts, makes pattern such as neighboring area or the Cutting Road region (scribe of presumptive area
Line region) related mark pattern (alignment marks) can become after its formation significantly, such as indicate pattern
Width increases, and can be more easily detected to form pattern when being detected so as to optical sensor.Therefore, implement using the present invention
The method of example can be obtained good critical dimension (critical dimension, CD) control, and then improve the to be detected of formation
The identification of pattern, to maintain high product yield.The method of the embodiment of the present invention is particularly suitable for small size semiconductor element
In the semiconductor device that part manufacture craft or feature member reduce, to promote the identification of finer pattern to be detected.
It is with reference to appended attached drawing narration wherein several groups of state sample implementations of the invention, to illustrate related forming method and structure below
Type.Related step and for example applicable step of CONSTRUCTED SPECIFICATION, relevant layers not with material and element (ex:Mandrel) space configuration
Etc. contents as described in following example content, but the present invention is not limited only to the aspect.The present invention not show it is all can
The embodiment of energy.Same or similar label is indicating same or similar part in embodiment.Furthermore it is not carried in the present invention
Other state sample implementations gone out may also can be applied.Relevant art can be without departing from the spirit and scope of the present invention to implementing
The structure of example is changed and is modified, to meet needed for practical application.And attached drawing simplified with profit clearly illustrate in embodiment
Hold, the dimension scale on attached drawing is not drawn according to actual product equal proportion.Therefore, specification and diagramatic content are only described herein reality
It applies example to be used, rather than be used as the scope of the present invention is limited.
Furthermore the word of specification and ordinal number such as " first ", " second ", " third " etc. used in claim,
To modify the element of claim, itself and unexpectedly contain and represent the request element have it is any before ordinal number, also do not represent
Sequence of a certain request element with another request element or the sequence in manufacturing method, the use of those ordinal numbers are only used for making
A request element with certain name is able to that with another request element with identical name clear differentiation can be made.
Figure 1A~Fig. 1 G are painted a kind of forming method of semiconductor element pattern according to an embodiment of the invention.It is real one
Apply in example, be using the layout such as mandrel design in two regions (such as first area A1 and second area A2) as example,
It is proposed illustrates, but not thus limitation the practical application present invention when pattern layout.As shown in Figure 1A, a base material is provided
Layer (base material layer) 11, and substrate material layer 11 has such as first area A1 and second area A2；And it is arranged
Multiple first mandrel (first mandrels) such as 131-133 and multiple second mandrels (second mandrels) 141-143
Above substrate material layer 11, and the first mandrel 131-133 corresponds to first area A1, and the second mandrel 141-143 corresponds to the
Two region A2.
Wherein, there is the first gap (first between two first adjacent mandrels (such as first mandrel 131 and 132)
Spacing) S1 has the second gap (second between two second adjacent mandrels (such as second mandrel 141 and 142)
spacing)S2.Attached drawing is only painted one of which state sample implementation.Certainly, according to needed for practical application condition, it can modify or become
Change the spacing between spacing and the second mandrel between the first mandrel；For example, spacing between the first adjacent mandrel can be with
Identical or different, the spacing between the second adjacent mandrel can be identical or different；Furthermore the first gap S1 of embodiment may
It is more than, is substantially equal to or is less than the second gap S2.Furthermore the one (such as first mandrel 132) of the first mandrel is along Y
There is the first critical dimension (first critical dimension) CD1, one (such as the second core of the second mandrel on direction
Axis 142) upper along the Y direction there is the second critical dimension (second criticaldimension), CD2, according to actually answering
The critical dimension of each mandrel, and the first critical dimension (ex can be modified or changed needed for condition:CD1 it) is likely larger than, substantially
On be equal to or be less than the second critical dimension (ex:CD2).First gap S1, the second gap S2, the first critical dimension are faced with second
As long as the second sidewall spacer that the variation between ungraduated ruler cun is formed in after capable of being allowed between the second mandrel can merge each other
(merge) can apply (and the second sidewall spacer merged herein correspond to subsequently be formed by it is recognizable to be detected
Pattern；Rear paragraph is described in detail).
In this embodiment, enable the second mandrel such as 141-143 arrange more closer than the first mandrel such as 131-133 (that is,
First gap S1 is more than the second gap S2), and the second mandrel such as 141-143 also increases (that is, the first critical dimension on the width
CD1 is less than the second critical dimension CD2) it is that example collocation attached drawing Figure 1A~Fig. 1 G are explained.
As shown in Figure 1B, a layer of spacer material 15 (spacer material layer) is formed in the first mandrel such as 131-
133 and second on mandrel such as 141-143, and wherein layer of spacer material 15 has thickness t1.Also, as shown in Figure 1 C, form first
Sidewall spacer (first sidewall spacers) such as 151,152,153 is in the side wall of the first mandrel 131-133, and shape
At second sidewall spacer (second sidewall spacers) such as 161,162,163 in the side of the second mandrel 141-143
Wall, and the second sidewall spacer between adjacent two second mandrels merges (that is, combination or merging) each other
(merge), as shown in the second sidewall spacer 162 and 163 mutually merged in Fig. 1 C.
In one embodiment, the width of the second gap S2 is no more than the one (such as 151 or 152 of the first side wall spacer
Or 153) double thickness.In one embodiment, the width of the second gap S2 is substantially equal to a first side wall spacer 151/
152/153 double thickness (S2 is about 2 × t1).In one embodiment, the width of the second gap S2 is equal to the first side wall interval
The thickness t1 of the one (such as 151 or 152 or 153) of object.However the present invention is not restricted to above-mentioned illustrative aspects, but according to
Ratios of the second gap S2 relative to the thickness t1 of the first side wall spacer can be modified or change needed for practical application condition, only
It wants to make to be formed in the sidewall spacer between adjacent two second mandrels to merge each other be using aspect.
As shown in figure iD, one gap file layer of deposition (gap filling layer) 17 is covered in the first side wall spacer
Above 151-153, the first mandrel 131-133, second sidewall spacer 161-163 and the second mandrel 141-143.Later, it removes
A part for gap file layer 17, such as gap file layer 17 is ground in a manner of chemical mechanical grinding (CMP), to expose at least
The upper surface of the first side wall spacer 151-153 and second sidewall spacer 161-163 form a gap filling pattern at this time
(such as the first side wall spacers 151 and 152 between adjacent the first side wall spacer of (gap filling pattern) 17 '
Between and the first side wall spacer 152 and 153 between) space.As referring to figure 1E, it after grinding, exposes between the first side wall
The upper surface 151a-153a of parting 151-153, the upper surface 161a-163a of second sidewall spacer 161-163, the first mandrel
The upper surface 141a-143a of the upper surface 131a-133a of 131-133 and the second mandrel 141-143.In one embodiment, gap
The upper surface 17a of filling pattern 17 ' is, for example, upper surface 151a-153a with the first side wall spacer 151-153, second sidewall
The upper surface 161a-163a of spacer 161-163, the upper surface 131a-133a of the first mandrel 131-133 and the second mandrel 141-
143 upper surface 141a-143a is generally flushed.
Furthermore as shown in figure iD, since the second sidewall spacer between the second adjacent mandrel 141-143 is mutual
The space of those positions is merged and filled up, therefore can not just insert adjacent second mandrel 141- when depositing gap file layer 17
Between 143, it can only be formed in the top of second sidewall spacer such as 162 and 163.Therefore gap file layer is removed in further part
After 17 the step of, gap filling pattern 17 ' is also in the position other than the second mandrel 141-143, as referring to figure 1E.It is laggard
Row pattern shifts.
As shown in fig. 1F, the first side wall spacer 151-153 and second sidewall spacer 161-163 is removed.At this point, substrate
11 top of material layer includes gap filling pattern 17 ', the first mandrel 131-133, the second mandrel 141-143.
As shown in Figure 1 G, with gap filling pattern 17 ', the first mandrel 131-133 and the second mandrel 141-143 for a mask
And substrate material layer 11 is etched, to form a patterned substrate material layer (patterned base material
layer)11’.Therefore, in transfer step, including the first pattern of the first side wall spacer 151-153 and including second sidewall
The second pattern and gap filling pattern 17 ' of spacer 161-163 is transferred to substrate material layer 11.After the completion of pattern transfer,
Remove gap filling pattern 17 ', the first mandrel 131-133, the second mandrel 141-143.In addition, in embodiment, substrate material layer
11/ patterned substrate material layer 11 ' may be including one or more forming the material of semiconductor element, e.g. a silicon
Baseplate material, monoxide material, a polycrystalline silicon material or other materials, the present invention is to this and is seldom particularly limited.
As shown in Figure 1 G, patterned substrate material layer 11 ' includes that multiple first grooves (first trenches) 18 are arranged
In first area A1 and correspond to the first pattern (i.e. the first side walls spacer 151-153) and multiple second groove (second
Trenches it) 19 is set to second area A2 and corresponds to the second pattern (i.e. second sidewalls spacer).Due to second groove
19 correspond to the position of the sidewall spacer of fusion, therefore can form the ditch wider (relative to first groove 18) after pattern transfer
Slot, the pattern (ex to be identified when with this as application:The identification pattern of Cutting Road) it can effectively promote pattern recognition degree.It is real one
Apply in example, 19 at least one of width of second groove such as width t2 (along the directions Y-) be more than first groove 18 at least its
One of width (such as thickness t1 equal to layer of spacer material 15).In one embodiment, the width of each second groove 19
(ex:Width t2) it is both greater than the width (ex of each first groove 18:Width t1).
Although above-mentioned example collocation attached drawing Figure 1A~Fig. 1 G arrange to obtain the first mandrel 131- of ratio with the second mandrel 141-143
133 closer (i.e.S1>S2) and the width of the second mandrel 141-143 be more than the first mandrel 131-133 width (i.e.CD2>
CD1 it is explained for), but the present invention is not limited thereto.In other embodiments, the second mandrel 141-143 can also be not added with
Width, i.e. its width are generally equal with the first mandrel 131-133 width, but arrange get Bi by the second mandrel 141-143
One mandrel 131-133 is closer, and achievees the purpose that make second sidewall spacer that can mutually merge.
In an application examples, first area A1 is, for example, a memory area (cell region) or active area, and
Two region A2 are, for example, a neighboring area or a Cutting Road region (scribe line region), and as shown in 1G figures
Two grooves 19 are, for example, the identification pattern as Cutting Road.But the present invention is not restricted to such application.In other application,
First area A1 and second area A2 can correspond to the region of identification pattern.Fig. 2 is please referred to, one of which of the present invention is painted and answers
The identification pattern top view of use-case.Wherein, the sidewall spacer of the mandrel of corresponding first area A1 will not be merged mutually, and be corresponded to
The sidewall spacer of the mandrel of second area A2 then mutually merges, therefore the first area A1 packets of identification pattern as shown in Figure 2
The pattern (such as aforementioned first groove 18) of narrow groove is included, and the second area A2 of identification pattern includes the pattern (example of wide groove
Such as aforementioned second groove 19, the corresponding sidewall spacer mutually merged).
In addition, in the other application example of the present invention, is watched from upward angle of visibility degree, can also form the group of multiple second mandrels,
And those groups be, for example, can regularly arranged (such as matrix arrangement) or irregular alignment, and positioned at adjacent second mandrel group it
Between second sidewall spacer 36 merge each other.Multiple second mandrels in the one of which application examples of the present invention that Fig. 3 is painted
Top view.In one embodiment, multiple second mandrels are located in second area A2 ' and (also can refer in the A2 of aforementioned second area
Illustrate about the structure of the second mandrel 141-142 and other related elements and step), e.g. include corresponding first block
(firstblock) the first group (first group of the second mandrels) M2-1 of the second mandrel of B1, right
Answer the second mandrel of the second group M2-2 and corresponding third block B3 of the second mandrel of the second block (second block) B2
Third group M2-3.Wherein the first block B1 is adjacent with the second block B2, and third block B3 is adjacent with the second block B2.From upper
Angle is watched, those second mandrels (ex:M2-1, M2-3, M2-3) D1 (such as the directions X-) extensions along a first direction, and the
The third group M2-3 of first group M2-1 of two mandrels, the second group M2-2 of the second mandrel and the second mandrel are along second party
To D2 (ex:The directions Y-) it is distributed to be scattered in three mandrel row (three in the first block B1 to third block B3 respectively
mandrel columns).By taking the distribution of the mandrel of two boxed areas as an example, such as adjacent the first block B1 and the second block
The first group M2-1 of B2, the second mandrel are aligned in the second group M2-2 (Fig. 3) of the second mandrel；Positioned at the second adjacent mandrel
The first group M2-1 merged each other with the second sidewall spacer 36 between the second group M2-2 of the second mandrel, and in
The pattern easily recognized is formed after pattern transfer.Certainly the application of the present invention is not restricted to this, the group of the second adjacent mandrel,
Its mandrel position can also mutually stagger or other modes arrangement.
In addition, in other application aspect, the second mandrel may also include multiple away minor segments (smallsegments).It please join
According to the top view that Fig. 4 A and Fig. 4 B, Fig. 4 A are multiple second mandrels in another application examples of the present invention.Fig. 4 B are along in Fig. 4 A
Another structural schematic diagram of second mandrel shown in line segment 4B-4B.Second mandrel 441-446 as shown in Figure 4 A is along first party
To D1 (ex:The directions X-) extend and along second direction D2 (ex:The directions Y-) it is arranged in rows, the second adjacent mandrel 441-446
Between to be, for example, (but do not limit be) have the second gap S2, and between the second sidewall between the second adjacent mandrel 441-446
Parting 46 merges (details of related content can refer to above-described embodiment content, and details are not described herein) each other.In another reality
It applies in example, the second mandrel 443 and 444 shown in the second mandrel such as Fig. 4 B respectively includes the mutually separated multiple away minor segments to come
(small segments) 443g and 444g D1 (ex along a first direction:The directions X-) distribution；And adjacent away minor segment 443g and
444g can be mutually aligned or be staggered, and the present invention is to this and is seldom limited.
According to above-mentioned, a kind of forming method for semiconductor element pattern that embodiment is proposed can make the figure of presumptive area
The related mark pattern (alignment marks) in case such as neighboring area or Cutting Road region can become significantly after its formation
(such as mark pattern width increases), can be more easily detected to form pattern when being detected so as to optical sensor.Therefore,
Using the method for the embodiment of the present invention, good critical dimension control can be obtained, and then improve distinguishing for the pattern to be detected formed
Knowledge and magnanimity, to maintain high product yield.The method of the embodiment of the present invention makes work particularly suitable for small size semiconductor element
In the semiconductor device that skill or feature member reduce, to promote the identification of finer pattern to be detected, for other elements
Electrically also have no adverse effects.Furthermore the method that embodiment is proposed forms semiconductor element figure with simplified and efficient step
Case, it is also compatible with existing manufacture craft in addition to pattern recognition can be effectively improved, it is very suitable for volume production.
Other embodiment, such as the upper different zones of layout or the position structure of block and mandrel and arrangement etc., it is also possible to can be with
Make appropriate selection needed for the corresponding practical application of mandrel distribution in each region or block when using, visual application and change.Cause
This, structure or pattern are used for illustrative purposes only as illustrated in the drawing, not limiting the range to be protected of the invention.In addition, phase
Operator is closed when knowing, the shape of component parts and position are also not limited to illustrate painted aspect in embodiment, and according to reality
Demand and/or manufacturing step when border is applied can be adjusted accordingly in the case of without departing from the spirit.
Although disclosing the present invention in conjunction with above example, it is not limited to the present invention.Skill belonging to the present invention
Have usually intellectual in art field, without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.Cause
This, protection scope of the present invention should be subject to what the appended claims were defined.
Claims (18)
1. a kind of forming method of semiconductor element pattern, including：
There is provided a substrate material layer has a first area and second area；
Multiple first mandrels are set above the substrate material layer and correspond to the first area；
Multiple second mandrels are set above the substrate material layer and correspond to the second area；
The first side wall spacer is formed in the side wall of those the first mandrels, and forms second sidewall spacer in those the second mandrels
Side wall, wherein those the first side wall spacers formed one first pattern, those second sidewall spacers formed one second pattern,
And those second sidewall spacers between adjacent two those second mandrels merge each other；With
Transfer include second pattern of first pattern and those second sidewall spacers of those the first side wall spacers extremely
The substrate material layer, to form a patterned substrate material layer.
2. forming method as described in claim 1, further includes：
Before shifting first pattern and second pattern, first remove between those the first side wall spacers and those second sidewalls
Parting.
3. forming method as described in claim 1, wherein the patterned substrate material layer include：
Multiple first grooves are set to the first area and correspond to first pattern；With
Multiple second grooves are set to the second area and correspond to second pattern.
4. forming method as claimed in claim 3, wherein the width of those each second grooves is more than those each first grooves
Width.
5. forming method as described in claim 1, wherein one first gap between adjacent two those first mandrels is more than
One second gap between adjacent two those second mandrels.
6. forming method as claimed in claim 5, the wherein width in second gap are no more than those the first side wall spacers
One double thickness.
7. forming method as claimed in claim 5, the wherein width in second gap be equal to those the first side wall spacers it
The thickness of one.
8. forming method as described in claim 1, the wherein one of those the first mandrels have one first critical dimension, those
The one of second mandrel has one second critical dimension, and first critical dimension is equal to second critical dimension.
9. forming method as described in claim 1, the wherein one of those the first mandrels have one first critical dimension, those
The one of second mandrel has one second critical dimension, and first critical dimension is less than second critical dimension.
10. forming method as described in claim 1, wherein those first mandrels have one first distribution density, those second
Mandrel has one second distribution density, and first distribution density is less than second distribution density.
11. forming method as described in claim 1, the patterned substrate material layer wherein in the second area includes extremely
It is few：
First block includes the first group of those the second mandrels；With
Second block, adjacent with first block, which includes the second group of those the second mandrels；
Wherein it is located at being somebody's turn to do between first group and second group of those the second mandrels of those adjacent the second mandrels
A little second sidewall spacers merge each other.
12. forming method as claimed in claim 11, wherein those second mandrels extend along a first direction, and those
First group of two mandrels and second group of those the second mandrels along a second direction be distributed with respectively this first
It is scattered in two mandrel rows in block and second block.
13. forming method as claimed in claim 12, first groups of wherein those the second mandrels be aligned in those second
Second group of mandrel.
14. forming method as described in claim 1, wherein those second mandrels extend along a first direction, and those
First group of two mandrels and second group of those the second mandrels are distributed along a second direction, wherein those second cores
One of axis, which is distributed including multiple away minor segments along the first direction, and those away minor segments are mutually separated comes.
15. forming method as described in claim 1, further includes：
Form space of the gap filling pattern between those adjacent the first side wall spacers；
Before shifting first pattern and second pattern, first remove between those the first side wall spacers and those second sidewalls
Parting；With
The substrate material layer is lost for a mask with the gap filling pattern, those first mandrels and those second mandrels
It carves, to form the patterned substrate material layer.
16. forming method as described in claim 1, the wherein first area are a memory area, which is one
Cutting Road region.
17. forming method as described in claim 1, the wherein first area are located at a neighboring area with the second area, and
The different piece of a transfer pattern is corresponded to respectively.
18. forming method as described in claim 1, the wherein substrate material layer are a silicon substrate.
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| CN201710180930.3A CN108630661A (en) | 2017-03-24 | 2017-03-24 | The forming method of semiconductor element pattern |
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| CN101159226A (en) * | 2006-10-02 | 2008-04-09 | 三星电子株式会社 | Method of forming pad patterns using self-align double patterning method, pad pattern layout formed using the same, and method of forming contact holes using self-align double patterning method |
| US20120208361A1 (en) * | 2011-02-14 | 2012-08-16 | Samsung Electronics Co., Ltd. | Method for forming fine patterns of a semiconductor device |
| CN103367258A (en) * | 2012-04-06 | 2013-10-23 | 力晶科技股份有限公司 | Semiconductor circuit structure and manufacturing process thereof |
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|---|---|---|---|---|
| US6429123B1 (en) * | 2000-10-04 | 2002-08-06 | Vanguard International Semiconductor Corporation | Method of manufacturing buried metal lines having ultra fine features |
| CN101159226A (en) * | 2006-10-02 | 2008-04-09 | 三星电子株式会社 | Method of forming pad patterns using self-align double patterning method, pad pattern layout formed using the same, and method of forming contact holes using self-align double patterning method |
| US20120208361A1 (en) * | 2011-02-14 | 2012-08-16 | Samsung Electronics Co., Ltd. | Method for forming fine patterns of a semiconductor device |
| CN103367258A (en) * | 2012-04-06 | 2013-10-23 | 力晶科技股份有限公司 | Semiconductor circuit structure and manufacturing process thereof |
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Application publication date: 20181009 |