CN108616315B - Power amplifier output power detection method and device, computer equipment and storage medium - Google Patents
Power amplifier output power detection method and device, computer equipment and storage medium Download PDFInfo
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- CN108616315B CN108616315B CN201810220260.8A CN201810220260A CN108616315B CN 108616315 B CN108616315 B CN 108616315B CN 201810220260 A CN201810220260 A CN 201810220260A CN 108616315 B CN108616315 B CN 108616315B
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- H04B17/101—Monitoring; Testing of transmitters for measurement of specific parameters of the transmitter or components thereof
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
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- H04B17/30—Monitoring; Testing of propagation channels
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Abstract
A power amplifier output power sampling method, device, computer equipment and storage medium, comprising: obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining output power corresponding to each time slot signal sampling point; acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points; and determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number. According to the technical scheme, after the time slot signal sampling points are sampled from the output signals of the power amplifier, the output power of the time slot signal sampling points is compared to obtain a plurality of target time slot signal sampling points with the highest output power, and the output power of the power amplifier is calculated according to the output power of the target time slot signal sampling points, so that the accuracy of obtaining the output power of the power amplifier is improved.
Description
Technical Field
The invention relates to the field of electronic equipment, in particular to a power amplifier output power detection method, a power amplifier output power detection device, computer equipment and a storage medium.
Background
In the field of power amplifier production, the working state of a power amplifier needs to be monitored according to the output power of the power amplifier. The traditional power amplifier output power sampling utilizes the characteristics of a detection tube, and obtains the current power amplifier output power by measuring the output level of the detection tube according to the linear or nonlinear relation of amplitude and output level. However, this method is not suitable for reading the power of the timeslot signal, and the accuracy of the output level of the detector is unstable, which tends to make the accuracy of the measured output power of the power amplifier low.
Disclosure of Invention
Accordingly, it is necessary to provide a method, an apparatus, a computer device and a storage medium for detecting output power of a power amplifier, which aim at the problem of low accuracy of the output power of the power amplifier.
A power amplifier output power detection method comprises the following steps:
obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining output power corresponding to each time slot signal sampling point;
acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points;
and determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
In one embodiment, before the step of obtaining the first set number of time slot signal sampling points from the power amplifier output signal, the method further includes: continuously sampling the output signals of the power amplifier to obtain a first set number of signal sampling points; determining the maximum power value corresponding to the signal sampling points of the first set number; judging whether the power amplifier output signal is a time slot signal or not according to the maximum power value and the actual power corresponding to each signal sampling point; and if the time slot signal is the time slot signal, skipping to the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal.
In one embodiment, the step of determining whether the power amplifier output signal is a timeslot signal according to the maximum power value and the actual power corresponding to each signal sampling point includes: counting the number of signal sampling points of which the actual power is less than half of the maximum power; if the number of the signal sampling points of which the actual power is smaller than half of the maximum power is larger than a set proportion relative to the first set number, determining that the power amplifier output signal is a time slot signal; the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal comprises the following steps: and obtaining a first set number of time slot signal sampling points from the first set number of signal sampling points.
In one embodiment, the step of continuously sampling the output signal of the power amplifier includes: continuously sampling the output signal of the power amplifier according to a set sampling rate; wherein the sampling rate is required to satisfy the condition: there are at least 3 sampling points within a single time slot signal duration.
In one embodiment, the step of obtaining a second set number of target timeslot signal sampling points with the highest output power from the first set number of timeslot signal sampling points includes: comparing the output power of the time slot signal sampling points with the first set number to obtain the sampling point with the maximum output power as a target time slot signal sampling point; acquiring a sampling point of the maximum output power from other time slot signal sampling points except the target time slot signal sampling point as a target time slot signal sampling point; and repeating the steps until the target time slot signal sampling points with the second set number are obtained.
In one embodiment, the step of obtaining a second set number of target timeslot signal sampling points with the highest output power from the first set number of timeslot signal sampling points includes: comparing the time slot signal sampling points of the first set number to obtain a sampling point of the maximum output power, recording the sampling point of the maximum output power as a target time slot sampling point, recording the output power of the target time slot sampling point, and modifying the output power of the sampling point of the maximum output power to a set value; the set value is not more than the minimum value of the output power corresponding to the time slot signal sampling points of the first set number; and repeating the steps until a second set number of target time slot sampling points and the output power of each target time slot sampling point are obtained.
In one embodiment, the step of determining the output power of the power amplifier according to the output power corresponding to the second set number of target timeslot signal sampling points includes: and calculating the average output power of the second set number of target time slot signal sampling points, and taking the average output power as the output power of the power amplifier.
A power amplifier output power detection device, comprising:
the first output power acquisition module is used for obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal and acquiring the output power corresponding to each time slot signal sampling point;
the sampling point acquisition module is used for acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points;
and the second output power acquisition module is used for determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining output power corresponding to each time slot signal sampling point;
acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points;
and determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining output power corresponding to each time slot signal sampling point;
acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points;
and determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
According to the power amplifier output power detection method, the device, the computer equipment and the storage medium, after the time slot signal sampling points are sampled from the output signals of the power amplifier, a plurality of target time slot signal sampling points with the highest output power are obtained by comparing the output powers of the time slot signal sampling points, and the output power of the power amplifier is obtained by calculating according to the output powers of the target time slot signal sampling points, so that the accuracy of obtaining the output power of the power amplifier is improved.
Drawings
FIG. 1 is a diagram of an exemplary embodiment of a power amplifier output power detection method;
FIG. 2 is a schematic structural diagram of a signal detection apparatus according to an embodiment;
FIG. 3 is a schematic flow chart illustrating a method for detecting output power of a power amplifier according to an embodiment;
FIG. 4 is a schematic diagram of the output power of the power amplifier according to an embodiment;
FIG. 5 is a schematic flow chart illustrating a method for detecting output power of a power amplifier according to another embodiment;
fig. 6 is a schematic structural diagram of a power amplifier output power detection apparatus according to an embodiment;
FIG. 7 is a block diagram of a computer device according to an embodiment.
Detailed Description
In order to further explain the technical means and effects of the present invention, the following description will be made for clear and complete descriptions of the technical solutions of the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments.
The power amplifier output power detection method provided by the application can be applied to the application environment shown in fig. 1, and comprises a signal detection device 10 and a power amplifier 20. The signal sampling device 10 is connected with the power amplifier 20, samples the time slot signal output by the power amplifier, and obtains the output power of the power amplifier by analyzing the acquired time slot signal sampling point.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a signal detection device according to an embodiment, and includes: a processor 110, a signal input interface 120, and a memory 130. The processor 110, which is used to provide computational and control capabilities, is hardware used to execute program instructions through basic arithmetic and logical operations in the signal detection device. The signal input interface 120 is used for inputting the output signal of the power amplifier. Memory 130 is a physical device used for temporarily or permanently storing computing programs or data (e.g., program state information).
As described in detail above, the signal detection device can perform a specified operation of power amplifier output power sampling. Signal detection device 10 performs these operations in the form of software instructions executed by processor 110 in a computer-readable medium. The software instructions stored in memory 130 cause processor 110 to perform the positioning method described above. Furthermore, the present invention can be implemented by hardware circuits or by a combination of hardware circuits and software instructions. Thus, implementations of the invention are not limited to any specific combination of hardware circuitry and software.
As shown in fig. 3, fig. 3 is a flowchart of a method for implementing power amplifier output power detection, including the following steps:
and step S31, obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining the output power corresponding to each time slot signal sampling point.
In the above step, the first set number is the number of the obtained time slot signal sampling points, the time slot signal sampling points are obtained by continuously sampling the first set number in a section of power amplifier output signal, and each time slot signal sampling point has corresponding output power.
Step S32, obtaining a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points.
In the above step, the second set number is the number of the acquired target timeslot signal sampling points, and the second set number is smaller than or equal to the first set number. And the target time slot signal sampling point is the part of the time slot signal sampling points with the highest output power.
And step S33, determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
According to the power amplifier output power detection method, after the time slot signal sampling points are sampled from the output signals of the power amplifier, the output powers of the time slot signal sampling points are compared to obtain a plurality of target time slot signal sampling points with the highest output power, and the output power of the power amplifier is calculated according to the output powers of the target time slot signal sampling points, so that the accuracy of obtaining the output power of the power amplifier is improved.
In one embodiment, before step S31, the method further includes: continuously sampling the output signals of the power amplifier to obtain a first set number of signal sampling points; determining the maximum power value corresponding to the signal sampling points of the first set number; judging whether the power amplifier output signal is a time slot signal or not according to the maximum power value and the actual power corresponding to each signal sampling point; and if the time slot signal is the time slot signal, skipping to the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal. It should be noted that, according to different output powers of the signals, the output signal of the power amplifier may be divided into a time slot signal and a dot frequency signal, and therefore, after the output signal of the power amplifier is sampled, the output signal of the power amplifier needs to be detected according to the maximum output power in the sampling points. In addition, the maximum power is the maximum output power in the signal sampling point. And comparing the output power of each signal sampling point according to the maximum power value so as to obtain the number of the signal sampling points reaching the set standard, and determining whether the output signal of the power amplifier is a time slot signal or not according to the number of the signal sampling points reaching the set standard.
In one embodiment, the step of determining whether the power amplifier output signal is a timeslot signal according to the maximum power value and the actual power corresponding to each signal sampling point includes: counting the number of signal sampling points of which the actual power is less than half of the maximum power; if the number of the signal sampling points of which the actual power is smaller than half of the maximum power is larger than a set proportion relative to the first set number, determining that the power amplifier output signal is a time slot signal; the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal comprises the following steps: and obtaining a first set number of time slot signal sampling points from the first set number of signal sampling points. In this embodiment, the maximum power value is the maximum output power value in the counted signal sampling points, the actual power of each signal sampling point is compared with the half maximum power value, and the number of signal sampling points with the actual power smaller than the half maximum power value is counted. When the ratio of the number of the signal sampling points with the actual power smaller than half of the maximum power to the first set number, namely the ratio of the number of the signal sampling points with the actual power smaller than half of the maximum power to the first set number, is larger than the set ratio, the output signal of the power amplifier can be determined to be a time slot signal, otherwise, the output signal of the power amplifier is determined to be a dot frequency signal. Generally, when the ratio of the number of signal sampling points with actual power greater than half the maximum power to the first set number is greater than 20%, the output signal of the power amplifier can be considered as a time slot signal. For example, if 200 signal sampling points are collected, wherein the number of the signal sampling points with the actual power greater than half of the maximum power value is 100, the ratio of the number of the signal sampling points with the actual power less than half of the maximum power value to the first set number is 50%, and the ratio is greater than 20%, and the output signal of the power amplifier is determined to be a time slot signal.
Fig. 4 is a schematic diagram of the output power of the power amplifier according to an embodiment, as shown in fig. 4, a horizontal axis of a coordinate represents time, a vertical axis of the coordinate represents the output power, each column represents a time slot signal sampling point, and two dotted lines in the diagram respectively correspond to a maximum power value Max and a half maximum power value Max/2 in the signal sampling points. When the actual power of the signal sampling point is greater than half of the maximum power, the height of a column corresponding to the signal sampling point exceeds a Max/2 dotted line, such as a signal sampling point C; and when the actual power of the signal sampling point is less than half of the maximum power, the height of a column corresponding to the signal sampling point is lower than the Max/2 dotted line, such as a signal sampling point B. In addition, point a represents a signal point at which continuous sampling is started.
In one embodiment, the step of continuously sampling the output signal of the power amplifier includes: continuously sampling the output signal of the power amplifier according to a set sampling rate; wherein the sampling rate is required to satisfy the condition: there are at least 3 sampling points within a single time slot signal duration. Considering that the signal duration of a single time slot is 10 microseconds at the minimum, and more than 3 signal points are acquired in each single time slot signal time, the sampling rate of the ADC is required to be at least more than 300 KSa/S.
In one embodiment, the step of obtaining a second set number of target timeslot signal sampling points with the highest output power from the first set number of timeslot signal sampling points includes: comparing the output power of the time slot signal sampling points with the first set number to obtain the sampling point with the maximum output power as a target time slot signal sampling point; acquiring a sampling point of the maximum output power from other time slot signal sampling points except the target time slot signal sampling point as a target time slot signal sampling point; and repeating the steps until the target time slot signal sampling points with the second set number are obtained. In this embodiment, after the sampling point of the maximum output power is obtained from the sampling points of the timeslot signals, the sampling points of the maximum output power are continuously obtained from the remaining sampling points of the timeslot signals, and so on until the number of the obtained sampling points of the maximum output power reaches the second set number.
In another embodiment, the step of obtaining a second set number of target timeslot signal sampling points with the highest output power from the first set number of timeslot signal sampling points includes: comparing the time slot signal sampling points of the first set number to obtain a sampling point of the maximum output power, recording the sampling point of the maximum output power as a target time slot sampling point, recording the output power of the target time slot sampling point, and modifying the output power of the sampling point of the maximum output power to a set value; the set value is not more than the minimum value of the output power corresponding to the time slot signal sampling points of the first set number; and repeating the steps until a second set number of target time slot sampling points and the output power of each target time slot sampling point are obtained.
For example, when the first set number is 200 and the second set number is 16, a specific procedure for obtaining 16 sampling points with the maximum output power from 200 sampling points of the timeslot signal is as follows:
first, round 1 comparison: comparing any two sampling points in the 200 time slot signal sampling points to obtain sampling points with large output power; and continuously comparing the sampling point with high output power with other time slot signal sampling points, and after the 200 time slot signal sampling points are compared in this way, obtaining the maximum output power in the 200 time slot signal sampling points, ending the first round of comparison, recording the maximum output power, and setting the output power of the corresponding time slot signal sampling point to be zero.
Comparing in the 2 nd round according to the 1 st round mode to obtain the 2 nd maximum output power; comparing in the 3 rd round according to the 1 st round, and obtaining the 3 rd maximum output power; in this way, 16 rounds of comparison are performed all the time, resulting in 16 maximum output powers and hence 16 samples of maximum output power.
As shown in fig. 5, fig. 5 is a flowchart of a power amplifier output power detection method according to another embodiment, which includes the following steps:
and step S51, obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining the output power corresponding to each time slot signal sampling point.
In the above step, the first set number is the number of the obtained time slot signal sampling points, the time slot signal sampling points are obtained by continuously sampling the first set number in a section of power amplifier output signal, and each time slot signal sampling point has corresponding output power.
Step S52, obtaining a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points.
In the above step, the second set number is the number of the acquired target timeslot signal sampling points, and the second set number is smaller than or equal to the first set number. And the target time slot signal sampling point is the part of the time slot signal sampling points with the highest output power.
And step S53, calculating the average output power of the second set number of target time slot signal sampling points, and taking the average output power as the output power of the power amplifier.
According to the power amplifier output power detection method, after the time slot signal sampling points are sampled from the output signals of the power amplifier, the output powers of the time slot signal sampling points are compared to obtain a plurality of target time slot signal sampling points with the highest output power, and the output power of the power amplifier is calculated according to the output powers of the target time slot signal sampling points, so that the accuracy of obtaining the output power of the power amplifier is improved.
As shown in fig. 6, fig. 6 is a schematic structural diagram of a power amplifier output power sampling apparatus according to an embodiment, including:
the first output power obtaining module 610 is configured to obtain a first set number of consecutive time slot signal sampling points from the power amplifier output signal, and obtain an output power corresponding to each time slot signal sampling point.
The first set number is the number of the obtained time slot signal sampling points, the time slot signal sampling points are obtained by continuously sampling the first set number in a section of power amplifier output signal, and each time slot signal sampling point has corresponding output power.
The sampling point obtaining module 620 is configured to obtain, from the sampling points of the timeslot signals of the first set number, target sampling points of the second set number with the highest output power.
It should be noted that the second set number is the number of the acquired target time slot signal sampling points, where the target time slot signal sampling points are the partial sampling points with the highest output power among the time slot signal sampling points. The second set number is less than or equal to the first set number.
And a second output power obtaining module 630, configured to calculate the output power of the power amplifier according to the output powers corresponding to the second set number of target timeslot signal sampling points.
The power amplifier output power sampling device firstly samples a time slot signal sampling point from an output signal of a power amplifier through the first output power acquisition module 610; then, by comparing the output powers of the time slot signal sampling points through the sampling point acquisition module 620, a plurality of target time slot signal sampling points with the highest output power are obtained; finally, the output power of the power amplifier is calculated and obtained through the second output power obtaining module 630 according to the output power of the target time slot signal sampling point, so that the accuracy of obtaining the output power of the power amplifier is improved.
In one embodiment, the power amplifier output power sampling device further comprises a data sampling module, which is used for continuously sampling the power amplifier output signal to obtain a first set number of signal sampling points; determining the maximum power value corresponding to the signal sampling points of the first set number; judging whether the power amplifier output signal is a time slot signal or not according to the maximum power value and the actual power corresponding to each signal sampling point; and if the time slot signal is the time slot signal, skipping to the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal. It should be noted that, according to different output powers of the signals, the output signal of the power amplifier may be divided into a time slot signal and a dot frequency signal, and therefore, after the output signal of the power amplifier is sampled, the output signal of the power amplifier needs to be detected according to the maximum output power in the sampling points. In addition, the maximum power is the maximum output power in the signal sampling point. And comparing the output power of each signal sampling point according to the maximum power value so as to obtain the number of the signal sampling points reaching the set standard, and determining whether the output signal of the power amplifier is a time slot signal or not according to the number of the signal sampling points reaching the set standard.
In one embodiment, the data sampling module is configured to count the number of signal sampling points whose actual power is less than half of the maximum power; if the number of the signal sampling points of which the actual power is smaller than half of the maximum power is larger than a set proportion relative to the first set number, determining that the power amplifier output signal is a time slot signal; the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal comprises the following steps: and obtaining a first set number of time slot signal sampling points from the first set number of signal sampling points. In this embodiment, the maximum power value is the maximum output power value in the counted signal sampling points, the actual power of each signal sampling point is compared with the half maximum power value, and the number of signal sampling points with the actual power smaller than the half maximum power value is counted. When the ratio of the number of the signal sampling points with the actual power smaller than half of the maximum power to the first set number, namely the ratio of the number of the signal sampling points with the actual power smaller than half of the maximum power to the first set number, is larger than the set ratio, the output signal of the power amplifier can be determined to be a time slot signal, otherwise, the output signal of the power amplifier is determined to be a dot frequency signal. Generally, when the ratio of the number of signal sampling points with actual power greater than half the maximum power to the first set number is greater than 20%, the output signal of the power amplifier can be considered as a time slot signal. For example, if 200 signal sampling points are collected, wherein the number of the signal sampling points with the actual power greater than half of the maximum power value is 100, the ratio of the number of the signal sampling points with the actual power less than half of the maximum power value to the first set number is 50%, and the ratio is greater than 20%, and the output signal of the power amplifier is determined to be a time slot signal.
In one embodiment, the data sampling module is configured to continuously sample the output signal of the power amplifier according to a set sampling rate; wherein the sampling rate is required to satisfy the condition: there are at least 3 sampling points within a single time slot signal duration. Considering that the signal duration of a single time slot is 10 microseconds at the minimum, and more than 3 signal points are acquired in each single time slot signal time, the sampling rate of the ADC is required to be at least more than 300 KSa/S.
In one embodiment, the sampling point obtaining module 620 is configured to compare the output powers of the first set number of time slot signal sampling points to obtain a sampling point with the maximum output power, which is used as a target time slot signal sampling point; acquiring a sampling point of the maximum output power from other time slot signal sampling points except the target time slot signal sampling point as a target time slot signal sampling point; and repeating the steps until the target time slot signal sampling points with the second set number are obtained. In this embodiment, after the sampling point of the maximum output power is obtained from the sampling points of the timeslot signals, the sampling points of the maximum output power are continuously obtained from the remaining sampling points of the timeslot signals, and so on until the number of the obtained sampling points of the maximum output power reaches the second set number.
In another embodiment, the sampling point obtaining module 620 is configured to compare the first set number of sampling points of the timeslot signal to obtain a sampling point of a maximum output power, record the sampling point of the maximum output power as a target sampling point of the timeslot, record the output power of the target sampling point of the timeslot, and modify the output power of the sampling point of the maximum output power to a set value; the set value is not more than the minimum value of the output power corresponding to the time slot signal sampling points of the first set number; and repeating the steps until a second set number of target time slot sampling points and the output power of each target time slot sampling point are obtained.
For example, when the first set number is 200 and the second set number is 16, a specific procedure for obtaining 16 sampling points with the maximum output power from 200 sampling points of the timeslot signal is as follows:
first, round 1 comparison: comparing any two sampling points in the 200 time slot signal sampling points to obtain sampling points with large output power; and continuously comparing the sampling point with high output power with other time slot signal sampling points, and after the 200 time slot signal sampling points are compared in this way, obtaining the maximum output power in the 200 time slot signal sampling points, ending the first round of comparison, recording the maximum output power, and setting the output power of the corresponding time slot signal sampling point to be zero.
Comparing in the 2 nd round according to the 1 st round mode to obtain the 2 nd maximum output power; comparing in the 3 rd round according to the 1 st round, and obtaining the 3 rd maximum output power; in this way, 16 rounds of comparison are performed all the time, resulting in 16 maximum output powers and hence 16 samples of maximum output power.
In one embodiment, the second output power obtaining module 630 is configured to calculate an average output power of the second set number of target timeslot signal sampling points, and use the average output power as the output power of the power amplifier.
For the specific limitation of the power amplifier output power sampling device, reference may be made to the above limitation on the power amplifier output power sampling method, which is not described herein again. All modules in the power amplifier output power sampling device can be completely or partially realized through software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 7. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a power amplifier output power detection method.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program: obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining output power corresponding to each time slot signal sampling point; acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points; and determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
In one embodiment, the processor, when executing the computer program, further performs the steps of: continuously sampling the output signals of the power amplifier to obtain a first set number of signal sampling points; determining the maximum power value corresponding to the signal sampling points of the first set number; judging whether the power amplifier output signal is a time slot signal or not according to the maximum power value and the actual power corresponding to each signal sampling point; and if the time slot signal is the time slot signal, skipping to the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal.
In one embodiment, the processor, when executing the computer program, further performs the steps of: counting the number of signal sampling points of which the actual power is less than half of the maximum power; if the number of the signal sampling points of which the actual power is smaller than half of the maximum power is larger than a set proportion relative to the first set number, determining that the power amplifier output signal is a time slot signal; the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal comprises the following steps: and obtaining a first set number of time slot signal sampling points from the first set number of signal sampling points.
In one embodiment, the processor, when executing the computer program, further performs the steps of: continuously sampling the output signal of the power amplifier according to a set sampling rate; wherein the sampling rate is required to satisfy the condition: there are at least 3 sampling points within a single time slot signal duration.
In one embodiment, the processor, when executing the computer program, further performs the steps of: comparing the output power of the time slot signal sampling points with the first set number to obtain the sampling point with the maximum output power as a target time slot signal sampling point; acquiring a sampling point of the maximum output power from other time slot signal sampling points except the target time slot signal sampling point as a target time slot signal sampling point; and repeating the steps until the target time slot signal sampling points with the second set number are obtained.
In one embodiment, the processor, when executing the computer program, further performs the steps of: comparing the time slot signal sampling points of the first set number to obtain a sampling point of the maximum output power, recording the sampling point of the maximum output power as a target time slot sampling point, recording the output power of the target time slot sampling point, and modifying the output power of the sampling point of the maximum output power to a set value; the set value is not more than the minimum value of the output power corresponding to the time slot signal sampling points of the first set number; and repeating the steps until a second set number of target time slot sampling points and the output power of each target time slot sampling point are obtained.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and calculating the average output power of the second set number of target time slot signal sampling points, and taking the average output power as the output power of the power amplifier.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which when executed by a processor performs the steps of: obtaining a first set number of continuous time slot signal sampling points from the power amplifier output signal, and obtaining output power corresponding to each time slot signal sampling point; acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points; and determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
In one embodiment, the computer program when executed by the processor further performs the steps of: continuously sampling the output signals of the power amplifier to obtain a first set number of signal sampling points; determining the maximum power value corresponding to the signal sampling points of the first set number; judging whether the power amplifier output signal is a time slot signal or not according to the maximum power value and the actual power corresponding to each signal sampling point; and if the time slot signal is the time slot signal, skipping to the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal.
In one embodiment, the computer program when executed by the processor further performs the steps of: counting the number of signal sampling points of which the actual power is less than half of the maximum power; if the number of the signal sampling points of which the actual power is smaller than half of the maximum power is larger than a set proportion relative to the first set number, determining that the power amplifier output signal is a time slot signal; the step of obtaining the time slot signal sampling points of the first set number by the power amplifier output signal comprises the following steps: and obtaining a first set number of time slot signal sampling points from the first set number of signal sampling points.
In one embodiment, the computer program when executed by the processor further performs the steps of: continuously sampling the output signal of the power amplifier according to a set sampling rate; wherein the sampling rate is required to satisfy the condition: there are at least 3 sampling points within a single time slot signal duration.
In one embodiment, the computer program when executed by the processor further performs the steps of: comparing the output power of the time slot signal sampling points with the first set number to obtain the sampling point with the maximum output power as a target time slot signal sampling point; acquiring a sampling point of the maximum output power from other time slot signal sampling points except the target time slot signal sampling point as a target time slot signal sampling point; and repeating the steps until the target time slot signal sampling points with the second set number are obtained.
In one embodiment, the computer program when executed by the processor further performs the steps of: comparing the time slot signal sampling points of the first set number to obtain a sampling point of the maximum output power, recording the sampling point of the maximum output power as a target time slot sampling point, recording the output power of the target time slot sampling point, and modifying the output power of the sampling point of the maximum output power to a set value; the set value is not more than the minimum value of the output power corresponding to the time slot signal sampling points of the first set number; and repeating the steps until a second set number of target time slot sampling points and the output power of each target time slot sampling point are obtained.
In one embodiment, the computer program when executed by the processor further performs the steps of: and calculating the average output power of the second set number of target time slot signal sampling points, and taking the average output power as the output power of the power amplifier.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A power amplifier output power detection method is characterized by comprising the following steps:
continuously sampling the output signals of the power amplifier to obtain a first set number of signal sampling points;
determining the maximum power value corresponding to the signal sampling points of the first set number;
counting the number of signal sampling points corresponding to each signal sampling point, wherein the actual power of the signal sampling points is less than half of the maximum power; if the number of the signal sampling points of which the actual power is smaller than half of the maximum power is larger than a set proportion relative to the first set number, determining that the power amplifier output signal is a time slot signal;
obtaining a first set number of time slot signal sampling points from the first set number of signal sampling points; acquiring output power corresponding to each time slot signal sampling point;
acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points; the method specifically comprises the following steps: sequentially carrying out comparison of preset rounds to obtain output power corresponding to a second set number of target time slot signal sampling points which are sequentially arranged from large to small; in each round of comparison, firstly setting the output power corresponding to the sampling point with the maximum output power obtained in the previous round of comparison to be zero, and obtaining a time slot signal sampling point set containing a first set number in the current round; comparing the sampling points with the maximum output power in the current round according to a preset rule from the time slot signal sampling point set containing the first set number in the current round, and storing the output power corresponding to the sampling point with the maximum output power in the current round;
and determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
2. The method for detecting the output power of a power amplifier according to claim 1, further comprising:
counting the number of signal sampling points of which the actual power is less than half of the maximum power; and if the number of the signal sampling points of which the actual power is less than half of the maximum power is smaller than or equal to the set proportion relative to the first set number, determining that the power amplifier output signal is a dot frequency signal.
3. The method for detecting the output power of a power amplifier according to claim 1, wherein the step of continuously sampling the output signal of the power amplifier comprises:
continuously sampling the output signal of the power amplifier according to a set sampling rate; wherein the sampling rate is required to satisfy the condition: there are at least 3 sampling points within a single time slot signal duration.
4. The method for detecting the output power of a power amplifier according to any one of claims 1 to 3, wherein the step of obtaining a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points comprises:
comparing the output power of the time slot signal sampling points with the first set number to obtain the sampling point with the maximum output power as a target time slot signal sampling point;
acquiring a sampling point of the maximum output power from other time slot signal sampling points except the target time slot signal sampling point as a target time slot signal sampling point; and repeating the steps until the target time slot signal sampling points with the second set number are obtained.
5. The method of claim 3, wherein the sampling rate is at least greater than 300 KSa/S.
6. The method for detecting the output power of a power amplifier according to any one of claims 1 to 3, wherein the step of determining the output power of the power amplifier according to the output power corresponding to the second set number of target timeslot signal sampling points comprises:
and calculating the average output power of the second set number of target time slot signal sampling points, and taking the average output power as the output power of the power amplifier.
7. A power amplifier output power detection device, comprising:
the data sampling module is used for continuously sampling the output signals of the power amplifier to obtain a first set number of signal sampling points; determining the maximum power value corresponding to the signal sampling points of the first set number; counting the number of signal sampling points corresponding to each signal sampling point, wherein the actual power of the signal sampling points is less than half of the maximum power; if the number of the signal sampling points of which the actual power is smaller than half of the maximum power is larger than a set proportion relative to the first set number, determining that the power amplifier output signal is a time slot signal; obtaining a first set number of time slot signal sampling points from the first set number of signal sampling points;
the first output power acquisition module is used for acquiring the output power corresponding to each time slot signal sampling point;
the sampling point acquisition module is used for acquiring a second set number of target time slot signal sampling points with the highest output power from the first set number of time slot signal sampling points; the method specifically comprises the following steps: sequentially carrying out comparison of preset rounds to obtain output power corresponding to a second set number of target time slot signal sampling points which are sequentially arranged from large to small; in each round of comparison, firstly setting the output power corresponding to the sampling point with the maximum output power obtained in the previous round of comparison to be zero, and obtaining a time slot signal sampling point set containing a first set number in the current round; comparing the sampling points containing the first set number of time slot signal sampling points in the current round according to a preset rule to obtain the sampling point with the maximum output power in the current round and storing the output power corresponding to the sampling point with the maximum output power in the current round; and the second output power acquisition module is used for determining the output power of the power amplifier according to the output power corresponding to the target time slot signal sampling points with the second set number.
8. The apparatus of claim 7,
the data sampling module is also used for continuously sampling the output signal of the power amplifier according to a set sampling rate; wherein the sampling rate is required to satisfy the condition: there are at least 3 sampling points within a single time slot signal duration.
9. A computer-readable storage medium, on which a computer program is stored, wherein the program, when executed by a processor, implements the steps of the power amplifier output power detection method according to any one of claims 1 to 6.
10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the power amplifier output power detection method according to any one of claims 1 to 6 when executing the program.
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| CN1642337A (en) * | 2004-01-12 | 2005-07-20 | 大唐移动通信设备有限公司 | Quick frequency scanning method for howing estate primary searching |
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