CN108614757B - Method for monitoring 1394 bus reset and implementing circuit - Google Patents
Method for monitoring 1394 bus reset and implementing circuit Download PDFInfo
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- CN108614757B CN108614757B CN201611140809.XA CN201611140809A CN108614757B CN 108614757 B CN108614757 B CN 108614757B CN 201611140809 A CN201611140809 A CN 201611140809A CN 108614757 B CN108614757 B CN 108614757B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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Abstract
The invention belongs to the computer hardware technology, and relates to a design circuit and a method for resetting and monitoring a 1394 bus. The 1394 bus is a network transmission data bus in the field of military aviation, the invention constructs the bus reset signal into a data packet format of a special packet, and then displays the bus reset occurrence moment in the form of the special packet through primary/secondary filtering, so that the time of the bus reset action can be determined, the 1394 bus can be monitored in real time, and the real-time processing requirement of the data in an airborne environment can be met.
Description
Technical Field
The invention belongs to the computer hardware technology, and relates to a design circuit and a method for resetting and monitoring a 1394 bus.
Background
The 1394 bus is used as a network transmission data bus in the field of military aviation, a bus monitoring node needs to monitor data packets and bus resetting on the bus, the data packets and the bus resetting are required to be recorded according to the sequence of the data packets and the bus resetting, and a bus event of the bus resetting is monitored according to the mode of the data packets. In the prior art, bus data packets and bus reset occurrence time are recorded, and software is used for sequencing according to sequence when monitoring records are checked, but the method is not suitable for the real-time processing requirements on data in an airborne environment.
Disclosure of Invention
The purpose of the invention is as follows: a method for monitoring 1394 bus reset and a realization circuit are provided, which are used for realizing real-time monitoring of 1394 bus. The invention provides a method for sequentially recording bus reset and common data packets according to time sequence by a hardware logic circuit by regarding the bus reset as a special message so as to meet the requirement of real-time processing of data.
The technical scheme of the invention is as follows:
a method of monitoring a 1394 bus reset, comprising the steps of:
step 1: the host interface module of the link layer is configured with a chip of the link layer, so that after detecting that the 1394 bus is reset, the host interface module of the link layer reports that a bus reset event occurs, and the step 2 is carried out; when the bus has data transmission, the link layer DM interface module receives the data packet transmitted by the link layer chip, and the step 3 is carried out;
step 2: the host interface module of the link layer informs the DM interface module of the link layer of constructing a bus reset packet, writes the bus reset packet into a data buffer FIFO, and then goes to step 4;
and step 3: the link layer DM interface module writes the data packet transmitted by the link layer chip DM interface into a data buffer FIFO;
and 4, step 4: the link layer DM interface module informs the FIFO control module whether the type of the data packet currently stored in the data buffer FIFO is a common data packet or a constructed bus reset packet, and the length of the data packet;
and 5: the FIFO control module stores the length information of the data packet into a type FIFO according to the type of the data packet, and simultaneously reads out and writes the data stored in the data buffer FIFO into the data FIFO;
step 6: the DMA control module detects whether the type FIFO is empty, if not, the DMA control module calculates the address and the packet length needed to be stored in the data packet and informs the host DMA interface module;
and 7: the host DMA interface module extracts data from the data FIFO according to the destination address and the length of the moved data of the DMA operation and sends the data to the host.
The circuit for realizing the method comprises a link layer host interface module, a link layer DM interface module, an FIFO control module, a data buffer FIFO, a type FIFO, a data FIFO, a DMA control module and a host interface module,
the host interface module of the link layer is used for configuring an external link layer chip, so that the external link layer chip reports the occurrence of a bus reset event to the host interface module of the link layer after detecting that the 1394 bus is reset; informing a link layer DM interface module to construct a bus reset packet;
the link layer DM interface module is used for constructing a bus reset packet according to a data packet transmitted from an external link layer chip and a notice of the link layer host interface module, and writing the bus reset packet into a data buffer FIFO according to a time sequence; informing an FIFO control module whether the type of a data packet currently stored in the data buffer FIFO is a common data packet or a constructed bus reset packet, and the length of the data packet;
the FIFO control module stores the length information of the data packet into the type FIFO according to the type of the data packet, and simultaneously reads out and writes the data stored in the data buffer FIFO into the data FIFO;
the DMA control module is used for detecting whether the type FIFO is empty or not, if not, calculating the address and the packet length which need to be stored in the data packet, and informing the host DMA interface module;
and the host DMA interface module extracts data from the data FIFO according to the destination address and the length of the moved data of the DMA operation and sends the data to the host.
The format of the bus reset packet is constructed to be different from the format of the normally transmitted data packet, so that the bus reset packet and the normally transmitted data packet can be distinguished.
The invention has the advantages and effects that: the bus reset signal is constructed into a data packet format of a special packet, and finally the bus reset occurrence time is displayed in the form of the special packet, so that the monitored bus reset and normally transmitted data packets can be arranged in real time according to the time sequence.
Drawings
FIG. 1 is a block diagram of the circuit structure of the present invention
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than the whole embodiments, and that all other embodiments, which can be derived by a person skilled in the art without inventive step based on the embodiments of the present invention, belong to the scope of protection of the present invention.
A design method for monitoring bus reset comprises the following steps:
step 1: the host interface module of the link layer is configured with a chip of the link layer, so that after detecting that the 1394 bus is reset, the host interface module of the link layer reports that a bus reset event occurs, and the step 2 is carried out; when the bus has data transmission, the link layer DM interface module receives the data packet transmitted by the link layer chip, and the step 3 is carried out;
step 2: the host interface module of the link layer informs the DM interface module of the link layer of constructing a bus reset packet, writes the bus reset packet into a data buffer FIFO, and then goes to step 4;
and step 3: the link layer DM interface module writes the data packet transmitted by the link layer chip DM interface into a data buffer FIFO;
and 4, step 4: the link layer DM interface module informs the FIFO control module whether the type of the data packet currently stored in the data buffer FIFO is a common data packet or a constructed bus reset packet, and the length of the data packet;
and 5: the FIFO control module stores the length information of the data packet into a type FIFO according to the type of the data packet, and simultaneously reads out and writes the data stored in the data buffer FIFO into the data FIFO;
step 6: the DMA control module detects whether the type FIFO is empty, if not, the DMA control module calculates the address and the packet length needed to be stored in the data packet and informs the host DMA interface module;
and 7: the host DMA interface module extracts data from the data FIFO according to the destination address and the length of the moved data of the DMA operation and sends the data to the host.
The circuit for realizing the method comprises a link layer host interface module, a link layer DM interface module, an FIFO control module, a data buffer FIFO, a type FIFO, a data FIFO, a DMA control module and a host interface module,
the host interface module of the link layer is used for configuring an external link layer chip, so that the external link layer chip reports the occurrence of a bus reset event to the host interface module of the link layer after detecting that the 1394 bus is reset; informing a link layer DM interface module to construct a bus reset packet;
the link layer DM interface module is used for constructing a bus reset packet according to a data packet transmitted from an external link layer chip and a notice of the link layer host interface module, and writing the bus reset packet into a data buffer FIFO according to a time sequence; informing an FIFO control module whether the type of a data packet currently stored in the data buffer FIFO is a common data packet or a constructed bus reset packet, and the length of the data packet;
the FIFO control module stores the length information of the data packet into the type FIFO according to the type of the data packet, and simultaneously reads out and writes the data stored in the data buffer FIFO into the data FIFO;
the DMA control module is used for detecting whether the type FIFO is empty or not, if not, calculating the address and the packet length which need to be stored in the data packet, and informing the host DMA interface module;
and the host DMA interface module extracts data from the data FIFO according to the destination address and the length of the moved data of the DMA operation and sends the data to the host.
The format of the bus reset packet is constructed to be different from the format of the normally transmitted data packet, so that the bus reset packet and the normally transmitted data packet can be distinguished.
Claims (2)
1. A method of monitoring a 1394 bus reset, comprising the steps of,
step 1: the host interface module of the link layer is configured with a chip of the link layer, so that after detecting that the 1394 bus is reset, the host interface module of the link layer reports that a bus reset event occurs, and the step 2 is carried out; when the bus has data transmission, the link layer DM interface module receives the data packet transmitted by the link layer chip, and the step 3 is carried out;
step 2: the host interface module of the link layer informs the DM interface module of the link layer of constructing a bus reset packet, writes the bus reset packet into a data buffer FIFO, and then goes to step 4;
and step 3: the link layer DM interface module writes the data packet transmitted by the link layer chip DM interface into a data buffer FIFO;
and 4, step 4: the link layer DM interface module informs the FIFO control module whether the type of the data packet currently stored in the data buffer FIFO is a common data packet or a constructed bus reset packet, and the length of the data packet;
and 5: the FIFO control module stores the length information of the data packet into a type FIFO according to the type of the data packet, and simultaneously reads out and writes the data stored in the data buffer FIFO into the data FIFO;
step 6: the DMA control module detects whether the type FIFO is empty, if not, the DMA control module calculates the address and the packet length needed to be stored in the data packet and informs the host DMA interface module;
and 7: the host DMA interface module extracts data from the data FIFO according to the destination address and the moved data length of the DMA operation, sends the data to the host computer, constructs the format of the bus reset packet, and is different from the format of the data packet transmitted normally, so that the bus reset packet and the data packet transmitted normally can be distinguished.
2. A circuit for implementing the method of monitoring 1394 bus resets of claim 1, including a link layer host interface module, a link layer DM interface module, a FIFO control module, a data buffer FIFO, a type FIFO, a data FIFO, a DMA control module, and a host interface module, wherein
The host interface module of the link layer is used for configuring an external link layer chip, so that the external link layer chip reports the occurrence of a bus reset event to the host interface module of the link layer after detecting that the 1394 bus is reset; informing a link layer DM interface module to construct a bus reset packet;
the link layer DM interface module is used for constructing a bus reset packet according to a data packet transmitted from an external link layer chip and a notice of the link layer host interface module, and writing the bus reset packet into a data buffer FIFO according to a time sequence; informing an FIFO control module whether the type of a data packet currently stored in the data buffer FIFO is a common data packet or a constructed bus reset packet, and the length of the data packet;
the FIFO control module stores the length information of the data packet into the type FIFO according to the type of the data packet, and simultaneously reads out and writes the data stored in the data buffer FIFO into the data FIFO;
the DMA control module is used for detecting whether the type FIFO is empty or not, if not, calculating the address and the packet length which need to be stored in the data packet, and informing the host DMA interface module;
the host DMA interface module extracts data from the data FIFO according to the destination address and the length of the moved data of the DMA operation and sends the data to the host,
the format of the bus reset packet is constructed to be different from the format of the normally transmitted data packet, so that the bus reset packet and the normally transmitted data packet can be distinguished.
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| CN201611140809.XA CN108614757B (en) | 2016-12-12 | 2016-12-12 | Method for monitoring 1394 bus reset and implementing circuit |
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| CN201611140809.XA CN108614757B (en) | 2016-12-12 | 2016-12-12 | Method for monitoring 1394 bus reset and implementing circuit |
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| CN108614757B true CN108614757B (en) | 2021-10-15 |
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Effective date of registration: 20221010 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710000 Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |
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