CN108599571B - Staggered parallel type switching power supply control circuit and control method - Google Patents
Staggered parallel type switching power supply control circuit and control method Download PDFInfo
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- CN108599571B CN108599571B CN201810731929.XA CN201810731929A CN108599571B CN 108599571 B CN108599571 B CN 108599571B CN 201810731929 A CN201810731929 A CN 201810731929A CN 108599571 B CN108599571 B CN 108599571B
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
- H02M3/1586—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel switched with a phase shift, i.e. interleaved
Abstract
The invention provides a staggered parallel type switching power supply control circuit, which comprises a main switching circuit and a slave switching circuit, wherein the control circuit comprises a first operational amplifier, a first input end of the first operational amplifier receives feedback voltage, a second input end of the first operational amplifier receives first reference voltage, and the first operational amplifier outputs a reference signal, and the reference signal is used for controlling the upper limit value and the lower limit value of inductance current in the main switching circuit and the upper limit value and the lower limit value of inductance current in the slave switching circuit; the control circuit adjusts the upper and lower limit values of the inductance current in the slave switch circuit according to the phase difference of the master switch circuit and the slave switch circuit so as to enable the phase difference of the master switch circuit and the slave switch circuit to reach the expected phase difference. The invention can adjust the phase difference between the master switch circuit and the slave switch circuit, and has better dynamic response.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a staggered parallel type switching power supply control circuit and a control method.
Background
Compared with the traditional buck circuit, the two buck circuits which are connected in parallel in a staggered way are adopted, as shown in fig. 1, each buck circuit only needs to bear half of output power, and the current born by the inductors L1 and L2 and the switching tubes Q1 and Q2 is half of that of the traditional buck circuit. Under high frequency, the output capacitor C00 can adopt a ceramic capacitor with smaller equivalent resistance, so that the output of the switching power supply is more stable, and the efficiency of the switching power supply system is higher.
In the prior art, two buck paths which are staggered and connected in parallel realize the phase-staggered conduction, a fixed frequency control mode is usually adopted, and the fixed frequency control mode is limited by the response speed of a loop, so that the dynamic response is poor. In general switching power supply design, a constant conduction control mode is generally adopted to obtain better dynamic response, but the constant conduction control mode is applied to a staggered parallel switching power supply, so that phase difference adjustment of two buck circuits is difficult to realize.
Disclosure of Invention
The invention aims to provide a staggered parallel type switching power supply control circuit and a control method for realizing phase adjustment, which are used for solving the problems that the dynamic response is poor and the phase-staggered conduction angle is difficult to adjust when the existing switching power supply is in phase-staggered conduction.
In order to achieve the above object, the present invention provides a control circuit of an interleaved parallel switching power supply, where the interleaved parallel switching power supply includes a master switching circuit and a slave switching circuit, the control circuit of the switching power supply includes a first operational amplifier, a first input terminal of which receives a feedback voltage, a second input terminal of which receives a first reference voltage, and the first operational amplifier outputs a reference signal, where the reference signal is used to control an upper limit value and a lower limit value of an inductor current in the master switching circuit and an upper limit value and a lower limit value of an inductor current in the slave switching circuit;
The control circuit adjusts the upper and lower limit values of the inductance current in the slave switch circuit according to the phase difference of the master switch circuit and the slave switch circuit so as to enable the phase difference of the master switch circuit and the slave switch circuit to reach the expected phase difference.
Optionally, the switching power supply control circuit further includes a main control circuit, and the main control circuit obtains an upper limit value and a lower limit value of the inductor current in the main switching circuit according to the reference signal and the first difference signal; the first difference signal represents the difference value between the upper limit value and the lower limit value of the inductor current in the main switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the main switch circuit, or smaller than or equal to the lower limit value of the inductance current in the main switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the main switch circuit.
Optionally, the switching power supply control circuit further includes a slave control circuit, and when the phase difference between the master switching circuit and the slave switching circuit is greater than the expected phase difference, the slave control circuit reduces the upper and lower limit difference values of the inductor current in the slave switching circuit; the slave control circuit increases the upper and lower limit values of the inductor current in the slave switching circuit when the phase difference between the master switching circuit and the slave switching circuit is smaller than the expected phase difference.
Optionally, the secondary control circuit obtains an upper limit value and a lower limit value of the inductor current in the secondary switch circuit according to the reference signal and a second difference signal, and the second difference signal represents a difference value between the upper limit value and the lower limit value of the inductor current in the secondary switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the slave switch circuit, or smaller than or equal to the lower limit value of the inductance current in the slave switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the slave switch circuit; the second difference signal is adjusted according to the phase difference of the master and slave switching circuits.
Optionally, the slave control circuit further includes a phase difference detection circuit, the phase difference detection circuit receives a first signal and a second signal, and outputs a phase difference signal, the first signal represents a signal of on-off of a main switch in the main switch circuit, and the second signal represents a signal of on-off of a main switch tube in the slave switch circuit.
Optionally, when the first signal characterizes that a main switch in the main switch circuit is turned on, the phase difference detection circuit outputs a phase difference signal; the second signal characterizes the phase difference signal level inversion when the main switch in the slave switch circuit is turned on.
Optionally, the phase difference detection circuit includes a pulse generation circuit and a trigger, the pulse generation circuit receives the first signal and the second signal and outputs a first pulse signal and a second pulse signal; the trigger setting end receives the first pulse signal, the trigger resetting end receives the second pulse signal, and the trigger output signal is used as the phase difference signal or is converted to be used as the phase difference signal.
Optionally, the slave control circuit further includes a difference adjustment circuit, the difference adjustment circuit receiving a phase difference signal and controlling the first current to discharge the first capacitor when the phase difference between the master switch circuit and the slave switch circuit is greater than an expected phase difference; when the phase difference between the master switch circuit and the slave switch circuit is smaller than the expected phase difference, the second current is controlled to charge the first capacitor so as to obtain a regulating voltage, the regulating voltage regulates the second difference signal, and the regulating voltage represents the variation of the second difference signal.
Optionally, the difference value adjusting circuit includes a filter circuit and a comparator, the filter circuit includes a first resistor and a second capacitor, the first end of the first resistor is connected to the output end of the phase difference detecting circuit, the second end of the first resistor is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, the voltage on the second capacitor is a first voltage, the first end of the comparator receives the first voltage, the second end of the comparator receives a second reference voltage, the comparator outputs a comparison signal, and the second reference voltage represents an expected phase difference.
Optionally, the difference value adjusting circuit further includes a first current source, a second current source, and the first capacitor, and when the first voltage reaches the second reference voltage, the comparison signal controls the first current source to be turned on, and outputs the first current; and when the first voltage does not reach the second reference voltage, the comparison signal controls the second current source to be conducted, and the second current is output.
Optionally, the staggered parallel switching power supply includes at least one slave switching circuit, and the switching power supply control circuit adjusts the phase difference of any one or more of the slave switching circuits and the master switching circuit to a desired phase difference.
The invention also provides a control method of the staggered parallel switching power supply, which comprises the following steps:
Obtaining a reference signal according to error amplification signals of the first reference voltage and the feedback voltage, wherein the reference signal is used for controlling an upper limit value and a lower limit value of an inductor current in a main switch circuit and an upper limit value and a lower limit value of the inductor current in a slave switch circuit;
And adjusting the upper and lower limit values of the inductance current in the slave switch circuit according to the phase difference of the master switch circuit and the slave switch circuit so as to enable the phase difference of the master switch circuit and the slave switch circuit to reach the expected phase difference.
Optionally, obtaining an upper limit value and a lower limit value of the inductor current in the main switch circuit according to the reference signal and the first difference signal; the first difference signal represents the difference value between the upper limit value and the lower limit value of the inductor current in the main switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the main switch circuit, or smaller than or equal to the lower limit value of the inductance current in the main switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the main switch circuit.
Optionally, when the phase difference between the master switch circuit and the slave switch circuit is greater than the expected phase difference, the slave control circuit reduces the upper and lower limit values of the inductance current in the slave switch circuit; the slave control circuit increases the upper and lower limit values of the inductor current in the slave switching circuit when the phase difference between the master switching circuit and the slave switching circuit is smaller than the expected phase difference.
Optionally, the upper limit value and the lower limit value of the inductor current in the slave switch circuit are obtained according to the reference signal and a second difference signal, and the second difference signal represents the difference value between the upper limit value and the lower limit value of the inductor current in the slave switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the slave switch circuit, or smaller than or equal to the lower limit value of the inductance current in the slave switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the slave switch circuit; the second difference signal is adjusted according to the phase difference of the master and slave switching circuits.
Compared with the prior art, the invention has the following advantages: obtaining a reference signal according to the errors of the first reference voltage and the feedback voltage, wherein the reference signal is used for controlling the upper limit value and the lower limit value of the inductance current in the main switch circuit and the upper limit value and the lower limit value of the inductance current in the auxiliary switch circuit; and adjusting the upper and lower limit values of the inductance current in the slave switch circuit according to the phase difference of the master switch circuit and the slave switch circuit so as to enable the phase difference of the master switch circuit and the slave switch circuit to reach the expected phase difference. The invention can adjust the phase difference between the master switch circuit and the slave switch circuit, and the dynamic response of the switch power supply is better when the phase is misphased and conducted.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration of an interleaved parallel switching power supply of the present invention;
FIG. 2 is a schematic diagram of a control circuit for an interleaved parallel switching power supply according to the present invention;
FIG. 3 is a schematic diagram of a main control circuit of the present invention;
FIG. 4 is a schematic diagram of a slave control circuit according to the present invention;
FIG. 5 is a schematic diagram of a phase difference detection circuit and a differential value adjustment circuit according to the present invention;
FIG. 6 is a waveform diagram of a control circuit for an interleaved parallel switching power supply according to the present invention;
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments only. The invention is intended to cover any alternatives, modifications, equivalents, and variations that fall within the spirit and scope of the invention.
In the following description of preferred embodiments of the invention, specific details are set forth in order to provide a thorough understanding of the invention, and the invention will be fully understood to those skilled in the art without such details.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. It should be noted that the drawings are in a simplified form and are not to scale precisely, but rather are merely intended to facilitate and clearly illustrate the embodiments of the present invention.
Fig. 1 illustrates an interleaved parallel switching power supply of the present invention, which includes a main switching circuit and a slave switching circuit, a capacitor C00 and voltage dividing resistors R1 and R2, the main switching circuit includes a first main switching tube M1, a first auxiliary switching tube M3 and a first inductor L1, and the slave switching circuit includes a second main switching tube M2, a second auxiliary switching tube M4 and a second inductor L2. The present embodiment is only illustrated by two staggered parallel switching circuits, and the staggered parallel switching power supply may further include a plurality of parallel slave switching circuits.
Fig. 2 illustrates a schematic diagram of a control circuit of an interleaved parallel switching power supply according to the present invention, including a first operational amplifier U100, a master control circuit U101, a slave control circuit U102, and a capacitor C0. The first operational amplifier U0 has a first input terminal receiving the feedback voltage FB, a second input terminal receiving the first reference voltage VREF, and outputting the reference signal IVC. The main control circuit U101 receives a reference signal IVC and a first difference signal DeltaVC 1 to obtain an upper limit value ITOP1 and a lower limit value IBOT1 of the inductance current of the main switching circuit, wherein the first difference signal DeltaVC 1 represents the difference between the upper limit value ITOP1 and the lower limit value IBOT1, IVC is more than or equal to ITOP1 or IVC is less than or equal to IBOT1 or IBOT is less than IVC and less than ITOP1. The first sampling signal CS1 representing the inductor current of the main switching circuit is compared with the upper limit value ITOP1 and the lower limit value IBOT of the inductor current of the main switching circuit, respectively, so as to control the on and off of the first main switching transistor M1 and the first auxiliary switching transistor M3. The reference signal IVC and the second difference signal DeltaVC 2 are received from the control circuit U102, so that the upper limit value ITOP2 and the lower limit value IBOT2 of the inductance current of the secondary switch circuit are obtained, the second difference signal DeltaVC 2 represents the difference between the upper limit value ITOP2 and the lower limit value IBOT2, IVC is more than or equal to ITOP2 or IVC is less than or equal to IBOT2 or IBOT2 is less than IVC and less than ITOP2. The slave control circuit U102 detects the phase difference between the master switching circuit and the slave switching circuit, and adjusts the upper and lower limit values of the inductor current in the slave switching circuit according to the phase difference, that is, adjusts Δvc2, to obtain new ITOP2 and IBOT2. The second sampling signal CS2 characterizing the inductor current of the slave switching circuit is compared with the second valley reference signal IBOT and the second peak reference signal ITOP2, respectively, to control the on and off of the second main switching transistor M2 and the second auxiliary switching transistor M4. One slave control circuit controls one slave switching circuit, when a plurality of slave switching circuits exist, a plurality of corresponding slave control circuits are needed, any one slave control circuit can control the phase difference between the corresponding slave switching circuit and the master switching circuit to the expected phase difference, and the plurality of slave control circuits can simultaneously control the phase difference between the corresponding plurality of slave switching circuits and the master switching circuit to the expected phase difference respectively.
Fig. 3 illustrates a schematic diagram of a main control circuit of the present invention, which includes a main upper and lower limit adjusting circuit U201, a comparator U202, a comparator U203, a logic circuit U204 and a driving circuit U205, wherein the main upper and lower limit adjusting circuit U201 receives a reference signal IVC and a first difference signal Δvc1, and outputs an inductor current upper limit value ITOP1 and an inductor current lower limit value IBOT1 of a main switch circuit. The comparator U202 receives the first sampling signal CS1 at its non-inverting input terminal, receives the ITOP1 at its inverting input terminal, and outputs the signal VT1 at its output terminal, and when CS1 reaches ITOP1, the first main switching transistor M1 is turned off and the first auxiliary switching transistor M3 is turned on. The comparator U203 receives IBOT at its non-inverting input, receives the first sampling signal CS1 at its inverting input, outputs the signal VB1 at its output, and turns on the first main switching transistor M1 and turns off the first auxiliary switching transistor M3 when CS1 reaches IBOT. The logic circuit U204 receives VT1 and VB1 signals, outputs TG1 and BG1 signals, TG1 is a pulse width modulation signal of the first main switching transistor M1, BG1 is a modulation signal of the first auxiliary switching transistor M3, and the driving circuit receives TG1 and BG1, and outputs driving signals vg1_t and vg1_b, respectively.
Fig. 4 illustrates a schematic diagram of a slave control circuit of the present invention, which includes a phase difference detection circuit U301, a difference adjustment circuit U302, a slave upper and lower limit adjustment circuit, a comparator U304, a comparator U305, a logic circuit U306, and a drive circuit U307. The phase difference detection circuit U301 receives the first signal TG1 and the second signal TG2, outputs a phase difference signal Q representing a phase difference between the master switch circuit and the slave switch circuit, where the first signal TG1 and the second signal TG2 represent a signal that the first master switch tube is turned on and a signal that the second master switch tube is turned off, respectively. The difference value adjusting circuit U302 receives the pulse signal Q and the expected phase difference signal VREF2, outputs an adjusting signal DeltaVC, receives the adjusting signal DeltaVC, the reference signal IVC and the second difference value DeltaVC 2 from the upper limit adjusting circuit and outputs an upper limit value ITOP2 and a lower limit value IBOT2 of the inductance current of the switch circuit, wherein ITOP2-IBOT2 =DeltaVC2+DeltaVC; deltaVC2+DeltaVC is the adjusted second difference signal. The comparator U304 receives the second sampling signal CS2 at its non-inverting input terminal, receives the ITOP2 at its inverting input terminal, and outputs the signal VT2 at its output terminal, and when CS2 reaches ITOP2, the second main switching transistor M2 is turned off and the second auxiliary switching transistor M4 is turned on. The comparator U305 receives IBOT at its non-inverting input, receives the second sampling signal CS2 at its inverting input, and outputs the signal VB2 at its output, and when CS2 reaches IBOT2, the second main switching transistor M2 is turned on and the second auxiliary switching transistor M4 is turned off. The logic circuit U306 receives VT2 and VB2 signals, outputs TG2 and BG2 signals, TG2 is a pulse width modulation signal of the second main switching transistor M2, BG2 is a modulation signal of the second auxiliary switching transistor M4, and the driving circuit receives TG2 and BG2, and outputs driving signals vg2_t and vg2_b, respectively.
Fig. 5 illustrates a schematic diagram of a phase difference detection circuit including a pulse generation circuit U401 and a flip-flop U402, and a difference adjustment circuit including a first capacitor C401, a first comparator U403, an inverter, a first switch k1, a second switch k2, a first current source i1, a second current source i2, and a second capacitor C402. The pulse generating circuit U401 receives the first main switching tube pulse width modulation signal TG1 and the second main switching tube pulse width modulation signal TG2, and when the TG1 signal and the TG2 signal are respectively turned from low level to high level, the pulse generating circuit outputs a high level first pulse signal ph1 and a high level second pulse signal ph2 respectively. The setting end of the trigger U401 receives the first pulse signal ph1, the resetting end receives the second pulse signal ph2, and the output signal of the trigger is analog and is used as the phase difference signal. When the output signal of the trigger is digital, the output signal of the trigger is converted into analog quantity to be used as the phase difference signal. The first end of the first resistor R401 is connected with the output end of the trigger, the second end of the first resistor R401 is connected with the first end of the first capacitor C401, the second end of the first capacitor C401 is grounded, and the voltage on the first capacitor C401 is a first voltage V1. The inverting input terminal of the first comparator U403 receives V1, the non-inverting input terminal receives the second reference voltage VREF2, and the first comparator U403 outputs the first comparison signal Uon. When the phase difference of the two switch circuits is 180 degrees, the value of the second reference voltage VREF2 is half of the peak value of the signal Q, when the phase-dislocation conduction angle of the two switch circuits is 120 degrees, the value of the second reference voltage VREF2 is 1/3 of the peak value of the signal Q, and when the phase-dislocation conduction angle of the two switch circuits is N degrees, the value of the second reference voltage VREF2 is N/360 of the peak value of the signal Q. The first switch k1 and the first current source i1 are connected in series to form a first series circuit, the second switch k2 and the second current source i2 are connected in series to form a second series circuit, the common end of the first series circuit and the second series circuit is connected with the first end of the second capacitor C402, and the second end of the second capacitor C402 is grounded. The on-off of the first switch k1 and the second switch k2 is controlled by the first comparison signal Uon, when VREF1 is larger than V1, namely the first comparison signal Uon is at a high level, the first switch k1 is turned on, the second switch k2 is turned off, and the first current source i1 outputs a first current to charge the second capacitor C402; when VREF1< V1, i.e. the first comparison signal Uon is at a low level, the first switch k1 is turned off, the second switch k2 is turned on, the second current source i2 outputs a second current to discharge the second capacitor C402, and the voltage on the second capacitor C402 is the adjustment signal Δvc.
Fig. 6 illustrates waveforms of a staggered parallel switching power supply control circuit according to the present invention, TG1 and TG2 are waveforms of a first main switching tube pulse width modulation signal and a first main switching tube pulse width modulation signal, ph1 and ph2 are waveforms of a first pulse signal and a second pulse signal, CS1 is a main switching circuit inductor current waveform, CS2 is a slave switching circuit inductor current waveform, IBOT and IBOT are a main switching circuit inductor current lower limit value and a slave switching circuit inductor current lower limit value, IVC is a reference signal, and the reference signal IVC is located between the main switching inductor current upper limit value and the lower limit value, and IBOT1 and IBOT2 are the same in size. ITOP1 and ITOP2 are the upper limit value of the inductance current of the master switching circuit and the upper limit value of the inductance current of the slave switching circuit respectively, and Q is the waveform of the phase difference signal. According to sampling currents CS1 and CS2, signals TG1 and TG2 are obtained, a phase difference signal Q is obtained through the signals TG1 and TG2, an adjusting signal DeltaVC is obtained through processing the phase difference signal Q, a new difference DeltaVC 2 between ITOP2 and IBOT is obtained, and phase difference adjustment of a main switching circuit and a slave switching circuit can be achieved after a plurality of switching cycles.
Although the embodiments have been described and illustrated separately above, and with respect to a partially common technique, it will be apparent to those skilled in the art that alternate and integration may be made between embodiments, with reference to one embodiment not explicitly described, and reference may be made to another embodiment described.
The above-described embodiments do not limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the above embodiments should be included in the scope of the present invention.
Claims (15)
1. The utility model provides a staggered parallel type switching power supply control circuit, staggered parallel type switching power supply includes master switch circuit and from switch circuit, its characterized in that: the switching power supply control circuit comprises a first operational amplifier, wherein a first input end of the first operational amplifier receives feedback voltage, a second input end of the first operational amplifier receives first reference voltage, and the first operational amplifier outputs a reference signal which is used for controlling an upper limit value and a lower limit value of inductance current in the main switching circuit and an upper limit value and a lower limit value of inductance current in the auxiliary switching circuit;
The control circuit adjusts the upper and lower limit values of the inductance current in the slave switch circuit according to the phase difference of the master switch circuit and the slave switch circuit so as to enable the phase difference of the master switch circuit and the slave switch circuit to reach the expected phase difference.
2. The interleaved parallel switching power supply control circuit according to claim 1 wherein: the switching power supply control circuit further comprises a main control circuit, and the main control circuit obtains an upper limit value and a lower limit value of the inductance current in the main switching circuit according to the reference signal and the first difference signal; the first difference signal represents the difference value between the upper limit value and the lower limit value of the inductor current in the main switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the main switch circuit, or smaller than or equal to the lower limit value of the inductance current in the main switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the main switch circuit.
3. The interleaved parallel switching power supply control circuit according to claim 1 wherein: the switching power supply control circuit further comprises a slave control circuit, and when the phase difference between the master switching circuit and the slave switching circuit is larger than the expected phase difference, the slave control circuit reduces the upper limit difference value and the lower limit difference value of the inductance current in the slave switching circuit; the slave control circuit increases the upper and lower limit values of the inductor current in the slave switching circuit when the phase difference between the master switching circuit and the slave switching circuit is smaller than the expected phase difference.
4. The interleaved parallel switching power supply control circuit according to claim 3 wherein: the secondary control circuit obtains an upper limit value and a lower limit value of the inductance current in the secondary switch circuit according to the reference signal and a second difference signal, and the second difference signal represents the difference value between the upper limit value and the lower limit value of the inductance current in the secondary switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the slave switch circuit, or smaller than or equal to the lower limit value of the inductance current in the slave switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the slave switch circuit; the second difference signal is adjusted according to the phase difference of the master and slave switching circuits.
5. The interleaved parallel switching power supply control circuit according to claim 4 wherein: the slave control circuit further comprises a phase difference detection circuit, the phase difference detection circuit receives a first signal and a second signal and outputs a phase difference signal, the first signal represents a signal of the on-off of a main switch in the main switch circuit, and the second signal represents a signal of the on-off of a main switch tube in the slave switch circuit.
6. The interleaved parallel switching power supply control circuit according to claim 5 wherein: the first signal represents that when a main switch in the main switch circuit is turned on, the phase difference detection circuit outputs a phase difference signal; the second signal characterizes the phase difference signal level inversion when the main switch in the slave switch circuit is turned on.
7. The interleaved parallel switching power supply control circuit according to claim 6 wherein: the phase difference detection circuit comprises a pulse generation circuit and a trigger, wherein the pulse generation circuit receives the first signal and the second signal and outputs a first pulse signal and a second pulse signal; the trigger setting end receives the first pulse signal, the trigger resetting end receives the second pulse signal, and the trigger output signal is used as the phase difference signal or is converted to be used as the phase difference signal.
8. The interleaved parallel switching power supply control circuit according to claim 5 wherein: the slave control circuit further comprises a difference value adjusting circuit, the difference value adjusting circuit receives a phase difference signal, and when the phase difference between the master switch circuit and the slave switch circuit is larger than an expected phase difference, the first current is controlled to discharge the first capacitor; when the phase difference between the master switch circuit and the slave switch circuit is smaller than the expected phase difference, the second current is controlled to charge the first capacitor so as to obtain a regulating voltage, the regulating voltage regulates the second difference signal, and the regulating voltage represents the variation of the second difference signal.
9. The interleaved parallel switching power supply control circuit according to claim 8 wherein: the difference value adjusting circuit comprises a filter circuit and a comparator, wherein the filter circuit comprises a first resistor and a second capacitor, the first end of the first resistor is connected with the output end of the phase difference detecting circuit, the second end of the first resistor is connected with the first end of the second capacitor, the second end of the second capacitor is grounded, the upper voltage of the second capacitor is a first voltage, the first end of the comparator receives the first voltage, the second end of the comparator receives a second reference voltage, the comparator outputs a comparison signal, and the second reference voltage represents an expected phase difference.
10. The interleaved parallel switching power supply control circuit according to claim 9 wherein: the difference value adjusting circuit further comprises a first current source, a second current source and a first capacitor, wherein when the first voltage reaches a second reference voltage, the comparison signal controls the first current source to be conducted, and the first current is output; and when the first voltage does not reach the second reference voltage, the comparison signal controls the second current source to be conducted, and the second current is output.
11. A staggered parallel switching power supply control circuit as claimed in claim 1 or 2 or 3, wherein: the interleaved parallel switching power supply includes at least one slave switching circuit, and the switching power supply control circuit adjusts a phase difference of any one or more of the slave switching circuits and the master switching circuit to a desired phase difference.
12. A control method of a staggered parallel switching power supply is characterized by comprising the following steps of:
Obtaining a reference signal according to error amplification signals of the first reference voltage and the feedback voltage, wherein the reference signal is used for controlling an upper limit value and a lower limit value of an inductor current in a main switch circuit and an upper limit value and a lower limit value of the inductor current in a slave switch circuit;
And adjusting the upper and lower limit values of the inductance current in the slave switch circuit according to the phase difference of the master switch circuit and the slave switch circuit so as to enable the phase difference of the master switch circuit and the slave switch circuit to reach the expected phase difference.
13. The method for controlling an interleaved parallel switching power supply according to claim 12 wherein: obtaining an upper limit value and a lower limit value of the inductor current in the main switch circuit according to the reference signal and the first difference signal; the first difference signal represents the difference value between the upper limit value and the lower limit value of the inductor current in the main switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the main switch circuit, or smaller than or equal to the lower limit value of the inductance current in the main switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the main switch circuit.
14. The method for controlling an interleaved parallel switching power supply according to claim 12 wherein: when the phase difference between the master switch circuit and the slave switch circuit is larger than the expected phase difference, the slave control circuit reduces the upper limit value and the lower limit value of the inductance current in the slave switch circuit; the slave control circuit increases the upper and lower limit values of the inductor current in the slave switching circuit when the phase difference between the master switching circuit and the slave switching circuit is smaller than the expected phase difference.
15. The method for controlling an interleaved parallel switching power supply according to claim 14 wherein: obtaining an upper limit value and a lower limit value of the inductance current in the slave switch circuit according to the reference signal and a second difference signal, wherein the second difference signal represents the difference value between the upper limit value and the lower limit value of the inductance current in the slave switch circuit; the reference signal is larger than or equal to the upper limit value of the inductance current in the slave switch circuit, or smaller than or equal to the lower limit value of the inductance current in the slave switch circuit, or is positioned between the upper limit value and the lower limit value of the inductance current in the slave switch circuit; the second difference signal is adjusted according to the phase difference of the master and slave switching circuits.
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| CN106130321A (en) * | 2016-08-31 | 2016-11-16 | 杰华特微电子（张家港）有限公司 | The control method of a kind of on-off circuit, control circuit and switch circuit devices |
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| CN208581166U (en) * | 2018-07-05 | 2019-03-05 | 杰华特微电子（杭州）有限公司 | Staggered-parallel-type switching power source control circuit |
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