CN108598063A - Metal wire in conventional die and preparation method thereof - Google Patents
Metal wire in conventional die and preparation method thereof Download PDFInfo
- Publication number
- CN108598063A CN108598063A CN201810500067.XA CN201810500067A CN108598063A CN 108598063 A CN108598063 A CN 108598063A CN 201810500067 A CN201810500067 A CN 201810500067A CN 108598063 A CN108598063 A CN 108598063A
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- CN
- China
- Prior art keywords
- metal wire
- groove
- metal
- conventional die
- segment
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses the metal wires and preparation method thereof in a kind of conventional die, the part being located in metal wire in conventional die has first segment metal wire and second segment metal wire, and first segment metal wire and second segment metal wire can fuse by a constant current.Whereby, the metal wire in conventional die of the invention, metal wire are double break structure, are not in the case where metal wire is not blown completely using eFuse fuse metal lines, to improve fusing yield.
Description
Technical field
The present invention relates to chip design field, especially with regard in a kind of conventional die metal wire and its making side
Method.
Background technology
The full Life Cycle of chip can be can also be used as with personalizing chip by being disposably physically written certain codings in the chips
Phase identification, is widely used in all trades and professions.It is general in industry at present to be disposably physically written coding in the chips
Method has OTP and eFuse.OTP (One Time Programable) is a kind of type of memory of MCU, is meant disposable
It is programmable：By certain metal wires in the method fusing chip of laser burning, can not change and removing on chip makes physical is caused.
EFuse is to will also result in can not change and removing on chip makes physical by the way of electronics fuse metal line.
OTP fuses metal wire mature production technology in chip, simple, but production efficiency is low.With chip manufacturing
Technique enters Nano grade, and metal wire interval becomes smaller and smaller, this brings difficulty to the operation of OTP fuse metal lines.It adopts
Mode production efficiency with metal wire in eFuse fusing chips is higher, and production operation can be carried out on the chip of Nano grade,
But since fusing Energy distribution unevenness may cause metal wire not blow completely or metal when eFuse fuse metal lines
The phenomenon that line is again coupled to after high-temperature baking influences long term reliability.
Being disclosed in the information of the background technology part, it is only intended to increase understanding of the overall background of the invention, without answering
It has been the prior art well known to persons skilled in the art when being considered as recognizing or imply that the information is constituted in any form.
Invention content
The purpose of the present invention is to provide the metal wire and preparation method thereof in a kind of conventional die, metal wire is double break knot
Structure is not in the case where metal wire is not blown completely using eFuse fuse metal lines, to improve fusing yield.
To achieve the above object, one aspect of the present invention provides the metal wire in a kind of conventional die, position in the metal wire
There is first segment metal wire and second segment metal wire, and first segment metal wire and second segment metal wire in the part in conventional die
It can fuse by a constant current.
In a preferred embodiment, the first segment metal wire and second segment metal wire that can be fused are than remaining metal wire
Carefully.
The production method that another aspect of the present invention provides the metal wire in a kind of conventional die, includes the following steps：It carries
For semiconductor substrate, semiconductor substrate surface has the first passivation layer；The first passivation layer is patterned, it is recessed to be formed on its surface first
Slot；The first metal is deposited in the first groove and grinds the first extra metal, so that the first metal layer and the first passivation
Layer is concordant；The second passivation layer is deposited on the surface of the first passivation layer and the first metal layer；The second passivation layer is patterned, on its surface
Form the second groove, third groove and the 4th groove；And deposit the second gold medal in the second groove, third groove and the 4th groove
Belong to, the second extra metal is ground, so that second metal layer is concordant with the second passivation layer.
In a preferred embodiment, the depth of the first groove is less than the second groove, third groove and the 4th groove
Depth.
In a preferred embodiment, the material of the first passivation layer and the second passivation layer is silica.
In a preferred embodiment, the first metal layer and the material of second metal layer are copper.
Compared with prior art, metal wire in conventional die according to the present invention and preparation method thereof has following beneficial
Effect：Metal wire and preparation method thereof in the conventional die of the present invention, metal wire are double break structure, are fused using eFuse golden
It is not in the case where metal wire is not blown completely to belong to line, to improve fusing yield.
Description of the drawings
Fig. 1 is cuing open for the metal wire of metal wire in conventional die according to an embodiment of the present invention and preparation method thereof
Face structural schematic diagram.
Fig. 2 is the system of the metal wire of metal wire in conventional die according to an embodiment of the present invention and preparation method thereof
Make process schematic representation.
Main appended drawing reference explanation：
1- chips, 2- pads, 3- metal wires, 31- first segment metal wires, 32- second segment metal wires.
Specific implementation mode
Below in conjunction with the accompanying drawings, the specific implementation mode of the present invention is described in detail, it is to be understood that the guarantor of the present invention
Shield range is not restricted by specific implementation.
Unless otherwise explicitly stated, otherwise in entire disclosure and claims, term " comprising " or its change
It changes such as "comprising" or " including " etc. and will be understood to comprise stated element or component, and do not exclude other members
Part or other component parts.
As shown in Figure 1, according to the metal wire in a kind of conventional die of a preferred embodiment of the invention, the metal wire 3
In be located at conventional die 1 in part have first segment metal wire 31 and second segment metal wire 32, and first segment metal wire 31 and
Second segment metal wire 32 can fuse by a constant current.
In a preferred embodiment, the first segment metal wire 31 and second segment metal wire 32 that can be fused are than remaining gold
It is thin to belong to line 3.
As shown in Fig. 2, according to the making side of the metal wire in a kind of conventional die of another preferred embodiment of the present invention
Method includes the following steps：
Step 1：Semiconductor substrate is provided, semiconductor substrate surface has SiO2(silica), in SiO2Layer surface applies
It covers photoresist and is exposed, develops, etches, to be formed on its surface one than the first shallower groove；
Step 2：Copper is deposited in the first groove and grinds extra copper makes layers of copper and SiO2Concordant (the part copper of layer
Line can fuse at a certain current)；
Step 3：In layers of copper and SiO2The surface of layer deposits the 2nd SiO2Layer, in the 2nd SiO2Layer surface coats photoetching
Glue is simultaneously exposed, develops, etches, to be formed on its surface the second groove, third groove and the 4th groove；
Step 4：Copper is deposited in the second groove, third groove and the 4th groove, extra copper is ground and makes layers of copper and the
Two SiO2Layer is concordant.
In a preferred embodiment, the depth of the first groove is less than the second groove, third groove and the 4th groove
Depth；
In practical applications, the square small one by one above chip 1 represents a pad 2, when pad 2 is chip testing
Needle survey region.When using eFuse fuse metal lines 3, by applying voltage, metal wire 3 on the pad 2 on conventional die 1
By larger current, first segment metal wire 31 and second segment metal wire 32 can be blown (first segment metal wire 31
And second segment metal wire 32 is thinner than the metal wire 3 of other parts), go out cash so as to avoid using eFuse fuse metals line 3
Belong to the case where line 3 is not blown completely.
In short, the metal wire and preparation method thereof in the conventional die of the present invention, metal wire is double break structure, is used
EFuse fuse metal lines are not in the case where metal wire is not blown completely, to improve fusing yield.
The description of the aforementioned specific exemplary embodiment to the present invention is in order to illustrate and illustration purpose.These descriptions
It is not wishing to limit the invention to disclosed precise forms, and it will be apparent that according to the above instruction, can much be changed
And variation.The purpose of selecting and describing the exemplary embodiment is that explaining the specific principle of the present invention and its actually answering
With so that those skilled in the art can realize and utilize the present invention a variety of different exemplary implementation schemes and
Various chooses and changes.The scope of the present invention is intended to be limited by claims and its equivalents.
Claims (6)
1. the metal wire in a kind of conventional die, which is characterized in that be located at the part in the conventional die in the metal wire
With first segment metal wire and second segment metal wire, and the first segment metal wire and the second segment metal wire can pass through
It fuses in the case of one constant current.
2. the metal wire in conventional die as described in claim 1, which is characterized in that the first segment metal that can be fused
Line and the second segment metal wire are thinner than metal wire described in remaining.
3. a kind of production method of the metal wire in conventional die, which is characterized in that include the following steps：
Semiconductor substrate is provided, the semiconductor substrate surface has the first passivation layer；
First passivation layer is patterned, the first groove is formed on its surface；
The first metal is deposited in first groove and grinds extra first metal, so that first metal
Layer is concordant with first passivation layer；
The second passivation layer is deposited on the surface of first passivation layer and the first metal layer；
Second passivation layer is patterned, the second groove, third groove and the 4th groove are formed on its surface；And
The second metal is deposited in second groove, the third groove and the 4th groove, grinds extra described
Two metals, so that the second metal layer is concordant with second passivation layer.
4. the production method of the metal wire in conventional die as claimed in claim 3, which is characterized in that first groove
Depth is less than the depth of second groove, the third groove and the 4th groove.
5. the production method of the metal wire in conventional die as claimed in claim 3, which is characterized in that first passivation layer
Material with second passivation layer is silica.
6. the production method of the metal wire in conventional die as claimed in claim 3, which is characterized in that the first metal layer
Material with the second metal layer is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810500067.XA CN108598063B (en) | 2018-05-23 | 2018-05-23 | Metal wire in conventional chip and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810500067.XA CN108598063B (en) | 2018-05-23 | 2018-05-23 | Metal wire in conventional chip and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108598063A true CN108598063A (en) | 2018-09-28 |
| CN108598063B CN108598063B (en) | 2020-05-26 |
Family
ID=63632663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810500067.XA Active CN108598063B (en) | 2018-05-23 | 2018-05-23 | Metal wire in conventional chip and manufacturing method thereof |
Country Status (1)
| Country | Link |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5882998A (en) * | 1996-12-27 | 1999-03-16 | Vlsi Technology, Inc. | Low power programmable fuse structures and methods for making the same |
| CN1909227A (en) * | 2005-08-03 | 2007-02-07 | 国际商业机器公司 | Programmable semiconductor device and methods of making and using same |
| CN103633065A (en) * | 2012-08-15 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Electric fuse and programming method of electric fuse |
| CN107393843A (en) * | 2016-05-17 | 2017-11-24 | 格罗方德半导体公司 | The gate protection applied for high voltage stress |
-
2018
- 2018-05-23 CN CN201810500067.XA patent/CN108598063B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5882998A (en) * | 1996-12-27 | 1999-03-16 | Vlsi Technology, Inc. | Low power programmable fuse structures and methods for making the same |
| CN1909227A (en) * | 2005-08-03 | 2007-02-07 | 国际商业机器公司 | Programmable semiconductor device and methods of making and using same |
| CN103633065A (en) * | 2012-08-15 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Electric fuse and programming method of electric fuse |
| CN107393843A (en) * | 2016-05-17 | 2017-11-24 | 格罗方德半导体公司 | The gate protection applied for high voltage stress |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108598063B (en) | 2020-05-26 |
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