CN108574565A - A kind of S mode transmitter signal quality detection device and method - Google Patents

A kind of S mode transmitter signal quality detection device and method Download PDF

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Publication number
CN108574565A
CN108574565A CN201810379611.XA CN201810379611A CN108574565A CN 108574565 A CN108574565 A CN 108574565A CN 201810379611 A CN201810379611 A CN 201810379611A CN 108574565 A CN108574565 A CN 108574565A
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China
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ads
signal
voltage
analog
digital
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Inventor
刘志勇
林琳
刘引川
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Sichuan Ando Fast Science And Technology Co Ltd
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Sichuan Ando Fast Science And Technology Co Ltd
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Priority to CN201810379611.XA priority Critical patent/CN108574565A/en
Publication of CN108574565A publication Critical patent/CN108574565A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/20Arrangements for detecting or preventing errors in the information received using signal quality detector
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B17/00Monitoring; Testing
    • H04B17/10Monitoring; Testing of transmitters
    • H04B17/15Performance testing

Abstract

The invention discloses a kind of S mode transmitter signal quality detection device and methods,It is related to transmitter detection technique field,Including power management,Radiofrequency signal for emitting ADS B transmitters is converted to the buffer cell of linear voltage,Converting unit for carrying out signal amplification and DC voltage bias to linear voltage all the way,For being assembled into ADS B data messages after synchronizing head detection and PPM decodings to another way linear voltage,And the decoding unit of digital signal is converted to after being sampled to the analog voltage signal after amplification and DC voltage bias,The ADS B data messages of digital signal and reception ADS B data decoded portions output for reading analog-to-digital conversion part,And the control unit analyzed and exported after being handled,The present invention solves the prior art can not be quick,Qualitatively detection ADS B transmitter states and can not be accurately,The problem of quantitatively obtaining ADS B transmitter parameters.

Description

A kind of S mode transmitter signal quality detection device and method
Technical field
The present invention relates to transmitter detection technique field, more particularly to a kind of S mode transmitter signal quality detection device And method.
Background technology
ADS-B transmitters are a kind of devices that can send aircraft ADS-B broadcast messages, are had the flight of aircraft Number, the function that is sent out in the form of broadcasting of the addresses ICAO, longitude and latitude, height, speed, grade, the information such as course.
Currently, ADS-B transmitters are generally by transmitting a signal to another receiving terminal to determine whether normal work, implements It is next cumbersome, it is time consuming, do not have setting for the complete detection that profession can be carried out to ADS-B transmitters yet in the market It is standby, it can not accurately judge whether a certain index of ADS-B transmitters or parameter are normal, therefore, it is necessary to which designing one kind can be right ADS-B transmitters carry out quickly the simultaneously equipment of complete detection.
Invention content
It is an object of the invention to:A kind of S mode transmitter signal quality detection device and method are provided, is solved existing There is technology that can not quickly, qualitatively detect ADS-B transmitter states and can not accurately, quantitatively obtain ADS-B transmitters ginseng Several problems.
The technical solution adopted by the present invention is as follows:
A kind of S mode transmitter signal quality detection device, including power management, buffer cell, converting unit, decoding list Member, control unit, output unit;
Buffer cell:Radiofrequency signal for emitting ADS-B transmitters is converted to linear voltage;
Converting unit:For carrying out signal amplification and DC voltage bias to linear voltage all the way;
Decoding unit:For being assembled into ADS-B after synchronizing head detection and PPM decodings to another way linear voltage Data message, and be converted to digital signal after being sampled to the analog voltage signal after amplification and DC voltage bias;
Control unit:What digital signal and reception ADS-B data decoding portions for reading analog-to-digital conversion part exported ADS-B data messages, and analyzed and exported after being handled.
Further, the buffer cell includes declining of decaying of radiofrequency signal for emitting ADS-B transmitters Subtract device and carries out the logarithmic detector of linear detection for the signal after decaying.
Further, the converting unit include to linear voltage all the way carry out signal amplification operational amplifier and The baseline offset of DC voltage bias is carried out to amplified voltage signal.
Further, the decoding unit includes ADS-B data decoding portions and analog-to-digital conversion part.
Further, the ADS-B data decoding portions include being digitized place to another way linear voltage The 1bit digital modules of reason, digital pulse signal is synchronized head detection and the decoded decoders of PPM, and to decoding after The ADS-B data outputting modules that are assembled of signal.
Further, the Analog to Digital Converter section point includes being converted to digital signal after being sampled to analog voltage signal Analog-digital converter, store the FIFO memory of digital signal, and provide synchronous work with FIFO memory for analog-digital converter Make the clocked logic module of clock sclk.
Further, sampling lock modules are additionally provided between the decoder and FIFO memory.
Further, the output unit includes keyboard and display screen, and the index of whole system is completed in cooperation, waveform is shown And mutual parameter setting.
A kind of S mode transmitter signal quality determining method, includes the following steps:
Step 1:The radiofrequency signal that ADS-B transmitters emit is converted into linear voltage and is exported;
Step 2:Signal amplification and DC voltage bias are carried out to linear voltage all the way;
Step 3:It is assembled into ADS-B datagrams after synchronizing head detection and PPM decodings to another way linear voltage Text, and be converted to digital signal after being sampled to the analog voltage signal after amplification and DC voltage bias;
Step 4:It reads the digital signal of analog-to-digital conversion part and receives the ADS-B numbers of ADS-B data decoding portions output According to message, and is analyzed and exported after being handled.
In conclusion by adopting the above-described technical solution, the beneficial effects of the invention are as follows:
1. a kind of S mode transmitter signal quality detection device and method can accurately, quantitatively obtain the power of transmitter The watt level of size, the waveform parameter and single pulse of each PPM coded excitations pulse, while can also be by waveform and test Parametric results are intuitively shown, are checked convenient for user;
2. the present invention can not only detect the state of transmitter in outfield fast qualitative, moreover it is possible to as a kind of dedicated interior Field detecting equipment;
3. Analog to Digital Converter section of the present invention point includes the FIFO memory of storage digital signal, user can data not more Repeatedly from collected data before reading in FIFO memory before new, then shown in a manner of text or figure, it is convenient Follow-up consult uses;
4. analog-to-digital conversion part of the present invention further includes providing synchronous working clock for analog-digital converter and FIFO memory The clocked logic module of SCLK, analog-digital converter stop follow-up data after having acquired a frame ADS-B signals and preserve to control Unit reads the data in FIFO memory in time;
5. ADS-B data decoding portions of the present invention include being digitized the 1bit of processing to another way linear voltage Digital module, the 1bit digital modules can simply and effectively convert analog signals into traffic flow information.
Description of the drawings
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is a kind of functional block diagram of S mode transmitter signal quality detection device;
Fig. 2 is the output linear graph of logarithmic detector of the present invention;
Fig. 3 is the structure chart of FIFO memory of the present invention;
Fig. 4 is the digitized schematic diagrams of 1bit of the present invention;
Fig. 5 is the decoder functions flow chart of step 7.
Specific implementation mode
All features disclosed in this specification or disclosed all methods or in the process the step of, in addition to mutually exclusive Feature and/or step other than, can combine in any way.
It elaborates to the present invention with reference to Fig. 1 to Fig. 5.
A kind of S mode transmitter signal quality detection device, including power management, buffer cell, converting unit, decoding list Member, control unit, output unit;
Buffer cell:Radiofrequency signal for emitting ADS-B transmitters is converted to linear voltage;
Converting unit:For carrying out signal amplification and DC voltage bias to linear voltage all the way;
Decoding unit:For being assembled into ADS-B after synchronizing head detection and PPM decodings to another way linear voltage Data message, and be converted to digital signal after being sampled to the analog voltage signal after amplification and DC voltage bias;
Control unit:What digital signal and reception ADS-B data decoding portions for reading analog-to-digital conversion part exported ADS-B data messages, and analyzed and exported after being handled.
Further, the buffer cell includes declining of decaying of radiofrequency signal for emitting ADS-B transmitters Subtract device and carries out the logarithmic detector of linear detection for the signal after decaying.
Further, the converting unit include to linear voltage all the way carry out signal amplification operational amplifier and The baseline offset of DC voltage bias is carried out to amplified voltage signal.
Further, the decoding unit includes ADS-B data decoding portions and analog-to-digital conversion part.
Further, the ADS-B data decoding portions include being digitized place to another way linear voltage The 1bit digital modules of reason, digital pulse signal is synchronized head detection and the decoded decoders of PPM, and to decoding after The ADS-B data outputting modules that are assembled of signal.
Further, the Analog to Digital Converter section point includes being converted to digital signal after being sampled to analog voltage signal Analog-digital converter, store the FIFO memory of digital signal, and provide synchronous work with FIFO memory for analog-digital converter Make the clocked logic module of clock sclk.
Further, sampling lock modules are additionally provided between the decoder and FIFO memory.
Further, the output unit includes keyboard and display screen, and the index of whole system is completed in cooperation, waveform is shown And mutual parameter setting.
A kind of S mode transmitter signal quality determining method, includes the following steps:
Step 1:The radiofrequency signal that ADS-B transmitters emit is converted into linear voltage and is exported;
Step 2:Signal amplification and DC voltage bias are carried out to linear voltage all the way;
Step 3:It is assembled into ADS-B datagrams after synchronizing head detection and PPM decodings to another way linear voltage Text, and be converted to digital signal after being sampled to the analog voltage signal after amplification and DC voltage bias;
Step 4:It reads the digital signal of analog-to-digital conversion part and receives the ADS-B numbers of ADS-B data decoding portions output According to message, and is analyzed and exported after being handled.
The operation principle of the present invention is that:
The radiofrequency signal of ADS-B transmitters transmitting is linked into the prevention at radio-frequency port of the present apparatus, passes through declining for device buffer cell After subtracting device, the output signal of transmitter is reduced to 0dBm hereinafter, being then input to logarithmic detector AD8313, logarithmic detector The linear detection voltage signal of 20mV/dB is obtained in -60~0dBm input reference signals and is exported, and is accurate power measurement Basis is provided.
Signal after logarithmic detector detection is divided into two-way output:It is output to converting unit all the way, by operational amplifier The signal conditioning circuit of LT1801 compositions carries out signal amplification, then carries out DC voltage bias by baseline offset, until being suitble to mould It is just exported in the collectable ranges of analog-digital converter ADS830 of number conversion portion;Another way is then output to the ADS- of decoding unit B data decoded portion synchronizes head detection to ADS-B signals and PPM is decoded.
The output linear graph of logarithmic detector according to fig. 2, since logarithmic detector AD8313 is in -60dBm input signals When, detection DC output voltage is in 0.5V or so, and when maximum 0dBm is inputted, detection DC output voltage in 1.7V or so, Therefore, maximum variation voltage is in the linear input dynamic ranges of entire 60dB:△ V=1.7-0.5=1.2V.So signal Modulate circuit amplification factor is set as 2/1.2=1.67 times, and the 2V of analog-digital converter ADS830 is just suitble to expire amplitude Vpp inputs Then the resolution ratio of analog-digital converter ADS830 is designed as maximum by range:2V/28=7.8125mV.
Further according to above formula, the detection linearity slope of logarithmic detector is designed as 20mV/dB, it is dynamic in entire 60dB Within the scope of state, every millivolt of voltage is equivalent to performance number and is:60dB/2000mV=0.03dB/mV due to the resolution of analog-digital converter Rate is 7.8125mV, then Theoretical Design power resolution is 7.8125*0.03=0.234375dB, is entirely capable of in actual demand Enough needs for meeting inside and outside field detecting.
It is 2.5V since analog-digital converter ADS830 uses differential reference voltage mode, common mode terminal DC voltage, maximum permits Perhaps input analog voltage is ± 1V, and the input voltage range for 0V reference voltage ends is 1.5~3.5V, therefore, baseline offset The voltage that circuit exports logarithmic detector adjusts to direct current 1.5V and exports, use double operational TL1801 when -60dBm is inputted In one, be designed as adder pattern, pass through trimmer potentiometer adjust amplifier Static output level, it is ensured that input signal When≤- 60dBm, output voltage 1.5V, while adjusting potentiometer, when to make input signal be 0dBm, output voltage 3.5V.
The sample rate of analog-digital converter ADS830 is up to 60M, and high resolution reaches 8bit, fully meets the 1MHz tune of ADS-B The analog voltage of output is sampled and is converted to digital signal by the acquisition of the PPM signal of system, is then stored in FIFO storages Device.According to being Qwest's theorem, sample frequency be at least measured signal highest frequency 2 times could reappear measured signal, this Invention samples PPM signal using 32 sampling rates, and original analog is true as far as possible after reduction logarithmic detector Property.The case where for the most narrow pulse width of the PPM signal of ADS-B being 0.5us, in the case of 32M sample rates, pulse takes Sampling point is 16 points, i.e., each pulse in face can show 16 pixels on a liquid crystal display, it is contemplated that trade off performance and realization Cost, the index have good cost performance.The measure theory value of pulse width is 0.5us/16=0.03125us, energy simultaneously Enough meet the requirement for 0.05~0.1us of pulse width tolerance that international standard RTCA DO260B are defined.
The FIFO memory uses IDT7205 high speed FIFO storages, is a kind of SRAM of twoport, this memory does not have There is address wire, increments or decrements is carried out with being written or reading data signal address pointer, to realize that memory block addresses.In mould FIFO memory is added between number converter and control unit, plays the role of fast data buffer.Because of analog-digital converter Maximum operating frequency be 32MHz, be far above the processing capacity of MCU processor, so as not to the data that sample of analog-digital converter because It is lost to have little time processing, so allowing FIFO memory to work asynchronously with analog-digital converter stores the output number of analog-digital converter According to.
FIFO memory structure chart according to fig. 3, FIFO memory have 3 flag bit pins, respectively FF (full scale will: After memory is filled with internal storage areas, the set mark, at this time memory will ignore all data writing operations);HF is (half-full Mark:After memory is filled with half storage region, the set mark);EF (sky marks:When memory content is read empty, set Position the mark, at this time memory ignore all read data manipulations).The present invention is indicated using HF, is deposited for MCU processor and FIFO The crosslinking of reservoir reset terminal, the ADS-B information before the arrival of ADS-B synchronous triggering signals before storage synchronous head, Yi Mian Detect that restarting analog-digital converter storage data after ADS-B synchronous heads causes front end signal to be lost.
The Capacity Selection of FIFO memory of the present invention, calculates as follows:
FIFOsize=2 (Sclk*TADS-B)
Wherein, FIFOsizeIt is selected for FIFO memory total capacity, unit is byte;SclkFor the sampling of analog-digital converter Rate, unit are hertz, are herein 32MHz;TADS-BFor the sampling time, unit is the second;It can be with according to international standard RTCA DO260B Know that a frame ADS-B message lengths are 120us, can derive, FIFOsize=2 (32000000*0.00012)=7680 words Section.Therefore, it is 8K bytes (8192byte) that FIFO memory, which uses IDT7205 high speed FIFO storages, the IC capacity, meets system The basic demand for 7680 bytes of uniting.
In the formula of above-mentioned selection FIFO memory capacity, the reason of needing at least 2 sampling time, is:HF in the present invention The FIFO of signal and MCU automatically reset after enable signal (FIFO_AUTO_RST_EN) progress logical AND, control FIFO memory Clearing pin, when FIFO_AUTO_RST_EN is effective, and FIFO memory storage is to after a half space, if ADS-B numbers ADS-B synchronous heads are not detected according to decoded portion, while HF signals are effective, FIFO memory resetting pin can be triggered (15ns), FIFO memory automatically resets, then HF signals also remove (25ns) after the reset, and FIFO memory starts to deposit automatically again Store up sampled data;When FIFO memory is during being automatically stored sampled data, if ADS-B data decoding portions detect ADS-B synchronous heads, FIFO memory then export trigger signal and send out FIFO_AUTO_RST_EN after judgement to MCU, MCU and close Lock signal does not allow FIFO memory automatic clear, and FIFO memory continues to store sampled data at this time, after 120us Actively stop FIFO memory write operation by MCU.
The analog-to-digital conversion part further includes providing synchronous working clock sclk for analog-digital converter and FIFO memory The SCLK of clocked logic module, analog-digital converter part is in continuous operation state, and the SCLK of FIFO memory part is in Uncontrolled operating state, it is therefore an objective to stop subsequent analog-digital conversion data after having acquired a frame ADS-B signals and preserve, so as to MCU The data in FIFO memory are read in time.SCLK is output to the ports WR of FIFO memory, by being controlled by MCU with door mode CLK_EN mouths.MCU reads FIFO memory in time, obtains the analog-to-digital conversion being stored in before stopping sampling in FIFO memory Data are again started up after reading after allowing FIFO memory write operation, MCU to obtain analog-digital conversion data, carry out data It analyzes and is shown on liquid crystal display.
Another way is input to the signal of decoding unit, due to logarithmic detector output analog pulse signal amplitude with defeated Enter signal into logarithmic relationship, influenced by input signal strength, output amplitude value and width are unfixed, therefore cannot be direct It is sent to ADS-B data decoding portions and is digitized judgement, need through 1bit digitized processings, by the simulation arteries and veins of dynamic change The logic-level digital pulse signal that signal becomes single is rushed, being sent to decoder as Utopian 1bit data flows is solved Code.According to the 1bit digitalization principle figures of Fig. 4, using a high-speed comparator as core component, original rectified signal by than It is inputted compared with device anode, comparator negative terminal couples a part by original signal and carries out RC integrals, and strictly adjusts integral parameter, allows ratio 3dB low compared with device negative terminal Amplitude Ratio anode or so, such comparator just exports carefully and neatly done pulse square wave, reaches 1bit quantization purposes.
According to the decoder functions flow chart of Fig. 5, decoder parses the digital pulse signal after quantization, specific to flow Cheng Wei:Decoder initializes the pulse signal after quantization;Capture synchronous head, and cache synchronization header sequence;Judge to synchronize Head carries out follow-up bit captures if correct judgment;If misjudgment, recapture synchronous head;The follow-up bit of capture, into Row bit sequences buffer;Judge whether bit captures are completed, if completing, carries out CRC check;If not completing, recapture Follow-up bit;Judge whether CRC check is correct, if correctly, sending decoding message and being exported to ADS-B data;If check errors, Then return to recapture synchronous head.It is assembled into ADS-B data-message transmissions after synchronous head judgement, CRC check inspection are errorless Processing is interacted to the output of ADS-B data.
Sampling lock modules are additionally provided between the decoder and FIFO memory, when FIFO memory is being automatically stored During sampled data, if after the decoder of ADS-B data decoding portions detects ADS-B synchronous head signals, just locking is worked as The reset signal of preceding FIFO memory, makes FIFO memory no longer be deactivated data reset, to carry out working as former frame ADS-B Data information preserves, then the continuous acquisition at least data information of 120us.
Control unit uses MCU processor, reads FIFO memory, obtains analog-digital converter and stops being stored in before sampling Sampled data in FIFO memory and analog-digital conversion data, and obtain the ADS-B decodings that the output of ADS-B data is transmitted to MCU Data carry out MCU processing analyses, are shown by display unit.
The index of display unit and input unit cooperation completion whole system, waveform is shown and mutual parameter is arranged Deng.The input unit is inputted using keyboard, and the display unit uses 320*240 dot matrix TFT liquid crystal displays, is shown displayed across 320 points can be with 1 under waveform display interface:The sampled point of 1 display 320, i.e. the PPM coding waveforms of 10us length.It is whole Frame ADS-B waveform single screens need point 12 displays to finish, and cooperation keyboard operation, which can be moved left and right easily, checks that display is concerned about Impulse waveform.On wave-shape amplitude is shown, since analog-digital converter uses 8 bit resolutions, indication range from 0~255, according to Parameter above-mentioned converts and indicates that 0.234375dB power, liquid crystal display vertical direction resolution ratio are 240 for per unit, so Each pixel represents 60/240=0.25dB.
Liquid crystal display finally obtains the power waveform of ADS-B transmitters, pulse parameter width, rising edge of a pulse, pulse The information such as failing edge, raw decoded data, the addresses aircraft ICAO, flight number, longitude and latitude, height, speed, course, and to scheme Shape and text mode are shown, are checked convenient for user.
The present invention can accurately, quantitatively obtain the watt level of transmitter, the waveform parameter of each PPM coded excitations pulse With the watt level of single pulse, while waveform and the parametric results of test can also intuitively be shown, be convenient for user It checks, it not only can be in outfield fast qualitative detection transmitter state, moreover it is possible to as a kind of dedicated internal field detection device.
The above, only the preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto, it is any Those skilled in the art within the technical scope disclosed by the invention, can without the variation that creative work is expected or It replaces, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be limited with claims Subject to fixed protection domain.

Claims (9)

1. a kind of S mode transmitter signal quality detection device, it is characterised in that:It is single including power management, buffer cell, conversion Member, decoding unit, control unit, output unit;
Buffer cell:Radiofrequency signal for emitting ADS-B transmitters is converted to linear voltage;
Converting unit:For carrying out signal amplification and DC voltage bias to linear voltage all the way;
Decoding unit:For being assembled into ADS-B data after synchronizing head detection and PPM decodings to another way linear voltage Message, and be converted to digital signal after being sampled to the analog voltage signal after amplification and DC voltage bias;
Control unit:The ADS-B of digital signal and reception ADS-B data decoding portions output for reading analog-to-digital conversion part Data message, and analyzed and exported after being handled.
2. a kind of S mode transmitter signal quality detection device according to claim 1, it is characterised in that:The buffering Unit include the attenuator that the radiofrequency signal for emitting ADS-B transmitters decays and for the signal after decaying into The logarithmic detector of row linear detection.
3. a kind of S mode transmitter signal quality detection device according to claim 1, it is characterised in that:The conversion Unit includes carrying out the operational amplifier of signal amplification to linear voltage all the way and being carried out to amplified voltage signal straight Flow the baseline offset of voltage bias.
4. a kind of S mode transmitter signal quality detection device according to claim 1, it is characterised in that:The decoding Unit includes ADS-B data decoding portions and analog-to-digital conversion part.
5. a kind of S mode transmitter signal quality detection device according to claim 4, it is characterised in that:The ADS-B Data decoding portion includes being digitized the 1bit digital modules of processing, to digit pulse to another way linear voltage Signal synchronizes head detection and the decoded decoders of PPM, and the ADS-B data assembled to decoded signal export Module.
6. a kind of S mode transmitter signal quality detection device according to claim 4, it is characterised in that:The modulus Conversion portion includes the analog-digital converter that digital signal is converted to after being sampled to analog voltage signal, storage digital signal FIFO memory, and the clocked logic module of synchronous working clock sclk is provided for analog-digital converter and FIFO memory.
7. a kind of S mode transmitter signal quality detection device according to claim 5 or 6, it is characterised in that:The solution It is additionally provided with sampling lock modules between code device and FIFO memory.
8. a kind of S mode transmitter signal quality detection device according to claim 1, it is characterised in that:The output Unit includes keyboard and display screen, and the index of whole system is completed in cooperation, waveform is shown and mutual parameter setting.
9. a kind of S mode transmitter signal quality determining method, which is characterized in that include the following steps:
Step 1:The radiofrequency signal that ADS-B transmitters emit is converted into linear voltage and is exported;
Step 2:Signal amplification and DC voltage bias are carried out to linear voltage all the way;
Step 3:ADS-B data messages are assembled into after synchronizing head detection and PPM decodings to another way linear voltage, and Digital signal is converted to after being sampled to the analog voltage signal after amplification and DC voltage bias;
Step 4:It reads the digital signal of analog-to-digital conversion part and receives the ADS-B datagrams of ADS-B data decoding portions output Text, and analyzed and exported after being handled.
CN201810379611.XA 2018-04-25 2018-04-25 A kind of S mode transmitter signal quality detection device and method Pending CN108574565A (en)

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