CN108574476A - Clock generation circuit and electronic system - Google Patents
Clock generation circuit and electronic system Download PDFInfo
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- CN108574476A CN108574476A CN201710131316.8A CN201710131316A CN108574476A CN 108574476 A CN108574476 A CN 108574476A CN 201710131316 A CN201710131316 A CN 201710131316A CN 108574476 A CN108574476 A CN 108574476A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
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Abstract
A kind of clock generation circuit and electronic system, clock generation circuit include：First charge-discharge circuit and the first capacitance, the first charge-discharge circuit is in response to the different logic level of the first control voltage, to the first capacitor charging or electric discharge；First comparator is adapted to compare the first capacitance both end voltage and reference voltage, to export the first comparison voltage；Second charge-discharge circuit and the second capacitance, the second charge-discharge circuit is in response to the different logic level of the second control voltage, to the second capacitor charging or electric discharge；Second comparator is adapted to compare the second capacitance both end voltage and reference voltage, to export the second comparison voltage；Bi-stable latch, reverse phase and with phase latch point be suitable for latch the first and second comparison voltages respectively；Self-excitation elimination circuit, suitable for carrying out logical operation to the first comparison voltage being latched to obtain the second control voltage, and the second comparison voltage to being latched carries out logical operation to obtain the first control voltage.The present invention program can eliminate circuit self-excitation.
Description
Technical field
The present invention relates to electronic circuit design field, more particularly to a kind of clock generation circuit and electronic system.
Background technology
In applications of electronic circuitry, clock generation circuit is one of essential circuit module.According to different applications
Scene demand, there is a plurality of types of clock generation circuits.Wherein, relaxor is a kind of common clock generation electricity
Road, relaxor are by determining the clock signal frequency of circuit output to the periodic charge and discharge of capacitance.
A kind of clock generation circuit formed by relaxor exists in the prior art, circuit diagram refers to figure
1.Clock generation circuit 100 shown in FIG. 1 may include：NMOS tube M1, NMOS tube M2, PMOS tube M3 and PMOS tube M4, wherein
The grid that the grid of NMOS tube M1 and PMOS tube M3 receive the first control voltage sa, NMOS tube M2 and PMOS tube M4 receives the second control
Voltage sb processed；First capacitance C1 and the second capacitance C2；First comparator Cpa and the second comparator Cpb；By phase inverter Naa and instead
The bi-stable latch 101 of phase device Nab compositions；Reference current source 102 and reference voltage source 103.
Wherein, in normal operation, the level logic phase of the first control voltage sa and the second control voltage sb
Instead so that the first capacitance C1 and the second capacitance C2 are alternately charged, and charging current Ir can be by the reference current
Source 102 provides；When the voltage va at the both ends the first capacitance C1 is more than the reference voltage Vr that the reference voltage source 103 exports
When, the output level logic overturning of the first comparator Cpa, similarly, when the voltage vb at the both ends the second capacitance C2 is more than
When the reference voltage Vr, the output level logic of the second comparator Cpb is overturn；The bi-stable latch 101 can be with
The output level logic of the first comparator Cpa and the second comparator Cpb are latched, latch result is respectively as institute
State the control voltages of the first control voltage sa and second sb.Two latch points of the bi-stable latch 101 are suitable for output two-way
The clock signal of mutual reverse phase namely the first control voltage sa and the second control voltage sb.
There are a potential feedback network in above-mentioned clock generation circuit 100, self-oscillation can be caused so that when described
The clock signal that clock generation circuit 100 exports is abnormal.Although there is also the response times by reducing comparator in the prior art
It reduces above-mentioned self-oscillation odds, but such case can not be inherently eliminated.
Invention content
Present invention solves the technical problem that being how to be inherently eliminated the self-excitation of clock generation circuit in the prior art
Oscillation.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of clock generation circuit, the clock generation circuit
Including：First charge-discharge circuit, control terminal receive the first control voltage；First capacitance, with first charge-discharge circuit
Output end couples, and in response to the different logic level of the first control voltage, first charge-discharge circuit is to described first
Capacitor charging or electric discharge；First comparator is adapted to compare the voltage and reference voltage at first capacitance both ends, to export
One comparison voltage；Second charge-discharge circuit, control terminal receive the second control voltage；Second capacitance, with second charge and discharge
The output end of circuit couples, and in response to the different logic level of the second control voltage, second charge-discharge circuit is to institute
State the second capacitor charging or electric discharge；Second comparator is adapted to compare the voltage at second capacitance both ends and the reference electricity
Pressure, to export the second comparison voltage；Bi-stable latch has with phase latch point and reverse phase latch point, the reverse phase latch point
Suitable for latching first comparison voltage, the same phase latch point is suitable for latching second comparison voltage；Further include：Self-excitation disappears
Except circuit, coupled with the same phase latch point and reverse phase latch point, suitable for patrolling first comparison voltage being latched
Operation is collected, to obtain the second control voltage, and second comparison voltage to being latched carries out logical operation, with
To the first control voltage.
Optionally, the self-excitation elimination circuit includes：First NAND gate, first input end couple the reverse phase and latch
Point, output end output the second control voltage；Second NAND gate, first input end couple the same phase latch point,
Output end output the first control voltage；The second of second input terminal of first NAND gate and second NAND gate is defeated
Enter end and accesses enable signal.
Optionally, the enable signal includes that the rising edge of logic high is changed to from logic low.
Optionally, the self-excitation elimination circuit includes：First phase inverter, input terminal couple the reverse phase latch point,
Output end output the second control voltage；Second phase inverter, input terminal couple the same phase latch point, output end output
The first control voltage.
Optionally, first charge-discharge circuit includes：First switch, control terminal receive the first control voltage,
Its first end receives reference current, and second end couples the output end of first charge-discharge circuit, and the first switch is in institute
It states when the first control voltage is the first logic level and is connected；Second switch, control terminal receive the first control voltage, the
One end couples the output end of first charge-discharge circuit, and the second switch is different from described in the first control voltage
It is connected when the second logic level of the first logic level.
Optionally, second charge-discharge circuit includes：Third switchs, and control terminal receives the second control voltage,
Its first end receives the reference current, and second end couples the output end of second charge-discharge circuit, the third switch
It is connected when the second control voltage is first logic level；4th switch, control terminal receive second control
Voltage, first end couple the output end of second charge-discharge circuit, and the 4th switch is in the second control voltage
It is connected when second logic level.
Optionally, the clock generation circuit further includes：Current source is adapted to provide for the reference current.
Optionally, the clock generation circuit further includes：Voltage source is adapted to provide for the reference voltage.
In order to solve the above technical problems, the embodiment of the present invention also provides a kind of electronic system, including above-mentioned clock generates electricity
Road and the operating circuit that clock signal is provided by the clock generation circuit, wherein the second input of first NAND gate
Second input terminal of end and second NAND gate couples the power input of the operating circuit.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
The clock generation circuit of the embodiment of the present invention includes：First charge-discharge circuit and the first capacitance, first charge and discharge
Circuit is in response to the different logic level of the first control voltage, to first capacitor charging or electric discharge；First comparator,
It is adapted to compare the first capacitance both end voltage and reference voltage, to export the first comparison voltage；Second charge-discharge circuit and
Two capacitances, second charge-discharge circuit is in response to the different logic level of the second control voltage, to second capacitor charging
Or electric discharge；Second comparator is adapted to compare the second capacitance both end voltage and the reference voltage, is compared with output second
Voltage；Bi-stable latch, reverse phase and with phase latch point be suitable for latch first and second comparison voltage respectively；Also wrap
It includes：Self-excitation elimination circuit, suitable for carrying out logical operation to the first comparison voltage being latched to obtain the second control voltage,
And the second comparison voltage to being latched carries out logical operation to obtain the first control voltage.In the embodiment of the present invention, institute
It states self-excitation elimination circuit to have cut off to form self-oscillatory feedback network, is inherently eliminated clock production in the prior art
Self-oscillation in raw circuit.
Furthermore, the self-excitation elimination circuit may include：First NAND gate, first input end coupling are described anti-
Phase latch point, output end output the second control voltage；Second NAND gate, first input end coupling are described with mutually latch
Point, output end output the first control voltage；Second input terminal of first NAND gate and second NAND gate
Second input terminal accesses enable signal.Using the above scheme so that circuit structure of the embodiment of the present invention is simple, easy to implement.
Furthermore, the enable signal may include that the rising edge of logic high is changed to from logic low,
When the enable signal is logic low, the first control voltage and the second control voltage are logic high, are completed
Initialization to clock generation circuit of the embodiment of the present invention, when the enable signal becomes logic high, first control
The level logic of voltage processed and the second control voltage depends on the latch result of the bi-stable latch.Using the above scheme,
The reliability of circuit can be enhanced.
Furthermore, the electronic system of the embodiment of the present invention may include the clock generation circuit and by described
Clock generation circuit provides the operating circuit of clock signal, wherein the second input terminal of first NAND gate and described second
Second input terminal of NAND gate couples the power input of the operating circuit.When the operating circuit is powered on, electricity
The power supply signal of source input end includes the rising edge that logic high is changed to from logic low so that without making for described in
The additional control signal generating circuit of energy Design of Signal, it is easy to implement.
Description of the drawings
Fig. 1 is a kind of circuit diagram of relaxor in the prior art.
Fig. 2 is wave simulation figure of the relaxor shown in FIG. 1 in the clock signal for occurring to export when self-oscillation.
Fig. 3 is a kind of circuit diagram of clock generation circuit of the embodiment of the present invention.
Fig. 4 is the circuit diagram of another clock generation circuit of the embodiment of the present invention.
Fig. 5 is the circuit diagram of another clock generation circuit of the embodiment of the present invention.
Fig. 6 is the wave simulation figure of the clock signal of clock generation circuit output shown in fig. 5.
Specific implementation mode
As described in the background section, in the prior art, the clock generation circuit formed by relaxor there is
Potential feedback network can cause self-oscillation, and this cannot be inherently eliminated in existing solution from exciting
Swing phenomenon.
Present inventor is analyzed and has been emulated to clock generation circuit shown in FIG. 1.It is described with continued reference to Fig. 1
The output frequency of clock generation circuit 100 is determined by the first capacitance C1, the second capacitance C2, charging current Ir and reference voltage Vr
It is fixed.The NMOS tube M1, NMOS tube M2, PMOS tube M3 and PMOS tube M4 are switching tube, the NMOS tube M1 and PMOS tube M3 shapes
It (is not indicated in figure) at phase inverter, the NMOS tube M2 and PMOS tube M4 also form phase inverter (not indicated in figure).Described first
For capacitance C1 and the second capacitance C2 alternately from charge and discharge 0V to the reference voltage Vr, the size of current of charge and discharge is equal to institute
State charging current Ir, the frequency of clock signal caused by the clock generation circuit 100 is equal to Ir/Vr/C/2, wherein described
The capacitance of first capacitance C1 and the second capacitance C2 are equal, are expressed as C.
There are a potential feedback networks in the clock generation circuit 100：The drain electrode of PMOS tube M3 is passed through successively
First comparator Cpa, phase inverter Naa, the NMOS tube M1 and PMOS tube M3 form phase inverter, return the first comparator
Cpa；Similarly, there is also the feedback networks that one includes the second comparator Cpb.To include the feedback of the first comparator Cpa
For access, when the response speed of the first comparator Cpa is faster than the bi-stable latch 101, the bistable state lock
Storage 101 does not work in bistable state also, and is operate on intermediate amplification state, the first control voltage sa and the second control voltage
The logic level of sb is abnormal, will influence the charging and discharging state of the first capacitance C1 and the second capacitance C2, at this point, the clock produces
Raw circuit 100 possibly can not form negative-feedback and form positive feedback, the output end of the clock generation circuit 100 just will appear by
The free-run oscillation signal that the feedback network is determined, frequency are only determined by the device delay in the feedback network.
In the prior art, more conventional solution is the gain by reducing comparator or bandwidth, namely drop
The gain bandwidth product of low comparator, or time delay device is directly coupled after comparator, reduce comparator response speed to reach
The purpose of degree, but such scheme is affected to circuit.First, in normal work, comparator responded slow introduced
Circuit delay will be included in the clock signal of final output, clock signal be high frequency clock when, the circuit delay pair
The influence of the clock signal is very big；Secondly, above-mentioned solution does not completely eliminate this self-oscillation phenomenon, only will
Its odds reduces.
It specifically, can together referring to Fig. 1 and Fig. 2, wherein when the gain band of the first comparator and the second comparator
When width product is larger, there is a situation where self-oscillations for clock generation circuit 100 shown in FIG. 1.Fig. 2 includes time shaft having the same
Upper and lower two parts.When self-oscillation occurs, the first control voltage sa and the second control voltage sb can not generate waveform
Normal clock signal, but produce the high-frequency oscillation signal that frequency is about 1GHz；Meanwhile from described the of Fig. 2 lower parts
The voltage va at one both ends capacitance C1 and the voltage vb at the second both ends capacitance C2 are it can be found that the first capacitance C1 and the second capacitance
C2 can not also carry out normal periodical charge and discharge, and the clock generation circuit 100 can not work normally.The clock generates electricity
Self-oscillation situation in road 100 must be inherently eliminated.
For techniques discussed above problem, the embodiment of the present invention proposes a kind of clock generation circuit, by the way that self-excitation is arranged
Circuit is eliminated, the feedback network that fundamentally cut-out self-oscillation is relied on, and then it is inherently eliminated oneself of clock generation circuit
Induced Oscillation.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
As shown in figure 3, Fig. 3 shows a kind of clock generation circuit 200 of the embodiment of the present invention.The clock generation circuit
200 may include the first charge-discharge circuit 201, the first capacitance C1, first comparator Cpa, the second charge-discharge circuit 202, second
Capacitance C2, the second comparator Cpb, bi-stable latch 203 and self-excitation elimination circuit 204.
Furthermore, the control terminal of first charge-discharge circuit 201 receives the first control voltage sa；First electricity
The output end for holding C1 and first charge-discharge circuit 201 couples, in response to the different logic electricity of the first control voltage sa
Flat, first charge-discharge circuit 201 is to the first capacitance C1 charge or discharges；The first comparator Cpa be suitable for than
The voltage va and reference voltage Vr at the both ends the first capacitance C1, to export the first comparison voltage (not indicated in figure)；It is described
The control terminal of second charge-discharge circuit 202 receives the second control voltage sb；The second capacitance C2 and second charge and discharge electricity
The output end on road 202 couples, in response to the different logic levels of the second control voltage sb, second charge-discharge circuit
202 pairs of the second capacitance C2 charge or discharges；The second comparator Cpb is adapted to compare the both ends the second capacitance C2
The voltage vb and reference voltage Vr, to export the second comparison voltage (not indicated in figure)；The bi-stable latch 203 has
With phase latch point and reverse phase latch point (not indicated in figure), the reverse phase latch point is suitable for latching first comparison voltage, institute
Same phase latch point is stated to be suitable for latching second comparison voltage.
The self-excitation elimination circuit 204 is coupled with the same phase latch point and reverse phase latch point, suitable for the institute to being latched
It states the first comparison voltage and carries out logical operation, to obtain the second control voltage sb, and second ratio to being latched
Logical operation is carried out compared with voltage, to obtain the first control voltage sa.
Since the second control voltage sb is that the first comparison voltage progress logical operation being latched according to obtains
, the first control voltage sa is that the second comparison voltage progress logical operation being latched according to obtains, this " to hand over
Mutually " the mode controlled, it is cut-off to form self-oscillatory feedback network, it is inherently eliminated clock production in the prior art
Self-oscillation in raw circuit.
In specific implementation, the self-excitation elimination circuit 204 includes the first phase inverter Ia and the second phase inverter Ib.
Wherein, the input terminal of the first phase inverter Ia couples the reverse phase latch point, and the first phase inverter Ia's is defeated
Outlet output the second control voltage sb；The input terminal of the second phase inverter Ib couples the same phase latch point, and described the
Output end output the first control voltage sa of two phase inverter Ib.
The second control voltage sb is that the first comparison voltage for being latched according to carries out reverse phase and obtains, described the
One control voltage sa is that the second comparison voltage progress reverse phase being latched according to obtains, and can meet the clock production
It is cut-off self-oscillatory anti-to be formed by way of " interaction " control on the basis of control program in raw circuit 200
Feedthrough road.
It should be noted that the self-excitation elimination circuit 204 is only to include the first phase inverter Ia and the second phase inverter Ib is
Example, but be not limited thereto.The self-excitation elimination circuit 204 can also include other logical unit, as long as can meet
Control program in the clock generation circuit 200.
For example, reference can be made to another clock generation circuit 300 of the embodiment of the present invention shown in Fig. 4.Electricity is generated in clock
In road 300, self-excitation elimination circuit 205 may include：First NAND gate Na and the second NAND gate Nb.
Wherein, the first input end of the first NAND gate Na couples the reverse phase latch point, the first NAND gate Na
Output end output the second control voltage sb；The first input end coupling of the second NAND gate Nb is described with mutually latch
Point, output end output the first control voltage sa of the second NAND gate Nb；The second input of the first NAND gate Na
The second input terminal of end and the second NAND gate Nb access enable signal EN.
The clock generation circuit 300 of the embodiment of the present invention is not intended to limit carries out special limit to the form of the enable signal EN
System, as long as the control program in the clock generation circuit 300 can be met.For example, the enable signal EN can be
The voltage signal of logic high.
Furthermore, the enable signal EN may include the rising that logic high is changed to from logic low
Edge.When the enable signal EN is logic low, by the effect of the first NAND gate Na and the second NAND gate Nb, institute
It is logic high to state the control voltages of the first control voltage sa and second sb, can be completed to clock generation circuit of the embodiment of the present invention
300 initialization, for example, can be zero by the voltage initialization of the first capacitance C1 and the second both ends capacitance C2；When described
When enable signal EN becomes logic high, the level logic of the first control voltage sa and the second control voltage sb depend on
The latch result of the bi-stable latch 203.Using the above scheme, the reliability of circuit can be enhanced.
Another clock generation circuit 400 of the embodiment of the present invention is shown referring to Fig. 4 and Fig. 5, Fig. 5 together.
In the clock generation circuit 400, the first charge-discharge circuit 201 shown in Fig. 4 may include shown in fig. 5
One switch M3 and second switch M1.
Wherein, the control terminal of the first switch M3 receives the of the first control voltage sa, the first switch M3
One end receives reference current Ir, and the second end of the first switch M3 couples the output end of first charge-discharge circuit 201, institute
It states first switch M3 to be connected when the first control voltage sa is the first logic level, for example, first logic level can
To be logic low, but not limited to this.
The control terminal of the second switch M1 receives the first control voltage sa, the first end coupling of the second switch M1
The output end of first charge-discharge circuit 201 is connect, the second switch M1 is in the first control voltage sa for different from institute
It is connected when the second logic level for stating the first logic level.For example, second logic level can be logic high, but not
It is limited to this.Wherein, the second end of the second switch M1 can be grounded, and can also couple other voltage reference points, herein not into
Row is specifically limited.
Furthermore, second charge-discharge circuit 202 may include：Third switch M4 and the 4th switch M2.
Wherein, the control terminal of the third switch M4 receives the of the second control voltage sb, the third switch M4
One end receives the reference current Ir, and the second end of the third switch M4 couples the output of second charge-discharge circuit 202
End, the third switch M4 are connected when the second control voltage sb is first logic level namely logic low.
The control terminal of the 4th switch M2 receives the second control voltage sb, the first end coupling of the 4th switch M2
The output end of second charge-discharge circuit 202 is connect, the 4th switch M2 is described second in the second control voltage sb
It is connected when logic level namely logic high.Wherein, the second end of the 4th switch M2 can be grounded, and can also be coupled
Other voltage reference points, herein without specifically limited.
It should be noted that the embodiment of the present invention is only shown in Fig. 5 with the first switch M3 and third switch M4
For PMOS tube, the second switch M1 and the 4th switch M2 is NMOS tubes shown in Fig. 5, but not limited to this.Described first
It can be the semiconductor switch devices such as metal-oxide-semiconductor or triode to the 4th switch, can also be conventional switch element or be packaged in
The integrated switch of chip.
In embodiments of the present invention, the clock generation circuit 400 can also include：Current source 206 is adapted to provide for described
Reference current Ir.For example, the current source 206 may include current mirroring circuit, but not limited to this, it is any to generate the ginseng
The circuit or integrated formula device for examining electric current Ir can be used as the current source 206.
Furthermore, the clock generation circuit 400 can also include：Voltage source 207 is adapted to provide for described with reference to electricity
Press Vr.The voltage source 207 can be band gap reference (Bandgap), but not limited to this, it is any to generate the reference electricity
The circuit or integrated formula device for pressing Vr can be used as the current source 206.
Below will be with continued reference to Fig. 5, the course of work of clock generation circuit 400 described in brief analysis.Used below 0 indicates logic
Low level, and indicate logic high using 1.
When the second control voltage sb that the output end of the first NAND gate Na exports is 0, second NAND gate
When the first control voltage sa of the output end output of Nb is 1, the first switch M3 shutdowns, the second switch M1 is led
Logical, the first capacitance C1 is discharged, the third switch M4 conductings, the 4th switch M2 shutdowns, the second capacitance C2
It is electrically charged, when the voltage vb at the both ends the second capacitance C2 is charged to more than the reference voltage Vr, described second compares
Second comparison voltage of device Cpb outputs is 0 by 1 overturning, and the latch mode of the same phase latch point is 1, second NAND gate
The first control voltage sa of Nb outputs becomes 0；Similarly, at this point, since the voltage va at the both ends the first capacitance C1 is less than
The first comparison voltage of the reference voltage Vr, the first comparator Cpa outputs are maintained 1, the lock of the reverse phase latch point
It is 0 to deposit state, and the second control voltage sb of the first NAND gate Na outputs is 1.In turn, the first switch M3 is led
Logical, the second switch M1 shutdowns, the first capacitance C1 is electrically charged, the third switch M4 shutdowns, the 4th switch M2
Conducting, the second capacitance C2 are discharged, when the voltage va at the both ends the first capacitance C1 is charged to more than described with reference to electricity
When pressing Vr, it is 0 that the first comparison voltage of the first comparator Cpa outputs is overturn by 1, the latch mode of the reverse phase latch point
It is 1, the second control voltage sb of the first NAND gate Na outputs becomes 0；Similarly, at this point, due to second capacitance
The voltage vb at the both ends C2 is less than the reference voltage Vr, and the second comparison voltage of the second comparator Cpb outputs is maintained 1,
The latch mode of the same phase latch point is 0, and the first control voltage sa of the second NAND gate Nb outputs is 1, cycle
Back and forth.
The first control voltage sa and the second control that the first NAND gate Na and the second NAND gate Nb is respectively exported
Output ends of the voltage sb processed as the clock forming circuit 400 will generate the clock signal of two-way opposite in phase.
The simulation waveform of the clock signal of above-mentioned two-way opposite in phase can be on the basis of Fig. 5 with further reference to Fig. 6.With Fig. 2
It compares, in the case where keeping the gain bandwidth product of first comparator Cpa and the second comparator Cpb constant, the embodiment of the present invention
The clock generation circuit 400 produce the normal clock signal of waveform namely first control voltage sa (dotted line institutes
Show) and the second control voltage sb (shown in solid), the peak-to-peak value of the two is about 1.2V, and frequency is about 60MHz.Simultaneously as tool
Have an identical time shaft, Fig. 6 also show the voltage va at the both ends the first capacitance C1 and the voltage at the second both ends capacitance C2 and
Vb, clearly illustrates the charge and discharge process of the first capacitance C1 and the second capacitance C2 from 0V to 300mV in figure, frequency with
The frequency of the first control voltage sa or the second control voltage sb are identical, also about 60MHz.
With continued reference to Fig. 4 or Fig. 5, the embodiment of the invention also discloses a kind of electronic system, the electronic system can wrap
The clock generation circuit 300 or 400 is included, and accordingly, clock signal is provided by the clock generation circuit 300 or 400
Operating circuit (not shown), wherein the second of the second input terminal of the first NAND gate Na and the second NAND gate Nb
Input terminal couples the power input of the operating circuit.
When the operating circuit does not power on, the voltage of power input is zero, when the operating circuit is powered on,
Its power input receives the power supply signal that external power supply applies so that the enable signal EN includes changing from logic low
It is easy to the rising edge of logic high into without designing additional control signal generating circuit for the enable signal EN
Implement.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of clock generation circuit, the clock generation circuit include：
First charge-discharge circuit, control terminal receive the first control voltage；
First capacitance is coupled with the output end of first charge-discharge circuit, and in response to first control, voltage is different patrols
Level is collected, first charge-discharge circuit is to first capacitor charging or electric discharge；
First comparator is adapted to compare the voltage and reference voltage at first capacitance both ends, to export the first comparison voltage；
Second charge-discharge circuit, control terminal receive the second control voltage；
Second capacitance is coupled with the output end of second charge-discharge circuit, and in response to second control, voltage is different patrols
Level is collected, second charge-discharge circuit is to second capacitor charging or electric discharge；
Second comparator is adapted to compare the voltage at second capacitance both ends and the reference voltage, electric to export the second comparison
Pressure；
Bi-stable latch has with phase latch point and reverse phase latch point, and the reverse phase latch point is suitable for latching first ratio
Compared with voltage, the same phase latch point is suitable for latching second comparison voltage；
It is characterized in that, further including：
Self-excitation elimination circuit is coupled with the same phase latch point and reverse phase latch point, suitable for comparing be latched described first
Voltage carries out logical operation, to obtain the second control voltage, and patrols second comparison voltage being latched
Operation is collected, to obtain the first control voltage.
2. clock generation circuit according to claim 1, which is characterized in that the self-excitation elimination circuit includes：
First NAND gate, first input end couple the reverse phase latch point, output end output the second control voltage；
Second NAND gate, first input end couple the same phase latch point, output end output the first control voltage；
Second input terminal of first NAND gate and the second input terminal of second NAND gate access enable signal.
3. clock generation circuit according to claim 2, which is characterized in that the enable signal includes from logic low
It is changed to the rising edge of logic high.
4. clock generation circuit according to claim 1, which is characterized in that the self-excitation elimination circuit includes：
First phase inverter, input terminal couple the reverse phase latch point, output end output the second control voltage；
Second phase inverter, input terminal couple the same phase latch point, output end output the first control voltage.
5. clock generation circuit according to any one of claims 1 to 4, which is characterized in that first charge-discharge circuit
Including：
First switch, control terminal receive the first control voltage, and first end receives reference current, and second end couples institute
The output end of the first charge-discharge circuit is stated, the first switch is connected when the first control voltage is the first logic level；
Second switch, control terminal receive the first control voltage, and first end couples the defeated of first charge-discharge circuit
Outlet, the second switch are led when the first control voltage is the second logic level different from first logic level
It is logical.
6. clock generation circuit according to claim 5, which is characterized in that second charge-discharge circuit includes：
Third switchs, and control terminal receives the second control voltage, and first end receives the reference current, second end coupling
The output end of second charge-discharge circuit is connect, the third switch is first logic level in the second control voltage
When be connected；
4th switch, control terminal receive the second control voltage, and first end couples the defeated of second charge-discharge circuit
Outlet, the 4th switch are connected when the second control voltage is second logic level.
7. clock generation circuit according to claim 5, which is characterized in that further include：Current source is adapted to provide for the ginseng
Examine electric current.
8. clock generation circuit according to any one of claims 1 to 4, which is characterized in that further include：Voltage source is suitable for
The reference voltage is provided.
9. a kind of electronic system, including clock generation circuit according to claim 2 or 3 and carried by the clock generation circuit
For the operating circuit of clock signal, wherein the second of the second input terminal of first NAND gate and second NAND gate is defeated
Enter the power input that end couples the operating circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710131316.8A CN108574476A (en) | 2017-03-07 | 2017-03-07 | Clock generation circuit and electronic system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710131316.8A CN108574476A (en) | 2017-03-07 | 2017-03-07 | Clock generation circuit and electronic system |
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| CN109474260A (en) * | 2019-01-11 | 2019-03-15 | 成都信息工程大学 | A kind of adjustable oscillator of number |
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