CN108574457A - A kind of signal processing system and its method - Google Patents
A kind of signal processing system and its method Download PDFInfo
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- CN108574457A CN108574457A CN201710149141.3A CN201710149141A CN108574457A CN 108574457 A CN108574457 A CN 108574457A CN 201710149141 A CN201710149141 A CN 201710149141A CN 108574457 A CN108574457 A CN 108574457A
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- 238000012545 processing Methods 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000015654 memory Effects 0.000 claims abstract description 40
- 230000008569 process Effects 0.000 claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 230000008030 elimination Effects 0.000 claims abstract description 13
- 238000003379 elimination reaction Methods 0.000 claims abstract description 13
- 230000009471 action Effects 0.000 claims description 23
- 238000003672 processing method Methods 0.000 claims description 18
- 210000001367 artery Anatomy 0.000 claims description 7
- 210000003462 vein Anatomy 0.000 claims description 7
- 238000009529 body temperature measurement Methods 0.000 claims description 5
- 238000004088 simulation Methods 0.000 claims description 4
- 238000012937 correction Methods 0.000 description 7
- 239000010453 quartz Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000036413 temperature sense Effects 0.000 description 2
- 206010044565 Tremor Diseases 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
A kind of signal processing system and its method, in environment applied to inductance capacitance resonant cavity alternator resonant frequency OSC temperature-compensatings processing, via temperature-sensitive sticker/analog-digital converter obtain from the relevant different K values of different temperature, and K values are recorded in temperature-compensating processing module single write-in read-only memory OTP ROM；Capacitor and inductor resonant cavity oscillator LC Tank can be exported higher resonant frequency OSC frequency eliminations down by fractional N-type frequency eliminator；It is shaken using linear phase-locked loop LPLL to constrain the clock pulse of the exported clock pulse of fractional N-type frequency eliminator, Frequency-locked-loop FLL according to after linear phase-locked loop LPLL clock pulse dithering process clock pulse and the external frequency for applying an outside clock signal, and it finds out M values needed for fractional N-type frequency eliminator and N values and is sent to temperature-compensating processing module, and K values, M values and N values can be sent to fractional N-type frequency eliminator by temperature-compensating processing module, so that fractional N-type frequency eliminator can export accurately clock signal.
Description
Technical field
The present invention relates to signal processing system and methods, in more detail, are related to a kind of applied to inductance capacitance resonant cavity
(LC-Tank) signal processing system and method for the environment of the temperature-compensating processing of alternator resonant frequency OSC, utilizes temperature sense
Survey device/analog-digital converter, temperature-compensating processing module, fractional N-type frequency eliminator, linear phase-locked loop LPLL, Frequency-locked-loop
FLL, and the K values needed for fractional N-type frequency eliminator, M values and N are found out, so that fractional N-type frequency eliminator can export accurately clock pulse letter
Number.
Background technology
In the development of electronic product, due to the quick evolution of manufacture of semiconductor technology, occur powerful, complicated
Super large-scale integration, some electronic goods, for example, mobile phone, tablet computer, USB peripheral products all need single-chip
Using, and in complicated super large-scale integration, with greater need for accurate synchronous clock signal to realize the processing of high standard
Efficiency is event, and clock pulse generator, i.e. phase-locked loop PLL are widely used in frequency synthesizer and clock pulse data recovery device
Deng.
For current non-quartz oscillator, the structure of the more normal See of voltage controlled oscillator VCO can be divided into Two kinds, a kind of
Inductance capacitance resonant cavity (LC-Tank) oscillator, it is another then be Ring oscillators, and with CMOS processing procedures for, Ring shakes
The phase noise for swinging device is still unable to reach the requirement of related communication voltage controlled oscillator VCO specification at present, thus often with inductance capacitance
Resonant cavity (LC-Tank) oscillator Come designs voltage controlled oscillator VCO.
In high speed input/output I/O interfaces and wireless communication system, when needing inexpensive, dynamical
Pulse generator can reduce phase noise using inductance capacitance resonant cavity oscillator and reach the effect for the communicating requirement for meeting high-quality
It can specification.
In non-patent literature " A monolithic and self-referenced RF LC clock generator
Compliant with USB 2.0 ", Article in IEEE Journal of Solid-State Circuits,
March2007, author Michael S McCorquodale disclosed is, how to solve because environment variation (such as temperature
Degree) caused by quartz oscillator (XTAL) frequency variation caused by phase-locked loop PLL lock out frequency variation the problem of；
And used mode is, adds difference circuit (phase in a phase before feeding back frequency eliminating circuit using phase-locked loop PLL
Interpolation), whereby at different temperature, the mode of phase (shift phase) is jumped to reach adjustment phase-locked loop
PLL output frequencies.
Taiwan discloses/notification number I558095 " clock generating circuit and method " be disclose a kind of clock generating circuit and when
Arteries and veins production method, for generating a clock pulse.Clock generating circuit includes：One refers to clock generating circuit, is set in a chip,
Clock pulse is referred to for independently generating one；One temperature-sensitive sticker, for sense ambient temperature to generate a temperature information；One temperature
Compensating module couples the temperature-sensitive sticker, is used for generating a temperature compensation coefficient according to the temperature information；And one clock pulse adjustment
Circuit couples this and refers to clock generating circuit, for generating the clock pulse with reference to clock pulse and the temperature compensation coefficient according to this；Its
In, temperature compensation module dynamic generates the temperature compensation coefficient, so that one target frequency of frequency approach of the clock pulse, and essence
On do not vary with temperature.And Taiwan disclose/temperature compensation module of notification number I558095 " clock generating circuit and method " according to
The temperature compensation coefficient corresponding to each temperature is generated according to a reference value and slope, is acquired when a certain temperature using interpolation method
Setting value N.F, push away temperature compensation coefficient so as to counter.
Taiwan discloses/and notification number I485986 " method and apparatus of time pulse signal synthesis " is when disclosing a kind of adjustment output
Method in the frequency of arteries and veins signal to the accuracy of desired frequency of oscillation and its device.Under one embodiment of this method includes
Row step：Into a correction mode；One first control character is generated, to control the sequential of a clock pulse signal synthesizer；Adjustment should
First control character is substantially fallen into until the sequential of the synthesizer in a preset range with reference to clock pulse sequential；Utilize a temperature
It spends sensor and senses a temperature；The output preset value of first control character is stored to a nonvolatile memory；Leave the school
Holotype；The temperature is sensed using the sensor；And exporting and the temperature-sensitive sticker according to the nonvolatile memory
Output generates one second control character, to control the sequential of the clock signal synthesizer.And Taiwan discloses/notification number I485986
" method and apparatus of time pulse signal synthesis " is to utilize single point correction and temperature under processing procedure, voltage, the influence of change with temperature
Compensation mechanism maintains in the accuracy range that the frequency of clock signal requires to assigned frequency.
Taiwan discloses/notification number 201543803 " clock generating circuit and method " be disclose a kind of clock generating circuit with
Clock pulse generation methods, for generating a clock pulse.Clock generating circuit includes：One refers to clock generating circuit, is set to a chip
In, it is used for independently generating one with reference to clock pulse；One temperature-sensitive sticker, for sense ambient temperature to generate a temperature information；One
Temperature compensation module couples the temperature-sensitive sticker, is used for generating a temperature compensation coefficient according to the temperature information；An and clock pulse
Adjustment circuit couples this and refers to clock generating circuit, for generating the clock pulse with reference to clock pulse and the temperature compensation coefficient according to this；
Wherein, temperature compensation module dynamic generates the temperature compensation coefficient, so that one target frequency of frequency approach of the clock pulse, and it is real
It is not varied with temperature in matter.And Taiwan discloses the/temperature-compensating mould of notification number 201543803 " clock generating circuit and method "
Block benchmark value and slope generate the temperature compensation coefficient corresponding to each temperature, are acquired in a certain temperature using interpolation method
Setting value N.F when spending pushes away temperature compensation coefficient so as to counter.
So quartz oscillator (XTAL) how need not be utilized, without using difference circuit in phase and without profit
With single point correction, in addition, being not the phase of voltage controlled oscillator VCO in adjustment analog pll circuit, but digital servo-control can be utilized
Circuit is looked for except the relationship of frequency and temperature and phase and adjustment phase place, is problem to be solved.
Invention content
The main object of the present invention is to be to provide a kind of signal processing system and its method, is to be applied to inductance capacitance
In the environment of the temperature-compensating processing of resonant cavity (LC-Tank) alternator resonant frequency OSC, via temperature-sensitive sticker/simulation number
Word converter obtain from the relevant different K values of different temperature, and K values are recorded in the mono-recordable of temperature-compensating processing module
Enter read-only memory OTP ROM；Fractional N-type frequency eliminator can be exported capacitor and inductor resonant cavity oscillator LC-Tank higher
Resonant frequency OSC frequency eliminations down；Using linear phase-locked loop LPLL come constrain clock pulse that fractional N-type frequency eliminator is exported when
Arteries and veins shakes, Frequency-locked-loop FLL according to after linear phase-locked loop LPLL clock pulse dithering process clock pulse and external applied
The frequency of one outside clock signal, and find out the M values needed for fractional N-type frequency eliminator and N values and be sent to temperature-compensating processing
Module, and K values, M values and N values can be sent to fractional N-type frequency eliminator by temperature-compensating processing module, so as to fractional N-type frequency eliminator
Accurately clock signal can be exported.
Another object of the present invention is to be to provide a kind of signal processing system and its method, is to be applied to inductance capacitance
In the environment of the temperature-compensating processing of resonant cavity (LC-Tank) alternator resonant frequency OSC, compensated without using loop temperature is opened
Circuit (open loop temperature compensation circuit) and binary-weighted capacitors array
(binary-weighted capacitor array), and smaller chip area can be used to realize self-correction inductance capacitance
Frequency drift of the clock pulse generator caused by temperature.
A further object of the present invention is to be to provide a kind of signal processing system and its method, is to be applied to inductance capacitance
In the environment of the temperature-compensating processing of resonant cavity (LC-Tank) alternator resonant frequency OSC, it can need not be vibrated using quartz crystal
Device (XTAL) using difference circuit in phase and need not need not utilize single point correction, and fractional N-type frequency eliminator can be enable to export essence
Accurate clock signal.
Another object of the present invention is to be to provide a kind of signal processing system and its method, is to be applied to inductance capacitance
It is not adjustment analog pll circuit in the environment of the temperature-compensating processing of resonant cavity (LC-Tank) alternator resonant frequency OSC
The phase of middle voltage controlled oscillator VCO, but can be looked for except the relationship of frequency and temperature and phase and be adjusted using digital phase locked loop
Whole phase, and fractional N-type frequency eliminator can be enable to export accurately clock signal.
A further object of the present invention is to be to provide a kind of signal processing system and its method, is to be applied to inductance capacitance
In the environment of the temperature-compensating processing of resonant cavity (LC-Tank) alternator resonant frequency OSC, the physics of temperature linearity variation is utilized
The case where amount changes with inductance capacitance resonance OSC frequencies with temperature linearity determines straight line with more than two points, and institute is right
It is the several years that the more than two temperature answered, which do not limit, and recycle fractional N-type (fractional N) frequency elimination and inductance electricity
Hold resonance OSC frequencies to remove into required output frequency, is more than two different temperature with not certain limit value in other words
It spends and corrects frequency elimination number, to make except frequency out to be required.
According to above-described purpose, the present invention provides a kind of signal processing system, which includes temperature
Sensor/analog-digital converter (temperature sensor/ADC), temperature-compensating processing module, fractional N-type frequency eliminator
(fractional-N divider), linear phase-locked loop LPLL (Linear Phase Locked Loop) and frequency locking return
Road FLL (Frequency Lock Loop)；Wherein, temperature-compensating processing module may include temperature-compensating processor and storage
Device.
Temperature-sensitive sticker/analog-digital converter, via the temperature-sensitive sticker/analog-digital converter, by the temperature
Sensor learns temperature instantly and changes into voltage, then by the analog-digital converter be converted into digital code (code) character come
The K values of fractional N-type frequency eliminator are controlled, and different temperature will obtain different K values.
Temperature-compensating processing module, the temperature-compensating processing module may include temperature-compensating processor and memory,
In, there is single write-in read-only memory OTP (One Time Programmable) ROM and look-up table in the memory
(Look Up Table)；The single is written read-only memory OTP (One Time Programmable) ROM and records different temperatures
More than two K values, to do two point calibrations and just record two K values, to do three point calibrations and just record three K values；The temperature is mended
More than two K values in single write-in read-only memory OTP ROM, the look-up table can be utilized and come from by repaying processor
The M values and N values of Frequency-locked-loop FLL and obtain frequency shift (FS) ratio discreet value, and the frequency shift (FS) ratio discreet value is sent to
Fractional N-type frequency eliminator, so that fractional N-type frequency eliminator can export accurately clock signal.
Fractional N-type frequency eliminator, which, which can receive, comes from capacitor and inductor resonant cavity oscillator and is exported
Higher resonant frequency OSC, for example, frame clock signal output FCO (Frame Clock Output), produces clock signal
Clock signal FOUT is simultaneously sent to linear phase-locked loop LPLL (Linear Phase Lock Loop) by FOUT.
In addition, the fractional N-type frequency eliminator, after receiving the frequency shift (FS) ratio discreet value, which can incite somebody to action
The higher resonant frequency OSC that capacitor and inductor resonant cavity oscillator (LC-Tank) is exported, for example, frame clock signal exports FCO
(Frame Clock Output) frequency elimination down, so that fractional N-type frequency eliminator can export accurately clock signal.
Linear phase-locked loop LPLL (Linear Phase Lock Loop), is exported by the fractional N-type frequency eliminator
The shake (jitter) of the clock pulse (clock) of clock signal FOUT is bigger, thus the clock pulse that the fractional N-type frequency eliminator is exported
The clock pulse of signal FOUT will constrain the clock signal FOUT that fractional N-type frequency eliminator is exported using the linear phase-locked loop LPLL
Clock pulse shake.
Frequency-locked-loop FLL (Frequency Lock Loop), which will be after clock pulse dithering process
The clock pulse of clock signal FOUT be sent to the Frequency-locked-loop FLL, Frequency-locked-loop FLL according to from the linear phase-locked loop LPLL
And the clock pulse of the clock signal FOUT after clock pulse dithering process come and outside are applied to its an outside clock signal
Frequency, for example, 24Mhz or 48Mhz, and find out the M values needed for the fractional N-type frequency eliminator with N values and transmit the M values and N values
To the temperature-compensating processing module, and the temperature-compensating processor of the temperature-compensating processing module can utilize single write-in read-only
More than two K values, look-up table in memory OTP ROM and M values and the N values from Frequency-locked-loop FLL and obtain frequency
Rate shift ratio discreet value, and send the frequency shift (FS) ratio discreet value to fractional N-type frequency eliminator, so as to fractional N-type frequency elimination
Device can export accurately clock signal.
Using the present invention process of the signal processing system to carry out signal processing method when, first, measured into trip temperature
Action；Via the temperature-sensitive sticker/analog-digital converter, temperature instantly is learnt by the temperature-sensitive sticker and changes into voltage,
The K values of fractional N-type frequency eliminator are controlled by what the analog-digital converter was converted into digital code (code) character again, without
Same temperature will obtain different K values；More than two K of read-only memory OTP ROM record different temperatures are written in the single
Value will do two point calibrations and just record two K values, do three point calibrations and just record three K values.
Then, frequency shift (FS) ratio discreet value calculating action is carried out；The temperature-compensating processor can utilize the single to be written
More than two K values, the look-up table in read-only memory OTP ROM and M values and the N values from Frequency-locked-loop FLL and obtain
Go out frequency shift (FS) ratio discreet value, and sends the frequency shift (FS) ratio discreet value to fractional N-type frequency eliminator.
Then, accurate clock pulse output action is carried out；Fractional N-type frequency eliminator is pre- according to the received frequency shift (FS) ratio
Valuation, the fractional N-type frequency eliminator can export accurately clock signal.
Wherein, more detailed program when progress frequency shift (FS) ratio discreet value calculating action is：First, clock signal is carried out
FOUT generating routines, the fractional N-type frequency eliminator can receive come from capacitor and inductor resonant cavity oscillator exported it is higher humorous
Vibration frequency OSC, for example, frame clock signal output FCO (Frame Clock Output), produces clock signal FOUT and incite somebody to action
Clock signal FOUT is sent to linear phase-locked loop LPLL (Linear Phase Lock Loop)；In turn, clock pulse is carried out to tremble
The shake of dynamic processing routine, the clock pulse of the clock signal FOUT exported by the fractional N-type frequency eliminator is bigger, thus this point
The clock pulse for the clock signal FOUT that number N-type frequency eliminator is exported will be removed using the linear phase-locked loop LPLL to constrain fractional N-type
The clock pulse for the clock signal FOUT that frequency device is exported is shaken；Followed by, which will be after clock pulse dithering process
The clock pulse of clock signal FOUT be sent to the Frequency-locked-loop FLL, Frequency-locked-loop FLL according to from the linear phase-locked loop LPLL
And the clock pulse of the clock signal FOUT after clock pulse dithering process come and outside are applied to its an outside clock signal
Frequency, for example, 24Mhz or 48Mhz, and find out the M values needed for the fractional N-type frequency eliminator with N values and transmit the M values and N values
To the temperature-compensating processing module；And carry out obtaining frequency shift (FS) ratio discreet value program, the temperature-compensating processing module
Temperature-compensating processor can utilize more than two K values in single write-in read-only memory OTP ROM, look-up table and
M values and N values from Frequency-locked-loop FLL and obtain frequency shift (FS) ratio discreet value, and by the frequency shift (FS) ratio discreet value
Send fractional N-type frequency eliminator to.
Understand the purpose of the present invention, feature and technique effect to make to be familiar with this those skilled in the art, hereby passes through following specific realities
Example is applied, and coordinates appended attached drawing, to elaborate of the present invention as after：
Description of the drawings
Fig. 1 is a system schematic, to show the system architecture and the cooperation that illustrate the signal processing system of the present invention
The operation situation of inductance capacitance resonant cavity (LC-Tank) oscillator；
Fig. 2 is a flow chart, to show explanation using the signal processing system of the present invention in such as Fig. 1 to carry out signal
The process step of processing method；
Fig. 3 is a flow chart, to show carry out frequency shift (FS) ratio of the explanation using the signal processing method in such as Fig. 2
The more detailed program of discreet value calculating action step；
Fig. 4 is a schematic diagram, to show framework, the Yi Jipei of the embodiment for illustrating the signal processing system of the present invention
Close the operation situation of inductance capacitance resonant cavity (LC-Tank) oscillator；
Fig. 5 is a flow chart, to show an embodiment of the explanation using the signal processing system such as the present invention in Fig. 4
To carry out a process step of signal processing method；And
Fig. 6 is a flow chart, to show carry out frequency shift (FS) ratio of the explanation using the signal processing method in such as Fig. 5
The more detailed program of discreet value calculating action step.
Reference sign：
2 capacitor and inductor resonant cavity oscillators
11 signal processing systems
21,22,23 step
31,32,33 step
111 temperature-sensitive stickers/analog-digital converter
112 temperature-compensating processing modules
113 fractional N-type frequency eliminators
114 Frequency-locked-loop FLL
115 linear phase-locked loop LPLL
221,222,223,224 step
321,322,323,324 step
1121 temperature-compensating processors
1122 memories
Read-only memory OTP ROM are written in 1123 singles
1124 look-up table LUT
1131 clock signals
1132 clock signals
Clock signal frequency outside External
FCO frame clock signals
FOUT clock signals
Specific implementation mode
Fig. 1 is a system schematic, to show the system architecture and the cooperation that illustrate the signal processing system of the present invention
The operation situation of inductance capacitance resonant cavity (LC-Tank) oscillator.As shown in fig. 1, signal processing system 11 includes temperature sense
Survey device/analog-digital converter 111, temperature-compensating processing module 112, fractional N-type frequency eliminator 113, Frequency-locked-loop FLL 114,
And linear phase-locked loop LPLL 115；Wherein, temperature-compensating processing module 112 may include that temperature-compensating processor (is not schemed
Show) and memory (not shown).
Temperature-sensitive sticker/analog-digital converter 111, via the temperature-sensitive sticker/analog-digital converter 111, by
The temperature-sensitive sticker learns temperature instantly and changes into voltage, then is converted into digital code (code) by the analog-digital converter
Character controls the K values of fractional N-type frequency eliminator 113, and different temperature will obtain different K values.
Temperature-compensating processing module 112, the temperature-compensating processing module 112 may include temperature-compensating processor, Yi Jicun
Reservoir, wherein in the memory have single write-in read-only memory OTP (One Time Programmable) ROM and
Look-up table (Look Up Table)；Read-only memory OTP (One Time Programmable) ROM records are written not in the single
Synthermal more than two K values will do two point calibrations and just record two K values, do three point calibrations and just record three K values；It should
Temperature-compensating processor can utilize more than two K values in single write-in read-only memory OTP ROM, the look-up table, with
And M values and N values from Frequency-locked-loop FLL 114 and obtain frequency shift (FS) ratio discreet value, and it is the frequency shift (FS) ratio is pre-
Valuation sends fractional N-type frequency eliminator 113 to, so that fractional N-type frequency eliminator 113 can export accurately clock signal.
Fractional N-type frequency eliminator 113, which, which can receive, comes from capacitor and inductor resonant cavity oscillator 2
The higher resonant frequency OSC exported, for example, frame clock signal output FCO (Frame Clock Output), when producing
Clock signal FOUT is simultaneously sent to linear phase-locked loop LPLL 114 by arteries and veins signal FOUT.
In addition, the fractional N-type frequency eliminator 113 is after receiving the frequency shift (FS) ratio discreet value, the fractional N-type frequency eliminator
The 113 higher resonant frequency OSC that capacitor and inductor resonant cavity oscillator 2 can be exported, for example, frame clock signal exports FCO
(Frame Clock Output) is removed down, so that fractional N-type frequency eliminator can export accurately clock signal.
Linear phase-locked loop LPLL 115, by the clock pulse for the clock signal FOUT that the fractional N-type frequency eliminator 113 is exported
(clock) shake (jitter) is bigger, thus the clock pulse of clock signal FOUT that the fractional N-type frequency eliminator 113 is exported
The clock pulse that the clock signal FOUT that fractional N-type frequency eliminator 113 is exported will be constrained using the linear phase-locked loop LPLL 115
Shake.
Frequency-locked-loop FLL 114, the linear phase-locked loop LPLL 115 are by the clock signal after clock pulse dithering process
The clock pulse of FOUT is sent to Frequency-locked-loop FLL 114, and Frequency-locked-loop FLL 114 is according to from the linear phase-locked loop LPLL
115 and the clock pulse of the clock signal FOUT after clock pulse dithering process and the external outside clock pulse letter for being applied to it that come
Number external frequencies, for example, 24Mhz or 48Mhz, and find out the M values needed for the fractional N-type frequency eliminator 113 with N values, simultaneously
The M values and N values are sent to the temperature-compensating processing module 112, and the temperature-compensating of the temperature-compensating processing module 112 is handled
Device can utilize the single more than two K values in read-only memory OTP ROM, look-up table to be written and from the frequency locking time
The M values and N values of road FLL 115 and obtain frequency shift (FS) ratio discreet value ((not shown)), and the frequency shift (FS) ratio is estimated
Value sends fractional N-type frequency eliminator 113 to, so that fractional N-type frequency eliminator 113 can export accurately clock signal 1131.
Fig. 2 is a flow chart, to show explanation using the signal processing system of the present invention in such as Fig. 1 to carry out signal
The process step of processing method.
As shown in Figure 2, first, it in step 21, is acted into trip temperature measurement；Via the temperature-sensitive sticker/simulation
Digital quantizer 111 learns temperature instantly by the temperature-sensitive sticker and changes into voltage, then is turned by the analog-digital converter
It changes into and controls the K values of fractional N-type frequency eliminator 113 for digital code (code) character, and different temperature will obtain different K
Value；More than two K values of read-only memory OTP ROM record different temperatures are written in the single, to do two point calibrations and just record
Two K values will do three point calibrations and just record three K values, and enter step 22.
In step 22, frequency shift (FS) ratio discreet value calculating action is carried out；The temperature-compensating processor can utilize the single
More than two K values, the look-up table and the M values from Frequency-locked-loop FLL 114 in read-only memory OTP ROM is written
Frequency shift (FS) ratio discreet value is obtained with N values, and sends the frequency shift (FS) ratio discreet value to fractional N-type frequency eliminator 113,
And enter step 23.
In step 23, accurate clock pulse output action is carried out；Fractional N-type frequency eliminator 113 is inclined according to the received frequency
Shifting ratio discreet value, the fractional N-type frequency eliminator 113 can export accurately clock signal 1131.
Fig. 3 is a flow chart, to show carry out frequency shift (FS) ratio of the explanation using the signal processing method in such as Fig. 2
The more detailed program of discreet value calculating action step.As shown in Figure 3, first, clock signal FOUT generating routines are carried out
221；The fractional N-type frequency eliminator 113, which can receive, comes from the higher resonant frequency that capacitor and inductor resonant cavity oscillator 2 is exported
OSC, for example, frame clock signal output FCO (Frame Clock Output), produces clock signal FOUT and by the clock pulse
Signal FOUT is sent to linear phase-locked loop LPLL 115, and enters program 222.
In program 222, clock pulse dithering process program is carried out；The clock signal exported by the fractional N-type frequency eliminator 113
The shake of the clock pulse of FOUT is bigger, thus the clock pulse of clock signal FOUT that the fractional N-type frequency eliminator 113 is exported will utilize
The linear phase-locked loop LPLL 115 shakes come the clock pulse for constraining the clock signal FOUT that fractional N-type frequency eliminator 113 is exported, and
Enter program 223.
In program 223, carry out finding out M values and N value programs；The linear phase-locked loop LPLL 115 will be through clock pulse dithering process
The clock pulse of clock signal FOUT afterwards is sent to Frequency-locked-loop FLL 114, and Frequency-locked-loop FLL 114 is according to from the linear lock
Phase circuit LPLL 115 and the clock pulse of the clock signal FOUT after clock pulse dithering process that comes and external it is applied to its one
The external frequencies of external clock signal, for example, 24Mhz or 48Mhz, and find out the M needed for the fractional N-type frequency eliminator 113
Value is sent to the temperature-compensating processing module 112 with N values and by the M values and N values, and enters program 224.
In program 224, carry out obtaining frequency shift (FS) ratio discreet value program；The temperature of the temperature-compensating processing module 112
Compensation processor can utilize more than two K values in single write-in read-only memory OTP ROM, look-up table and come from
The M values and N values of Frequency-locked-loop FLL 115 and obtain frequency shift (FS) ratio discreet value, and by the frequency shift (FS) ratio discreet value
Send fractional N-type frequency eliminator 113 to.
Fig. 4 is a schematic diagram, to show framework, the Yi Jipei of the embodiment for illustrating the signal processing system of the present invention
Close the operation situation of inductance capacitance resonant cavity (LC-Tank) oscillator.As shown in Figure 4, signal processing system 11 includes temperature
Spend sensor/analog-digital converter 111, temperature-compensating processing module 112, fractional N-type frequency eliminator 113, linear phase-locked loop
LPLL 115 and Frequency-locked-loop FLL 114；Wherein, temperature-compensating processing module 112 may include temperature-compensating processor
1121 and memory 1122；And, wherein when 2 frequency of inductance capacitance resonant cavity (LC-Tank) oscillator is that straight line will be into
Two point calibration of row, when 2 frequency of inductance capacitance resonant cavity (LC-Tank) oscillator be conic section the present carry out three point calibrations, work as electricity
It is that P curve then carries out (P+1) point calibration that electrification, which holds 2 frequency of resonant cavity (LC-Tank) oscillator,.
Temperature-sensitive sticker/analog-digital converter 111, via the temperature-sensitive sticker/analog-digital converter 111, by
The temperature-sensitive sticker learns temperature instantly and changes into voltage, then is converted into digital code (code) by the analog-digital converter
Character controls the K values of fractional N-type frequency eliminator 113, and different temperature will obtain different K values；Such as, wherein respectively at 0
DEG C/25 DEG C/50 DEG C when, for example, when 0 DEG C, digital code character：Vbe_0=>ADC_Code_0, FLL=>K0；And in 50 °C
When, digital code character：Vbe_50=>ADC_Code_50, FLL=>K50；And when 25 DEG C, digital code character：Vbe_25=>
ADC_Code_25, FLL=>K25；It is event, so when temperature is X DEG C, digital code character：Vbe_x=>ADC_Code_X=>
Kx is input to fractional N-type frequency eliminator 113 by Kx (required K values) using look-up table (LUT), here, the temperature write is not
It is absolute, if taking a K value, high temperature to take a K value as long as doing two point correction room temperature.
Temperature-compensating processing module 112, the temperature-compensating processing module 112 may include temperature-compensating processor 1121, with
And memory 1122, wherein there is single write-in read-only memory OTP (One Time in the memory 1122
Programmable) ROM 1123 and look-up table LUT (Look Up Table) 1124；Read-only memory is written in the single
OTP (One Time Programmable) ROM1123 records more than two K values of different temperatures, to do two point calibrations and just remember
Two K values of record will do three point calibrations and just record three K values；It is read-only that the temperature-compensating processor 1121 can utilize the single to be written
More than two K values, look-up table LUT 1124 in memory OTP ROM1123 and from Frequency-locked-loop FLL's 115
M values and N values and obtain frequency shift (FS) ratio discreet value, and send the frequency shift (FS) ratio discreet value to fractional N-type frequency eliminator
113, so that fractional N-type frequency eliminator 113 can export accurately clock signal 1132.
Fractional N-type frequency eliminator 113, which, which can receive, comes from capacitor and inductor resonant cavity oscillator 2
The higher resonant frequency OSC exported, for example, frame clock signal output FCO (Frame Clock Output), when producing
Clock signal FOUT is simultaneously sent to linear phase-locked loop LPLL 115 by arteries and veins signal FOUT.
In addition, the fractional N-type frequency eliminator 113 is after receiving the frequency shift (FS) ratio discreet value, the fractional N-type frequency eliminator
The 113 higher resonant frequency OSC that capacitor and inductor resonant cavity oscillator 2 can be exported, for example, frame clock signal exports FCO
(Frame Clock Output) frequency elimination down, so that fractional N-type frequency eliminator 113 can export accurately clock signal 1132.
Linear phase-locked loop LPLL 114, by the clock pulse for the clock signal FOUT that the fractional N-type frequency eliminator 113 is exported
(clock) shake (jitter) is bigger, thus the clock pulse of clock signal FOUT that the fractional N-type frequency eliminator 113 is exported
The clock pulse that the clock signal FOUT that fractional N-type frequency eliminator 113 is exported will be constrained using the linear phase-locked loop LPLL 115
Shake.
Frequency-locked-loop FLL 114, the linear phase-locked loop LPLL 115 are by the clock signal after clock pulse dithering process
The clock pulse of FOUT is sent to Frequency-locked-loop FLL 114, and Frequency-locked-loop FLL 114 is according to from the linear phase-locked loop LPLL
115 and the clock pulse of the clock signal FOUT after clock pulse dithering process and the external outside clock pulse letter for being applied to it that come
Number external frequency 48Mhz or 24Mhz, and find out the M values needed for the fractional N-type frequency eliminator 113 and N values and by the M values
It is sent to the temperature-compensating processing module 112 with N values, and the temperature-compensating processor 1121 of the temperature-compensating processing module 112
More than two K values in single write-in read-only memory OTP ROM 1123, look-up table 1124 can be utilized and come from and be somebody's turn to do
The M values and N values of Frequency-locked-loop FLL 114 and obtain frequency shift (FS) ratio discreet value ((not shown)), and by the frequency shift (FS) ratio
Example discreet value sends fractional N-type frequency eliminator 113 to, so that fractional N-type frequency eliminator 113 can export accurately clock signal 1132.
In this present embodiment, integer=>N, decimal f=(K+M)/2M, wherein 2M=1000000, K change 1=>F changes
1.0ppm, and linear phase-locked loop LPLL filters out the clock pulse shake of fractional N-type frequency eliminator output；Frequency-locked-loop FLL 114 is utilized
Additional accurate external frequencies 48MHz or 24Mhz and find out N/M/K0, K25, K50, and usually 2M=1000000 is first fixed
Get off, and N can also substantially first be ordered, M, N should want the frequency that precision as needed is needed with rear class to determine.
Fig. 5 is a flow chart, to show an embodiment of the explanation using the signal processing system such as the present invention in Fig. 4
To carry out a process step of signal processing method.
As shown in Figure 5, first, it in step 31, is acted into trip temperature measurement；Via the temperature-sensitive sticker/simulation
Digital quantizer 111 learns temperature instantly by the temperature-sensitive sticker and changes into voltage, then is turned by the analog-digital converter
It changes into and controls the K values of fractional N-type frequency eliminator 113 for digital code (code) character, and different temperature will obtain different K
Value；More than two K values that read-only memory OTP ROM 1123 record different temperatures are written in the single, to do two point calibrations just
Two K values of record will do three point calibrations and just record three K values, and enter step 32.
In step 32, frequency shift (FS) ratio discreet value calculating action is carried out；The temperature-compensating processor 1122 can utilize should
More than two K values that single is written in read-only memory OTP ROM 1123, the look-up table 1124 and come from Frequency-locked-loop
The M values and N values of FLL 114 and obtain frequency shift (FS) ratio discreet value, and send the frequency shift (FS) ratio discreet value to score N
Type frequency eliminator 113, and enter step 33.
In step 33, accurate clock pulse output action is carried out；Fractional N-type frequency eliminator 113 is inclined according to the received frequency
Shifting ratio discreet value, the fractional N-type frequency eliminator 113 can export accurately clock signal 1132.
Fig. 6 is a flow chart, to show carry out frequency shift (FS) ratio of the explanation using the signal processing method in such as Fig. 5
The more detailed program of discreet value calculating action step.It carries out clock signal FOUT generating routines first as shown in Figure 6
321；The fractional N-type frequency eliminator 113, which can receive, comes from the higher resonant frequency that capacitor and inductor resonant cavity oscillator 2 is exported
OSC, for example, frame clock signal output FCO (Frame Clock Output), produces clock signal FOUT and by the clock pulse
Signal FOUT is sent to linear phase-locked loop LPLL 115, and enters program 322.
In program 322, clock pulse dithering process program is carried out；The clock signal exported by the fractional N-type frequency eliminator 113
The shake of the clock pulse of FOUT is bigger, thus the clock pulse of clock signal FOUT that the fractional N-type frequency eliminator 113 is exported will utilize
The linear phase-locked loop LPLL 115 shakes come the clock pulse for constraining the clock signal FOUT that fractional N-type frequency eliminator 113 is exported, and
Enter program 323.
In program 323, carry out finding out M values and N value programs；The linear phase-locked loop LPLL 115 will be through clock pulse dithering process
The clock pulse of clock signal FOUT afterwards is sent to Frequency-locked-loop FLL 114, and Frequency-locked-loop FLL 114 is according to from the linear lock
Phase circuit LPLL 115 and the clock pulse of the clock signal FOUT after clock pulse dithering process that comes and external it is applied to its one
External the frequency 48Mhz or 24Mhz of external clock signal, and find out M values and N needed for the fractional N-type frequency eliminator 113
The M values and N values are simultaneously sent to the temperature-compensating processing module 112 by value, and enter program 324.
In program 324, carry out obtaining frequency shift (FS) ratio discreet value program；The temperature of the temperature-compensating processing module 112
Compensation processor 1121 can utilize the single that more than two K values in read-only memory OTP ROM 1123, look-up table is written
1124 and the M values from Frequency-locked-loop FLL 114 and N values and obtain frequency shift (FS) ratio discreet value, and it is the frequency is inclined
Shifting ratio discreet value sends fractional N-type frequency eliminator 113 to.
In summary the embodiment, we can obtain a kind of signal processing system and its method of the present invention, be
In the environment that temperature-compensating applied to inductance capacitance resonant cavity (LC-Tank) alternator resonant frequency OSC is handled, this hair is utilized
When bright signal processing system is to carry out signal processing method, via temperature-sensitive sticker/analog-digital converter obtain from it is different
The relevant different K values of temperature, and K values are recorded in the single write-in read-only memory OTP of temperature-compensating processing module
ROM；Fractional N-type frequency eliminator can be by higher resonant frequency OSC that capacitor and inductor resonant cavity oscillator LC-Tank is exported down
Frequency elimination；It is shaken using linear phase-locked loop LPLL to constrain the clock pulse for the clock pulse that fractional N-type frequency eliminator is exported, Frequency-locked-loop
FLL according to after linear phase-locked loop LPLL clock pulse dithering process clock pulse and the external outside clock signal applied
Frequency, and find out the M values needed for fractional N-type frequency eliminator and N values and be sent to temperature-compensating processing module, and temperature is mended
K values, M values and N values can be sent to fractional N-type frequency eliminator by repaying processing module, when can be exported accurately so as to fractional N-type frequency eliminator
Arteries and veins signal.The signal processing system and method for the present invention includes following advantages：
Via temperature-sensitive sticker/analog-digital converter obtain from the relevant different K values of different temperature, and by K values
It is recorded in the single write-in read-only memory OTP ROM of temperature-compensating processing module；Capacitor and inductor can be total to by fractional N-type frequency eliminator
The higher resonant frequency OSC that the cavity oscillations device LC-Tank that shakes is exported is removed down；Divided to constrain using linear phase-locked loop LPLL
The clock pulse shake of the clock pulse that is exported of number N-type frequency eliminators, Frequency-locked-loop FLL according to linear phase-locked loop LPLL clock pulse shakes at
The frequency of clock pulse and the external outside clock signal applied after reason, and find out the M values needed for fractional N-type frequency eliminator
With N values and be sent to temperature-compensating processing module, and temperature-compensating processing module can send K values, M values and N values to score
N-type frequency eliminator, so that fractional N-type frequency eliminator can export accurately clock signal.
Without using opening loop temperature compensation circuit (open loop temperature compensation
Circuit it) with binary-weighted capacitors array (binary-weighted capacitor array), and can use smaller
Chip area realize drift of the self-correction inductance capacitance clock pulse generator caused by temperature.
Quartz oscillator (XTAL) can need not be utilized, difference circuit in phase need not be utilized and single-point school need not be utilized
Just, fractional N-type frequency eliminator can be enable to export accurately clock signal.
It is not to adjust the phase of voltage controlled oscillator VCO in analog pll circuit, but can be looked for using digital phase locked loop
The adjustment phase place except the relationship of frequency and temperature and phase, and fractional N-type frequency eliminator can be enable to export accurately clock pulse letter
Number.
The case where being changed with temperature linearity with inductance capacitance resonance OSC frequencies using the physical quantity of temperature linearity variation, with
More than two points determine straight line, and it is the several years that corresponding more than two temperature, which do not limit, and recycle score N
Type (fractional N) frequency elimination and inductance capacitance resonance OSC frequencies remove at required output frequency, be not have in other words
More than two different temperature of certain limit value and correct frequency elimination number, to make except frequency out to be required.
The foregoing is only a preferred embodiment of the present invention, is not limited to the scope of the present invention；It is all it is other not
It is detached from the lower equivalent change or modification completed of design design disclosed in this invention, should be included in above-mentioned claim
It is interior.
Claims (10)
1. a kind of signal processing method is applied to the environment that the temperature-compensating of inductance capacitance resonant cavity alternator resonant frequency is handled
In, including following procedure：
It is acted into trip temperature measurement；
Carry out frequency shift (FS) ratio discreet value calculating action；Using with the relevant more than two K values of temperature, look-up table and M
Value and N values and obtain frequency shift (FS) ratio discreet value；And
Carry out accurate clock pulse output action；According to the received frequency shift (FS) ratio discreet value, and when can export accurately
Arteries and veins signal.
2. signal processing method as described in claim 1, wherein the frequency shift (FS) ratio discreet value calculating action is carried out, it is multiple
Including following procedure：
Carry out clock signal FOUT generating routines；
Carry out clock pulse dithering process program；Constrain the clock pulse shake of the clock signal FOUT exported；
It carries out finding out the M values and the N value programs；According to the clock pulse of the clock signal FOUT after clock pulse dithering process and
The frequency of one outside clock signal, and find out the required M values and the N values；And
It carries out obtaining the frequency shift (FS) ratio discreet value program.
3. signal processing method as described in claim 1, wherein in carry out the temperature measurement action, via temperature-sensitive sticker/
Analog-digital converter learns temperature instantly by the temperature-sensitive sticker and changes into voltage, then is turned by the analog-digital converter
It changes into and controls more than two K values of fractional N-type frequency eliminator for digital code character and recorded.
4. signal processing method as described in claim 1, wherein carry out the frequency shift (FS) ratio discreet value calculating action；Profit
This is obtained with the relevant more than two K values of temperature, the look-up table and the M values and the N values from Frequency-locked-loop
Frequency shift (FS) ratio discreet value, and send the frequency shift (FS) ratio discreet value to the fractional N-type frequency eliminator.
5. signal processing method as described in claim 1, wherein carry out the accurate clock pulse output action；The fractional N-type frequency elimination
Device exports the accurately clock signal according to the received frequency shift (FS) ratio discreet value.
6. signal processing method as claimed in claim 2, wherein in carry out the temperature measurement action, via temperature-sensitive sticker/
Analog-digital converter learns temperature instantly by the temperature-sensitive sticker and changes into voltage, then is turned by the analog-digital converter
It changes into and controls more than two K values of fractional N-type frequency eliminator for digital code character and recorded.
7. signal processing method as claimed in claim 2, wherein carry out the frequency shift (FS) ratio discreet value calculating action；Profit
This is obtained with the relevant more than two K values of temperature, the look-up table and the M values and the N values from Frequency-locked-loop
Frequency shift (FS) ratio discreet value, and send the frequency shift (FS) ratio discreet value to the fractional N-type frequency eliminator.
8. signal processing method as claimed in claim 2, wherein carry out the accurate clock pulse output action；The fractional N-type frequency elimination
Device exports the accurately clock signal according to the received frequency shift (FS) ratio discreet value.
9. a kind of signal processing system is applied to the environment that the temperature-compensating of inductance capacitance resonant cavity alternator resonant frequency is handled
In, including：
Temperature-sensitive sticker/analog-digital converter, via the temperature-sensitive sticker/analog-digital converter, by the temperature sensing
Device learns different temperature instantly and changes into voltage, then is converted into digital code character not by the analog-digital converter
Same more than two K values；
Record is come from the temperature-sensitive sticker/simulation numeral and turned by temperature-compensating storage module, the temperature-compensating storage module
More than two K values of parallel operation；
Fractional N-type frequency eliminator, which, which can receive, comes from the resonance that capacitor and inductor resonant cavity oscillator is exported
Frequency and produce clock signal FOUT and exported it；
Clock signal FOUT is sent to the linear phase-locked loop by linear phase-locked loop, the fractional N-type frequency eliminator；Utilize the line
Property phase-locked loop come constrain the clock signal FOUT that the fractional N-type frequency eliminator is exported clock pulse shake；And
The clock pulse of clock signal FOUT after clock pulse dithering process is sent to the lock by Frequency-locked-loop, the linear phase-locked loop
Frequency circuit, the Frequency-locked-loop apply according to the clock pulse and outside of the clock signal FOUT after clock pulse dithering process
One outside clock signal frequency, and find out the M values needed for the fractional N-type frequency eliminator with the N values and transmit the M values and N values
To the temperature-compensating processing module；
Wherein, which utilizes more than two K values, look-up table and the M from the Frequency-locked-loop
Value and the N values and obtain frequency shift (FS) ratio discreet value, and send the frequency shift (FS) ratio discreet value to the fractional N-type frequency elimination
Device, so that the fractional N-type frequency eliminator can export accurately clock signal.
10. signal processing system as claimed in claim 9, wherein the temperature-compensating processing module is handled comprising temperature-compensating
Device and memory have single write-in read-only memory and the look-up table in the memory, and single write-in is read-only to deposit
Reservoir records more than two K values of different temperatures；The temperature-compensating processor can utilize the single that read-only memory is written
In more than two K values, the look-up table and the M values and the N values from the Frequency-locked-loop and obtain the frequency shift (FS)
Ratio discreet value.
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