CN108573976B - Three-dimensional memory element and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 287
- 238000003860 storage Methods 0.000 claims abstract description 50
- 239000011241 protective layer Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 46
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 8
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims 1
- 235000011114 ammonium hydroxide Nutrition 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 39
- 239000002184 metal Substances 0.000 description 39
- 229910052581 Si3N4 Inorganic materials 0.000 description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 17
- 239000000463 material Substances 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 239000002131 composite material Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000012495 reaction gas Substances 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- 229910005096 Si3H8 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 125000006850 spacer group Chemical class 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a three-dimensional memory element. The manufacturing method comprises the following steps: forming a plurality of insulation layers and a plurality of sacrificial layers which are alternately stacked on a substrate; forming at least one first opening through the insulating layer and the sacrificial layer; forming a plurality of protective layers on the surface of the sacrificial layer exposed by the side wall of the first opening; forming a charge storage layer on the side wall of the first opening, wherein the charge storage layer covers the protective layer; forming a channel layer on the charge storage layer; the sacrificial layer and the protection layer are replaced by a plurality of gate layers. The invention also provides a three-dimensional memory element.
Description
Technical Field
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a three-dimensional memory device and a method for fabricating the same.
Background
Non-volatile memory devices (e.g., flash memory) have the advantage that stored data does not disappear after power is turned off, and thus are widely used in personal computers and other electronic devices.
Flash memory arrays currently used in the industry include NOR (NOR) flash memory and NAND (NAND) flash memory. Because the structure of the NAND flash memory is that memory cells are connected in series, the integration and the area utilization rate of the NAND flash memory are better than those of the NOR flash memory, and the NAND flash memory is widely applied to various electronic products. In addition, in order to further increase the integration of memory devices, a three-dimensional NAND flash memory is developed. However, there are still many challenges associated with three-dimensional NAND flash memory.
Disclosure of Invention
The present invention provides a method for fabricating a three-dimensional memory device, which can prevent the charge storage layer from being damaged by a phosphoric acid-containing etching solution during the removal of the silicon nitride sacrificial layer, thereby improving the performance of the formed three-dimensional memory device.
The invention provides a method for manufacturing a three-dimensional memory element, which comprises the following steps. A plurality of insulation layers and a plurality of sacrificial layers are formed on the substrate in an alternating stacking manner. At least one first opening is formed through the insulating layer and the sacrificial layer. And forming a plurality of protective layers on the surface of the sacrificial layer exposed by the side wall of the first opening. And forming a charge storage layer on the side wall of the first opening, wherein the charge storage layer covers the protective layer. And forming a channel layer on the charge storage layer. Replacing the sacrificial layer and the protective layer with a plurality of gate layers.
In an embodiment of the invention, the protective layer is a silicon layer.
In an embodiment of the invention, the step of forming the protection layer includes performing a selective chemical vapor deposition process.
In one embodiment of the present invention, in the selective chemical vapor deposition process, the reaction temperature is in a range of about 300 ℃ to 520 ℃, and the reaction gas includes silane.
In one embodiment of the present invention, the maximum thickness of each layer in the protective layer is in the range of about 10 to 200 angstroms.
In an embodiment of the invention, each of the passivation layers has an arc-shaped surface.
In an embodiment of the present invention, after the step of forming the channel layer, the method further includes: forming an isolation layer under the first opening; and forming a conductor plug on the upper part of the first opening, wherein the conductor plug is in contact with the channel layer.
In an embodiment of the invention, the step of replacing the sacrificial layer and the protection layer with the gate layer includes the following steps. At least one second opening is formed through the insulating layer and the sacrificial layer. And removing the sacrificial layer and the protective layer exposed by the second opening to form a plurality of horizontal openings exposing parts of the charge storage layer. And filling the gate layer into the horizontal opening.
In an embodiment of the invention, the sacrificial layer is a silicon nitride layer, and the protection layer is a silicon layer.
In an embodiment of the invention, the step of removing the sacrificial layer and the protection layer includes: removing the sacrificial layer with an etching solution containing phosphoric acid; and removing the protective layer with an etching solution containing ammonia.
In an embodiment of the present invention, each of the gate layers includes a metal barrier layer and a metal layer.
In an embodiment of the invention, each of the gate layers further includes a metal insulating layer formed between the metal barrier layer and the charge storage layer.
The invention further provides a three-dimensional memory device, which comprises a stacked structure, a charge storage layer and a channel layer. The stacked structure is disposed on a substrate and has at least one opening passing through the stacked structure, wherein the stacked structure includes a plurality of insulating layers and a plurality of gate layers stacked alternately, and the gate layer exposed by the opening is raised relative to the insulating layer exposed by the opening. The charge storage layer is disposed on the sidewall of the opening. The channel layer is disposed on the charge storage layer.
In an embodiment of the invention, an end portion of the gate layer exposed by the opening protrudes by about 10 to 200 angstroms relative to an end portion of the insulating layer.
In an embodiment of the invention, an end portion of the gate layer has an arc-shaped surface.
In an embodiment of the invention, the end portion of the insulating layer has a substantially flat surface.
In an embodiment of the invention, the charge storage layer and the channel layer have a wavy cross section.
In one embodiment of the present invention, the charge storage layer includes an oxide-nitride-oxide composite layer.
In an embodiment of the present invention, each of the gate layers includes a metal barrier layer and a metal layer.
In an embodiment of the invention, each of the gate layers further includes a metal insulating layer, and the metal insulating layer is located between the metal barrier layer and the charge storage layer.
Based on the above, in the method of the present invention, a silicon protection layer is formed between the charge storage layer and the sacrificial layer. The silicon protection layer may be used to protect the charge storage layer from damage by a phosphoric acid-containing etching solution during removal of the silicon nitride sacrificial layer. Thus, the resulting three-dimensional memory device has improved performance.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to 1H are schematic cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the invention.
[ notation ] to show
100: substrate
101. 127: stacking structure
102. 117, 128: insulating layer
104: sacrificial layer
106. 118: opening of the container
108: protective layer
109. 111: silicon oxide layer
110: silicon nitride layer
112: charge storage layer
114: channel layer
115: insulating layer
116: conductor plug
120: horizontal opening
121: metal insulating layer
122. 130, 130: metal barrier layer
124. 132: metal layer
126: gate layer
D: distance between two adjacent plates
E1, E2: end part
R: concave part
Detailed Description
Fig. 1A to 1H are schematic cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the invention.
Referring to fig. 1A, a stack structure 101 is formed on a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. In one embodiment, a doped region may be formed in the substrate 100 according to design requirements. In addition, the stacked structure 101 includes a plurality of insulating layers 102 and a plurality of sacrificial layers 104 stacked alternately. In one embodiment, the material of the insulating layer 102 comprises silicon oxide, the material of the sacrificial layer 104 comprises silicon nitride, and the forming method comprises performing a plurality of Chemical Vapor Deposition (CVD) processes.
Then, patterning is performedIn the process, a portion of the stacked structure 101 is removed to form one or more openings 106 through the insulating layer 102 and the sacrificial layer 104. In one embodiment, a portion of the substrate 100 is also removed during the patterning process such that the opening 106 extends into the substrate 100. In one embodiment, the opening 106 may have substantially vertical or slightly sloped sidewalls, as shown in FIG. 1A. Referring to fig. 1B, a plurality of protection layers 108 are formed on the surface of the sacrificial layer 104 exposed by the sidewalls of the opening 106. In one embodiment, the step of forming the protection layer 108 includes performing a selective chemical vapor deposition (selective CVD) process. In one embodiment, when the passivation layer 108 is a silicon layer, the reaction temperature of the selective chemical vapor deposition process is in a range of about 300 ℃ to 520 ℃, and the reaction gas includes silane. The reaction temperature can be, for example, but is not limited to, about 300 ℃, 325 ℃, 350 ℃, 375 ℃, 400 ℃, 425 ℃, 450 ℃, 475 ℃, 500 ℃, 520 ℃, including any range between any two of the foregoing values. The reaction gas comprises SiH4、Si2H6、Si3H8Or a combination thereof. When the reaction temperature and the reaction gas are properly selected, the protection layer 108 (e.g., silicon layer) is selectively formed only on the sacrificial layer 104 (e.g., silicon nitride layer) and not on the insulating layer 102 (e.g., silicon oxide layer). In one embodiment, the protection layer 108 is initially formed as an amorphous silicon layer and is converted to a polysilicon layer in a subsequent process step, such as the step of forming the charge storage layer 112. In another embodiment, the protection layer 108 is initially formed as a polysilicon layer.
In one embodiment, each of the passivation layers 108 has an arc-shaped surface. More specifically, the thickness of each layer in the protective layer 108 is not uniform, but varies in the range of 1 to 200 angstroms. In one embodiment, the maximum thickness T of each of the protective layers 108 falls within a range of about 10 angstroms to about 200 angstroms. The maximum thickness T can be, for example and without limitation, about 10 angstroms, 20 angstroms, 30 angstroms, 40 angstroms, 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, including any range between any two of the foregoing values. In an embodiment, due to the configuration of the protective layer 108, the sidewalls of the opening 106 of fig. 1B are formed to have a plurality of recesses R separated, and the protective layer 108 is embedded in the recesses R, respectively.
Referring to fig. 1C, a charge storage layer 112 is formed on the sidewall of the opening 106, and the charge storage layer 112 covers the passivation layer 108 and the insulating layer 102. In one embodiment, the charge storage layer 112 is an oxide-nitride-oxide (ONO) composite layer including a silicon oxide layer 109, a silicon nitride layer 110, and a silicon oxide layer 111. In one embodiment, the method of forming the charge storage layer 112 includes performing a plurality of chemical vapor deposition processes to form an ONO composite layer, and then performing an anisotropic etching process to remove a portion of the ONO composite layer. More specifically, the charge storage layer 112 is formed on the sidewall of the opening 106 in the form of a spacer, and the bottom surface of the opening 106 is exposed.
Next, a channel layer 114 is formed on the charge storage layer 112. In one embodiment, the material of the channel layer 114 comprises polysilicon, and the forming method comprises performing a chemical vapor deposition process to form a channel material layer on the surface of the stacked structure 101 and the surface of the opening 106, and removing the channel material layer outside the opening 106. More specifically, the channel layer 114 covers the charge storage layer 112 on the side surface of the opening 106 and contacts the substrate 100 exposed from the bottom surface of the opening 106.
Referring to fig. 1D, an isolation layer 115 is formed under the opening 106. In one embodiment, the isolation layer 115 comprises silicon oxide or spin-on-dielectric (SOD) material, and the forming method comprises performing a cvd process or a spin-on process to form an isolation material layer filling the opening 106, and performing a back etching process on the isolation material layer.
Thereafter, a conductive plug 116 is formed on the upper portion of the opening 106, and the conductive plug 116 contacts the channel layer 114. In one embodiment, the material of the conductive plug 116 comprises polysilicon, and the forming method comprises performing a chemical vapor deposition process to form a conductive material layer filling the opening 106, and removing the conductive material layer outside the opening 106.
Next, an insulating layer 117 is formed on the stacked structure 101, and the insulating layer 117 covers the conductor plug 116 and the stacked structure 101. In one embodiment, the material of the insulating layer 117 includes silicon oxide, and the forming method thereof includes performing a chemical vapor deposition process.
Referring to fig. 1E to fig. 1G, the sacrificial layer 104 and the protection layer 108 are replaced by a plurality of gate layers 126. In one embodiment, as shown in fig. 1E, a patterning process is performed to remove a portion of the insulating layer 117 and a portion of the stacked structure 101, so as to form one or more openings 118 through the insulating layer 117, the insulating layer 102 and the sacrificial layer 104. In one embodiment, portions of the substrate 100 are also removed during the patterning process such that the openings 118 extend into the substrate 100. In one embodiment, the opening 118 may have substantially vertical or slightly sloped sidewalls, as shown in FIG. 1E. In one embodiment, the bottom of opening 118 is lower than the bottom of opening 106.
Next, as shown in fig. 1F, the sacrificial layer 104 and the protection layer 108 exposed by the opening 118 are removed to form a plurality of horizontal openings 120 exposing portions of the charge storage layer 112. In one embodiment, the protective layer 108 is used as an etch stop layer, using phosphoric acid (H) as the etch stop layer3PO4) The etching solution removes sacrificial layer 104. In one embodiment, after removing the sacrificial layer 104, ammonia (NH) is added4OH) to remove the protective layer 108.
In particular, in the conventional method, since the etching selectivity of the etching solution containing phosphoric acid to silicon nitride/silicon oxide is not high enough, the ONO charge storage layer adjacent to the silicon nitride sacrificial layer is damaged during the removal of the silicon nitride sacrificial layer, which results in the reduction of the storage efficiency and the failure of the device. However, in the present invention, the formation of the silicon protection layer between the ONO charge storage layer and the silicon nitride sacrificial layer prevents the charge storage layer from being damaged by the etching solution containing phosphoric acid. More specifically, due to the relatively high silicon nitride/silicon etch selectivity, the silicon protection layer 108 of the present invention may be used to protect the silicon oxide layer 109 and/or the silicon nitride layer 110 of the charge storage layer 112 from the phosphoric acid-containing etching solution during the removal of the silicon nitride sacrificial layer 104.
Then, as shown in FIG. 1G, the horizontal opening 120 is filled with a gate layer126. In one embodiment, each of the gate layers 126 includes a metal barrier layer 122 and a metal layer 124. In one embodiment, the material of the metal barrier layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, and the forming method thereof includes performing a chemical vapor deposition process. In one embodiment, the material of the metal layer 124 includes tungsten (W), and the forming method thereof includes performing a chemical vapor deposition process. In one embodiment, each layer in the gate layer 126 further includes a metal insulating layer 121, and the metal insulating layer 121 is formed between the metal barrier layer 122 and the charge storage layer 112. In one embodiment, the material of the metal insulating layer 121 includes a metal oxide having a dielectric constant greater than 8 or even greater than 10, such as aluminum oxide (Al)2O3) And a method of forming the same includes performing a chemical vapor deposition process or an Atomic Layer Deposition (ALD) process. In one embodiment, the metal insulation layer 121, the metal barrier layer 122 and the metal layer 124 not only fill the horizontal openings 120, but also are formed on the surface of the openings 118, as shown in fig. 1G.
Referring to fig. 1H, the metal insulation layer 121, the metal barrier layer 122 and the metal layer 124 in the opening 118 are removed. Next, the opening 118 is sequentially filled with an insulating layer 128, a metal barrier layer 130 and a metal layer 132. In one embodiment, the material of the insulating layer 128 comprises silicon oxide, the material of the metal barrier layer 130 comprises titanium nitride, and the material of the metal layer 132 comprises tungsten. In one embodiment, during the removal step, a portion of the metal insulation layer 121, a portion of the metal barrier layer 122, and a portion of the metal layer 124 in the horizontal opening 120 adjacent to the opening 118 are also removed, and this space is filled with the subsequent insulation layer 128. Thus, the fabrication of the three-dimensional memory device of the present invention is completed.
Hereinafter, the structure of the three-dimensional memory element of the present invention will be described with reference to fig. 1H. The three-dimensional memory device of the present invention includes a stacked structure 127, a charge storage layer 112, and a channel layer 114. The stack structure 127 is disposed on the substrate 100 and has at least one opening 106 passing through the stack structure 127. The stack structure 127 includes a plurality of insulating layers 102 and a plurality of gate layers 126 stacked alternately, and the gate layer 126 exposed by the opening 106 is raised with respect to the insulating layer 102 exposed by the opening 106. In one embodiment, the end E1 of the gate layer 126 exposed by the opening 106 protrudes by about 10 to 200 angstroms relative to the end E2 of the insulating layer 102. More specifically, in one embodiment, the end portion E1 of the gate layer 126 has an arc-shaped surface, the end portion E2 of the insulating layer 102 has a substantially flat surface, and the end portion E1 of the gate layer 126 protrudes beyond the end portion E2 of the insulating layer 102 by a distance D in a range of about 10 to 200 angstroms. The distance D can be, for example and without limitation, about 10 angstroms, 20 angstroms, 30 angstroms, 40 angstroms, 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, including any range between any two of the foregoing values.
From another perspective, the side wall of the opening 106 has a plurality of recesses R separated, and the end portion E1 of the gate layer 126 is embedded in the recesses R. In one embodiment, the gate layer 126 includes an optional metal insulating layer 121, a metal barrier layer 122 and a metal layer 124, and a portion of the metal insulating layer 121, a portion of the metal barrier layer 122 and a portion of the metal layer 124 are located in the recess R at the sidewall of the opening 106.
The charge storage layer 112 is disposed on the sidewall of the opening 106. In one embodiment, the charge storage layer 112 comprises an ONO composite layer. The channel layer 114 is disposed on the charge storage layer 112. In one embodiment, the channel layer 114 comprises polysilicon. In one embodiment, since the gate layer 126 in the stack structure 127 is raised with respect to the insulating layer 102, the charge storage layer 112 and the channel layer 114 adjacent to the stack structure 127 have a wave-like profile. In another embodiment, the side of the charge storage layer 112 adjacent to the stacked structure 127 has a wavy cross section, and the side away from the stacked structure 127 has a substantially flat cross section. In one embodiment, the charge storage layer 112 is disposed on the sidewall of the opening 106 but exposes the bottom surface of the opening 106, and the channel layer 114 is disposed on the sidewall and the bottom surface of the opening 106 and contacts the substrate 100.
In one embodiment, the three-dimensional memory device of the present invention further includes an isolation layer 115 and a conductor plug 116. The isolation layer 115 is located below the opening 106, and the channel layer 114 surrounds the isolation layer 115. A conductor plug 116 is located at an upper portion of the opening 106 and contacts the channel layer 114.
In summary, in the method of the present invention, the silicon passivation layer is formed between the ONO charge storage layer and the silicon nitride sacrificial layer, so as to prevent the charge storage layer from being damaged by the etching solution containing phosphoric acid. More specifically, the silicon protection layer of the present invention may be used to protect the charge storage layer from the phosphoric acid-containing etching solution during the removal of the silicon nitride sacrificial layer due to the relatively high silicon nitride/silicon etch selectivity. Thus, the resulting three-dimensional memory device has improved performance.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, but rather, may be embodied in many different forms and modifications without departing from the spirit and scope of the present invention.
Claims (10)
1. A method of fabricating a three-dimensional memory device, comprising:
forming a plurality of insulation layers and a plurality of sacrificial layers which are alternately stacked on a substrate;
forming at least one first opening through the insulating layers and the sacrificial layers;
forming a plurality of protective layers on the surfaces of the sacrificial layers exposed by the side walls of each of the at least one first opening;
forming a charge storage layer on the side wall of the first opening, wherein the charge storage layer covers the protective layers;
forming a channel layer on the charge storage layer; and
replacing the sacrificial layers and the protective layers with gate layers, comprising: removing the sacrificial layer by using an etching solution containing phosphoric acid, wherein the protective layer is used for protecting the charge storage layer from being damaged by the etching solution containing phosphoric acid, removing the protective layer by using an etching solution containing no phosphoric acid so as to form a plurality of horizontal openings, and filling the gate electrode layers into the horizontal openings;
the protective layer is selectively formed only on the sacrificial layer, but not on the insulating layer.
2. The method of claim 1, wherein the passivation layers are silicon layers.
3. The method of claim 1, wherein the step of forming the passivation layers comprises performing a selective chemical vapor deposition process.
4. The method of claim 1, wherein each of the protective layers has a maximum thickness in a range of 10 to 200 angstroms.
5. The method of claim 1, wherein the step of replacing the sacrificial layers and the passivation layers with the gate layers further comprises: at least one second opening is formed through the insulating layers and the sacrificial layers.
6. The method of manufacturing a three-dimensional memory element according to claim 5, wherein the step of removing the protective layer using an etching solution containing no phosphoric acid includes: and removing the protective layers by using an etching solution containing ammonia water.
7. A three-dimensional memory element fabricated based on the method of any one of claims 1-6, comprising:
a stacked structure disposed on a substrate and having at least one opening passing through the stacked structure, wherein the stacked structure comprises a plurality of insulating layers and a plurality of gate layers stacked alternately, and the gate layers exposed by the opening are raised relative to the insulating layers exposed by the opening;
a charge storage layer disposed on the sidewall of the opening; and
a channel layer disposed on the charge storage layer.
8. The three-dimensional memory device of claim 7, wherein the gate layers exposed by the opening have ends that protrude 10-200 angstroms from the ends of the insulating layers.
9. The three-dimensional memory element according to claim 7, wherein end portions of the gate layers have arc-shaped surfaces, and end portions of the insulating layers have flat surfaces.
10. The three-dimensional memory element of claim 7, wherein the charge storage layer and the channel layer have a wavy cross-section.
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