CN108572785A - A kind of NAND-FLASH memory read operations method and device - Google Patents
A kind of NAND-FLASH memory read operations method and device Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The present invention provides a kind of NAND FLASH memories read operation method and devices, are related to data memory operations technical field.A kind of NAND FLASH memories read operation method and device provided by the invention, it is effective that reading enable signal is triggered using clock cycle fractional frequency signal is read, so that the term of validity for reading enable signal was limited in multiple clock cycle, then in the term of validity of the reading enable signal, it will be in the register of the data buffer storage in page buffer to setting quantity, the effective time for increasing data buffer storage, the efficiency of NAND FLASH memory read operations can be improved while ensureing that read operation is normally carried out.
Description
Technical field
The present invention relates to data memory operations technical fields, more particularly to a kind of NAND-FLASH memory read operations
Method and device.
Background technology
NAND-FLASH memories, it is internal to use non-linear macroelement pattern, it is carried for the realization of solid-state large-capacity memory
Cheap effective solution scheme is supplied, therefore, NAND-FLASH memories are widely adopted in PC and electronic equipment etc.
Deng.It is first, data are (English from storage array when NAND-FLASH memories carry out read operation：Array it is slow that page is read in)
Storage (English：Page buffer) in, then, according to externally input clock signal, the digital independent in page buffer is arrived
I/O interface exports.Since the data stored in page buffer are relatively more, and the I/O interface of NAND-FLASH memories is generally 16
It is a or 8, when data are read I/O interface from page buffer every time being exported, it can only once update output 16
Position (English：Bit) or 8 data, it that is to say a word (English：Word) or a byte is (English：Byte), therefore,
It is generally necessary to which multiple external read clock periods could be finished the data in page buffer by I/O interface output.
In order to which when external timing signal arrives, quickly the data in page buffer can be exported from I/O interface,
Register would generally be inserted between page buffer and I/O interface, using reading, clock cycle signal triggering reading enable signal is effective,
In the term of validity for reading the reading enable signal of clock cycle limitation at one, the data exported will be needed to carry in each reading clock cycle
In preceding caching to register, within each reading clock cycle, the data in register are exported by the I/O interface of memory.
In the prior art, when by data buffer storage to register, the data buffer storage time has been limited in one and has read clock week
It, can be because cache-time not enough caches when operating spread of voltage for example, in the case of brownout in phase
Mistake, and then cause to read error in data, the stability of read operation is poor.
Invention content
In view of the above problems, it is proposed that the present invention overcoming the above problem in order to provide one kind or solves at least partly
State a kind of NAND-FLASH memory read operations method and device of problem.
According to the present invention in a first aspect, provide a kind of NAND-FLASH memory read operations method, including：
Enable signal is read using the triggering of clock cycle fractional frequency signal is read, keeps the reading enable signal effective；
It, will be in the register of the data buffer storage in page buffer to setting quantity in the reading enable signal term of validity；
Data in the register of the setting quantity are exported by the I/O interface of memory.
Optionally, the reading clock cycle fractional frequency signal is to read clock cycle two divided-frequency signal, read clock cycle three frequency division
Signal ... reads any one in clock cycle Fractional-N frequency signal.
Optionally, the reading clock cycle fractional frequency signal is generated by preset d type flip flop.
Optionally, the register for setting quantity as with the deposit that is correspondingly arranged of reading clock cycle fractional frequency signal
Device.
Optionally, it is described using read the clock cycle read clock cycle fractional frequency signal triggering read enable signal the step of it
Before, the method further includes：
Receive data read command, wherein the data read command includes destination address；
According to the destination address, it would be desirable to which the data for executing read operation are stored into page buffer.
Optionally, described according to the destination address, it would be desirable to which that the data for executing read operation are stored into page buffer
Step, including：
It is inquired in storage array according to the destination address, obtains page data corresponding with the destination address；
The page data is stored into page buffer.
Second aspect according to the present invention provides a kind of NAND-FLASH memory read operations device, including：
Trigger module, for using clock cycle fractional frequency signal triggering reading enable signal is read, the reading enable signal being made to have
Effect；
Cache module, in the reading enable signal term of validity, by the data buffer storage in page buffer to setting number
In the register of amount；
Output module, for exporting the data in the register of the setting quantity by the I/O interface of memory.
Optionally, the reading clock cycle fractional frequency signal is to read clock cycle two divided-frequency signal, read clock cycle three frequency division
Signal ... reads any one in clock cycle Fractional-N frequency signal.
Optionally, the reading clock cycle fractional frequency signal is generated by preset d type flip flop.
Optionally, the register for setting quantity as with the deposit that is correspondingly arranged of reading clock cycle fractional frequency signal
Device.
Optionally, described device further includes：
Receiving module, for receiving data read command, wherein the data read command includes destination address；
Memory module, for according to the destination address, it would be desirable to which the data for executing read operation are stored into page buffer.
Optionally, the memory module, including：
Acquisition submodule is obtained with the target for being inquired in storage array according to the destination address
The corresponding page data in location；
Sub-module stored, for storing the page data into page buffer.
For first technology, the present invention has following advantage：
A kind of NAND-FLASH memory read operations method and device provided in an embodiment of the present invention utilizes the reading clock cycle
Fractional frequency signal is effective to trigger reading enable signal so that the term of validity for reading enable signal was limited in multiple clock cycle, so
It can protected in the register of the data buffer storage in page buffer to setting quantity in the term of validity of the reading enable signal afterwards
While card read operation is normally carried out, the effective time for increasing data buffer storage, NAND-FLASH memory read operations are improved
Efficiency.
Above description is only the general introduction of technical solution of the present invention, in order to better understand the technical means of the present invention,
And can be implemented in accordance with the contents of the specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, below the special specific implementation mode for lifting the present invention.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, various other advantages and benefit are common for this field
Technical staff will become clear.Attached drawing only for the purpose of illustrating preferred embodiments, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings：
Fig. 1 is a kind of NAND-FLASH memory read operations method and step flow chart provided in an embodiment of the present invention；
Fig. 2-1 is another kind NAND-FLASH memory read operation method and step flow charts provided in an embodiment of the present invention；
Fig. 2-2 is a kind of d type flip flop schematic diagram provided in an embodiment of the present invention；
Fig. 2-3 is a kind of read operation schematic diagram provided in an embodiment of the present invention；
Fig. 3 is a kind of NAND-FLASH memory read operations device block diagram provided in an embodiment of the present invention；
Fig. 4-1 is another kind NAND-FLASH memory read operation device block diagrams provided in an embodiment of the present invention；
Fig. 4-2 is another NAND-FLASH memory read operation device block diagram provided in an embodiment of the present invention；
Fig. 4-3 is a kind of memory module block diagram provided in an embodiment of the present invention.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
Embodiment one
Referring to Fig.1, it illustrates a kind of NAND-FLASH memory read operations method and step flows of the embodiment of the present invention
Figure, this method can specifically include following steps：
Step 101 reads enable signal using reading clock cycle fractional frequency signal triggering, keeps the reading enable signal effective.
Wherein, it reads enable signal to can serve to indicate that in the data buffer storage to register in page buffer, practical application
In, reading the failing edge of clock cycle fractional frequency signal can trigger that the reading enable signal is effective, which can
Think and read clock cycle Fractional-N frequency signal, wherein N is the positive integer more than 1, correspondingly, being believed using the reading clock cycle Fractional-N frequency
Number reading enable signal is triggered, can to trigger that primary to read enable signal effective every N number of failing edge so that reads enable signal
The term of validity be limited in N number of reading clock cycle, can effectively increase read enable signal the term of validity.
Step 102, in the reading enable signal term of validity, the data buffer storage in page buffer to setting quantity is posted
In storage.
Wherein, it is that can carry out the time of data buffer storage to read the enable signal term of validity, in the reading enable signal term of validity
It is interior, can be by the register of the data buffer storage in the page buffer to setting quantity, the register of the setting quantity can be
With read the corresponding register of clock cycle fractional frequency signal, in the embodiment of the present invention, the term of validity due to reading enable signal is limited
Within multiple reading clock cycle, that is, it is exactly to increase the data buffer storage time, then when carrying out data buffer storage, just needs
Corresponding data are cached, can ensure being normally carried out for read operation in this way, therefore the quantity of register needs and read clock
Period fractional frequency signal is corresponding.
Step 103 exports the data in the register of the setting quantity by the I/O interface of memory.
In each failing edge for reading clock cycle fractional frequency signal, having by memory I O Interface output data can be all triggered
Signal is imitated, which, which can serve to indicate that, exports the data in memory by I/O interface, in this way, each failing edge
A byte or the data of a word can be exported by the I/O interface of memory.In above-mentioned steps 102, caching to setting number
Data in the register of amount disclosure satisfy that and export a byte or one by the I/O interface of memory in each failing edge
The data of a word.
In conclusion a kind of NAND-FLASH memory read operations method provided in an embodiment of the present invention, utilizes reading clock
Period fractional frequency signal is effective to trigger reading enable signal so that the term of validity for reading enable signal is limited in multiple clock cycle
It is interior, then in the term of validity of the reading enable signal, the data buffer storage in page buffer is extremely set in the register of quantity, it can
While ensureing that read operation is normally carried out, the effective time for increasing data buffer storage improves the reading of NAND-FLASH memories
The efficiency of operation.
Embodiment two
With reference to Fig. 2-1, it illustrates another NAND-FLASH memory read operations method and steps of the embodiment of the present invention
Flow chart, this method can specifically include following steps：
Step 201 receives data read command, wherein the data read command includes destination address.
Memory can receive data read command, which can serve to indicate that the number in storage array
According to being read out, wherein may include destination address in the data read command, which can be used to refer to store
Need the address of the data of execution read operation.
Step 202, according to the destination address, it would be desirable to the data for executing read operation are stored into page buffer.
Wherein, which executes the data of read operation, the data as stored in destination address.Specifically, the step
202 may include：
Step 2021 is inquired according to the destination address in storage array, is obtained corresponding with the destination address
Page data.
It is exemplary, inquiry can be realized into row address comparison, after address compares successfully, obtain using the destination address
Page data corresponding with destination address.
Step 2022 stores the page data into page buffer.
After getting the corresponding page data of destination address, which can be stored into page buffer, generally
Reading for NAND-FLASH memories and programming operation, be all using page as least unit carry out, so, NAND-FLASH is deposited
Corresponding region can be arranged in reservoir, will be written to being gone in storage array dedicated for storage or rigid be read from storage array
The data of the one page taken out, this corresponding region, is exactly page buffer.
Step 203 reads enable signal using reading clock cycle fractional frequency signal triggering, keeps the reading enable signal effective.
The reading clock cycle fractional frequency signal can be to read clock cycle two divided-frequency signal, read clock cycle three frequency division signal ...
Any one in clock cycle Fractional-N frequency signal is read, when the reading clock cycle fractional frequency signal is to read clock cycle two divided-frequency signal
When, the failing edge triggering reading enable signals every two reading clock cycle signals can be made effective, wherein it is enabled to trigger the reading
Signal is effective, can be that triggering reads enable signal for high level, when the reading clock cycle fractional frequency signal is to read the clock cycle three to divide
When frequency signal, the failing edge triggering reading enable signals every three reading clock cycle signals can be made effective, when the reading clock
Period fractional frequency signal is that when reading four fractional frequency signal of clock cycle, the failing edge for reading clock cycle signal every four can be made to touch
Hair reading enable signal is effective, and so on.It is effective using clock cycle fractional frequency signal triggering reading enable signal is read in this way, it can make
The effective time for obtaining data buffer storage was limited in inside multiple clock cycle, was read in the clock cycle for example, being limited in two, four
In a reading clock cycle, the data buffer storage time is improved.It should be noted that in practical application, the clock cycle point is read selecting
When frequency signal, even number reads realization difficulty of the clock cycle fractional frequency signal compared to the reading clock cycle fractional frequency signal of odd number
Smaller, also more preferably, general recommendations is using reading clock cycle two divided-frequency signal as trigger signal for realization effect.
Wherein, which can be generated by preset d type flip flop, to read the clock cycle two
For fractional frequency signal, Fig. 2-2 is a kind of d type flip flop schematic diagram provided in an embodiment of the present invention, as shown in Fig. 2-2, the d type flip flop
It can specifically include：The ends CLK, the ends Q andEnd and the ends D, specific implementation when, can will read clock cycle signal from
The ends CLK input, willEnd is connected with the ends D, and the signal exported from the ends Q is corresponding reading clock cycle two divided-frequency signal.It needs
Illustrate, in another alternative embodiment of the present invention, can also be provided in other ways and read clock cycle fractional frequency signal,
For example, being realized by frequency divider.
Step 204, in the reading enable signal term of validity, the data buffer storage in page buffer to setting quantity is posted
In storage.
Wherein, this sets the register of quantity as the register that is correspondingly arranged with above-mentioned reading clock cycle fractional frequency signal,
Exemplary, under normal circumstances, NAND-FLASH memories are all with byte mode or word pattern when carrying out read operation
It carries out, correspondingly, register can be generally eight bit register or 16 bit registers, by taking word pattern as an example, when the reading clock
Period fractional frequency signal is that when reading clock cycle Fractional-N frequency signal, corresponding 16 bit register of N groups can be arranged, actually answering
Can also be the corresponding one group of 16*N bit register of setting in, as long as can reach identical storage effect, the present invention is real
Example is applied not limit this.
For example, when the reading clock cycle fractional frequency signal is to read clock cycle two divided-frequency signal, correspondence can be set
Two group of 16 bit register, alternatively, can also be corresponding one group of 32 bit register of setting.It is when reading clock cycle fractional frequency signal
When reading clock cycle three frequency division signal, corresponding three group of 16 bit register can be set, alternatively, setting is one group 48 corresponding
Bit register.
It, can be with when the reading clock cycle fractional frequency signal is to read clock cycle Fractional-N frequency signal by taking byte mode as an example
Corresponding N groups eight bit register is set, can also be the corresponding one group of 8*N bit register of setting, as long as energy in practical applications
Reach identical storage effect, it is not limited in the embodiment of the present invention.
For example, when the reading clock cycle fractional frequency signal is to read clock cycle two divided-frequency signal, correspondence can be set
Two groups of eight bit registers, alternatively, can also be corresponding one group of 16 bit register of setting.It is when reading clock cycle fractional frequency signal
When reading clock cycle three frequency division signal, corresponding three groups of eight bit registers can be set, alternatively, setting is one group 24 corresponding
Bit register.
Step 205 exports the data in the register of the setting quantity by the I/O interface of memory.
Wherein, the failing edge for each reading clock cycle fractional frequency signal, can all trigger through memory I O Interface output data
Useful signal, which can indicate to export the data in memory by I/O interface, in this way, each failing edge
A byte or the data of a word can be exported by the I/O interface of memory.Therefore, it is necessary to be arranged and read the clock cycle point
The corresponding register of frequency signal, disclosure satisfy that with the data ensured in register and is connect by the IO of memory in each failing edge
The data of mouth one byte of output or a word.
The read operation method of the embodiment of the present invention is illustrated with a specific example below.With type matrix in this specific example
Formula is exactly once to export 16 data instances by the I/O interface of memory, to the read operations of NAND-FLASH memories into
Row explanation.Fig. 2-3 is a kind of read operation schematic diagram provided in an embodiment of the present invention, and as Figure 2-3, the REB in figure indicates to read
Clock cycle signal, the read clock signal in figure are to read clock cycle two divided-frequency signal, wherein READ indicates to read enabled letter
Number, the high level lasting time of READ is the term of validity for reading enable signal, can be by caching of page between the high period of READ
In data buffer storage to the register of setting quantity in device.What the Output in figure was indicated is to export number by memory I O Interface
According to signal, each failing edge for reading clock cycle signal, which can trigger the signal by memory I O Interface output data, to be had
Effect, the useful signal can indicate to export the data in memory by I/O interface, that is, be exactly, and believe in each reading clock cycle
Number failing edge can all begin through memory I/O interface export 16 data.It can be seen from the figure that reading clock at two
Operation can be exported in the period of periodic signal twice, exports 16 data every time, just needs the output 32 to be in two periods
Data, it is corresponding that the data of caching 32 are just needed between the high period of READ, therefore when register is set, need
Setting two group of 16 bit register corresponding with clock cycle two divided-frequency signal is read, it can be seen from the figure that the height electricity of each READ
The flat duration has been limited in two and has read inside the clock cycle, compared with the prior art the high level lasting time quilt of middle READ
It is limited in one to read inside the clock cycle, the embodiment of the present invention can be obviously improved the effective time that READ reads enable signal.
In conclusion a kind of NAND-FLASH memory read operations method provided in an embodiment of the present invention, utilizes reading clock
Period fractional frequency signal is effective to trigger reading enable signal so that the term of validity for reading enable signal is limited in multiple clock cycle
It is interior, then in the term of validity of the reading enable signal, the data buffer storage in page buffer is extremely set in the register of quantity, it can
While ensureing that read operation is normally carried out, the effective time for increasing data buffer storage improves the reading of NAND-FLASH memories
The efficiency of operation.
Embodiment three
Referring to Fig. 3, it illustrates a kind of block diagram of NAND-FLASH read operations device 30 of the embodiment of the present invention, such as Fig. 3
Shown, which may include：
Trigger module 301, for using clock cycle fractional frequency signal triggering reading enable signal is read, making the reading enable signal
Effectively.
Cache module 302, in the reading enable signal term of validity, the data buffer storage in page buffer extremely to be set
In the register of quantity.
Output module 303, for exporting the data in the register of the setting quantity by the I/O interface of memory.
In conclusion a kind of NAND-FLASH memory read operations device provided in an embodiment of the present invention, utilizes reading clock
Period fractional frequency signal is effective to trigger reading enable signal so that the term of validity for reading enable signal is limited in multiple clock cycle
It is interior, then in the term of validity of the reading enable signal, the data buffer storage in page buffer is extremely set in the register of quantity, it can
While ensureing that read operation is normally carried out, the effective time for increasing data buffer storage improves the reading of NAND-FLASH memories
The efficiency of operation.
Example IV
Referring to Fig. 4-1, it illustrates the block diagrams of another NAND-FLASH read operations device 40 of the embodiment of the present invention, such as
Shown in Fig. 4-1, which may include：
Trigger module 401, for using clock cycle fractional frequency signal triggering reading enable signal is read, making the reading enable signal
Effectively.
Cache module 402, in the reading enable signal term of validity, the data buffer storage in page buffer extremely to be set
In the register of quantity.
Output module 403, for exporting the data in the register of the setting quantity by the I/O interface of memory.
Optionally, the reading clock cycle fractional frequency signal is to read clock cycle two divided-frequency signal, read clock cycle three frequency division
Signal ... reads any one in clock cycle Fractional-N frequency signal.
Optionally, the reading clock cycle fractional frequency signal is generated by preset d type flip flop.
Optionally, the register for setting quantity as with the deposit that is correspondingly arranged of reading clock cycle fractional frequency signal
Device.
Fig. 4-2 is the block diagram of another NAND-FLASH read operations device 40 provided in an embodiment of the present invention, such as Fig. 4-2 institutes
Show, which may include：Trigger module 401, cache module 402, output module 403, receiving module 404 and storage mould
Block 405
Trigger module 401, for using clock cycle fractional frequency signal triggering reading enable signal is read, making the reading enable signal
Effectively.
Cache module 402, in the reading enable signal term of validity, the data buffer storage in page buffer extremely to be set
In the register of quantity.
Output module 403, for exporting the data in the register of the setting quantity by the I/O interface of memory.
Receiving module 404, for receiving data read command, wherein the data read command includes destination address.
Memory module 405, for according to the destination address, it would be desirable to which the data for executing read operation are stored to page buffer
In.
Fig. 4-3 is a kind of block diagram of memory module 405 provided in an embodiment of the present invention, referring to Fig. 4-3, memory module 405
May include：
Acquisition submodule 4051 obtains and the mesh for being inquired in storage array according to the destination address
Mark the corresponding page data in address.
Sub-module stored 4052, for storing the page data into page buffer.
In conclusion a kind of NAND-FLASH memory read operations device provided in an embodiment of the present invention, utilizes reading clock
Period fractional frequency signal is effective to trigger reading enable signal so that the term of validity for reading enable signal is limited in multiple clock cycle
It is interior, then in the term of validity of the reading enable signal, the data buffer storage in page buffer is extremely set in the register of quantity, it can
While ensureing that read operation is normally carried out, the effective time for increasing data buffer storage improves the reading of NAND-FLASH memories
The efficiency of operation.
For device embodiments, since it is basically similar to the method embodiment, so fairly simple, the correlation of description
Place illustrates referring to the part of embodiment of the method.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that the implementation of the present invention
Example can be put into practice without these specific details.In some instances, well known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this description.
Similarly, it should be understood that in order to simplify the disclosure and help to understand one or more of each inventive aspect,
Above in the description of exemplary embodiment of the present invention, each feature of the invention is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：It is i.e. required to protect
Shield the present invention claims the more features of feature than being expressly recited in each claim.More precisely, as following
Claims reflect as, inventive aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following specific implementation mode are expressly incorporated in the specific implementation mode, wherein each claim itself
All as a separate embodiment of the present invention.
Those skilled in the art, which are appreciated that, to carry out adaptively the module in the equipment in embodiment
Change and they are arranged in the one or more equipment different from the embodiment.It can be the module or list in embodiment
Member or component be combined into a module or unit or component, and can be divided into addition multiple submodule or subelement or
Sub-component.Other than such feature and/or at least some of process or unit exclude each other, it may be used any
Combination is disclosed to all features disclosed in this specification (including adjoint claim, abstract and attached drawing) and so to appoint
Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification (including adjoint power
Profit requires, abstract and attached drawing) disclosed in each feature can be by providing the alternative features of identical, equivalent or similar purpose come generation
It replaces.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included certain features rather than other feature, but the combination of the feature of different embodiments means in of the invention
Within the scope of and form different embodiments.For example, in the following claims, embodiment claimed is appointed
One of meaning mode can use in any combination.
It should be noted that the present invention will be described rather than limits the invention for above-described embodiment, and ability
Field technique personnel can design alternative embodiment without departing from the scope of the appended claims.In the claims,
Any reference mark between bracket should not be configured to limitations on claims.Word "comprising" does not exclude the presence of not
Element or step listed in the claims.Word "a" or "an" before element does not exclude the presence of multiple such
Element.The present invention can be by means of including the hardware of several different elements and being come by means of properly programmed computer real
It is existing.In the unit claims listing several devices, several in these devices can be by the same hardware branch
To embody.The use of word first, second, and third does not indicate that any sequence.These words can be explained and be run after fame
Claim.
Claims (12)
1. a kind of NAND-FLASH memory read operations method, which is characterized in that including：
Enable signal is read using the triggering of clock cycle fractional frequency signal is read, keeps the reading enable signal effective；
It, will be in the register of the data buffer storage in page buffer to setting quantity in the reading enable signal term of validity；
Data in the register of the setting quantity are exported by the I/O interface of memory.
2. according to the method described in claim 1, it is characterized in that, the reading clock cycle fractional frequency signal is to read the clock cycle two
Fractional frequency signal, reading clock cycle three frequency division signal ... read any one in clock cycle Fractional-N frequency signal.
3. according to the method described in claim 2, it is characterized in that, the reading clock cycle fractional frequency signal is by preset D
What trigger generated.
4. according to the method described in claim 1, it is characterized in that, the register for setting quantity as with the reading clock week
The register that phase fractional frequency signal is correspondingly arranged.
5. according to the method described in claim 1, it is characterized in that, reading to make using reading clock cycle fractional frequency signal triggering described
Before the step of energy signal, the method further includes：
Receive data read command, wherein the data read command includes destination address；
According to the destination address, it would be desirable to which the data for executing read operation are stored into page buffer.
6. according to the method described in claim 5, it is characterized in that, described according to the destination address, it would be desirable to execute and read behaviour
The data of work store the step into page buffer, including：
It is inquired in storage array according to the destination address, obtains page data corresponding with the destination address：
The page data is stored into page buffer.
7. a kind of NAND-FLASH memory read operations device, which is characterized in that including：
Trigger module, for using clock cycle fractional frequency signal triggering reading enable signal is read, keeping the reading enable signal effective；
Cache module, in the reading enable signal term of validity, the data buffer storage in page buffer extremely to be set quantity
In register；
Output module, for exporting the data in the register of the setting quantity by the I/O interface of memory.
8. device according to claim 7, which is characterized in that the reading clock cycle fractional frequency signal is to read the clock cycle two
Fractional frequency signal, reading clock cycle three frequency division signal ... read any one in clock cycle Fractional-N frequency signal.
9. device according to claim 8, which is characterized in that the reading clock cycle fractional frequency signal is by preset D
What trigger generated.
10. device according to claim 7, which is characterized in that the register for setting quantity as with the reading clock
The register that period fractional frequency signal is correspondingly arranged.
11. device according to claim 7, which is characterized in that described device further includes：
Receiving module, for receiving data read command, wherein the data read command includes destination address；
Memory module, for according to the destination address, it would be desirable to which the data for executing read operation are stored into page buffer.
12. according to the devices described in claim 11, which is characterized in that the memory module, including：
Acquisition submodule obtains and the destination address pair for being inquired in storage array according to the destination address
The page data answered；
Sub-module stored, for storing the page data into page buffer.
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| WO2022226820A1 (en) * | 2021-04-28 | 2022-11-03 | Yangtze Memory Technologies Co., Ltd. | Clock signal return scheme for data read in page buffer of memory device |
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