CN106598548A - Solution method and device for read-write conflict of storage unit - Google Patents
Solution method and device for read-write conflict of storage unit Download PDFInfo
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- 230000004044 response Effects 0.000 claims description 32
- 238000013500 data storage Methods 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 12
- 238000013507 mapping Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000004080 punching Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30138—Extension of register space, e.g. register cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
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Abstract
The invention provides a solution method and device for a read-write conflict of a storage unit. The method comprises the following steps: a new storage module is established, which includes an original memory and at least one set of newly added data registers; an initial address pointer res is arranged for the data register; when a data reading request and a data writing request are received at the same time for the same data register address within the same clock cycle, the data reading request is responded normally and data corresponding to the reading address for the current reading request is read; the writing address for the current writing request is mapped to the storage module where the current address pointer res is arranged so as to encode the current address pointer res into the writing address for the current writing request and write the data at the data register address pointed by the address pointer res; and meanwhile, the reading address corresponding to the current data reading request is encoded into a new address pointer res. According to the invention, the method ensures that the old data can be read effectively in terms of the reading request during the read-write conflict, and meanwhile, the writing request can be responded normally.
Description
Technical field
The present invention relates to network communication field, more particularly to a kind of solution and device of memory element read/write conflict.
Background technology
At present, it is required for using in all of chip memory element, conventional memory element is to run into read-write same
Conflict can be produced when location, and for the memory element of different manufacturers, its mode for processing conflict is different, chip design is public
Take charge of the comprehensive various conditions of needs in design and select manufacturers, when read/write conflict needs effectively reading data earlier, some
This function is not supported in the design of manufacturer, and its solution is usually, to lose a part of access bandwidth, it is to avoid read-write punching
It is prominent；This implementation, the design to chip produce excessive restriction, are unfavorable for the development of chip.
The content of the invention
It is an object of the invention to provide the solution and device of a kind of memory element read/write conflict.
One of for achieving the above object, the solution of the memory element read/write conflict of an embodiment of the present invention is described
Method includes：New memory module is set up, the memory module includes：Former memorizer, and increase on the basis of former memorizer
Plus least one set data register, the data storage for former memorizer occur read/write conflict when, interim storage number
According to；
Initial address pointer res is arranged to the data register；
If under the same clock cycle, to same data register address, being separately received reading request of data or receiving write
Request of data,
Then normal response reads request of data, and reads the corresponding data of current reading request address；
And normal response write request of data, and write data in Current Write Request address；
If under the same clock cycle, to same data register address, while receive reading request of data and write data please
Ask,
Then normal response reads request of data, and reads the corresponding data of current reading request address；
The write address of Current Write Request is mapped in current address pointer res places memory module, by current address
Pointer res is by being encoded to the write address of Current Write Request, and writes data into the data that the address pointer res is pointed to
On deposit address；
Meanwhile, it is new address pointer res by the current corresponding geocoding of reading of request of data that reads.
Used as the further improvement of an embodiment of the present invention, the width of the data register is set to deposit with the original
Reservoir width is identical, and depth is set to identical with the write port number of the former memorizer.
Used as the further improvement of an embodiment of the present invention, methods described is specifically included：
If the two neighboring clock cycle, receive the reading request of data to identical data register address and write data please
Ask；
Then after latter clock cycle, the pointer address of the memory module recovers the shape to before the previous clock cycle
State.
As the further improvement of an embodiment of the present invention, " write address of Current Write Request is mapped to current
In the memory module of address pointer res places " specifically include：
Arrange and address register group of the former memorizer with same even depth, the address register group is in former storage
When device occurs read/write conflict, the actual physical address of the former memorizer is stored.
Used as the further improvement of an embodiment of the present invention, methods described also includes：
Under present clock period, if receiving the reading request of data to same data register address and write request of data；
The address register group is then searched, the current physical address for reading request of data and write request of data matching is obtained；
According to the physical address for obtaining, its corresponding legacy data is read；
Meanwhile, new data are written in the address pointer res, and the correspondence renewal address register group physically
Location.
One of for achieving the above object, the solving device of the memory element read/write conflict of an embodiment of the present invention is described
Device includes：Memory module, the memory module include：Former memorizer, and increase at least on the basis of former memorizer
One group of data register, the data storage for former memorizer occur read/write conflict when, interim storage data；
Preset module, for arranging initial address pointer res to the data register；
Processing module, under the same clock cycle, to same data register address, be separately received reading request of data or
When receiving write request of data,
Normal response reads request of data, and reads the corresponding data of current reading request address；
And normal response write request of data, and write data in Current Write Request address；
Under the same clock cycle, to same data register address, while receiving reading request of data and write request of data
When,
Then normal response reads request of data, and reads the corresponding data of current reading request address；
The write address of Current Write Request is mapped in current address pointer res places memory module, by current address
Pointer res is by being encoded to the write address of Current Write Request, and writes data into the data that the address pointer res is pointed to
On deposit address；
Meanwhile, it is new address pointer res by the current corresponding geocoding of reading of request of data that reads.
Used as the further improvement of an embodiment of the present invention, the width of the data register is set to deposit with the original
Reservoir width is identical, and depth is set to identical with the write port number of the former memorizer.
As the further improvement of an embodiment of the present invention, the processing module specifically for：
The two neighboring clock cycle, receive the reading request of data to identical data register address and write request of data
When；
Then after latter clock cycle, the pointer address of the memory module recovers the shape to before the previous clock cycle
State.
Used as the further improvement of an embodiment of the present invention, the memory module also includes：With the former storage utensil
There is an address register group of same even depth, the address register group is for when former memorizer occurs read/write conflict, storing institute
State the actual physical address of former memorizer.
As the further improvement of an embodiment of the present invention, the processing module specifically for：
Under present clock period, if receiving the reading request of data to same data register address and write request of data；
The address register group is then searched, the current physical address for reading request of data and write request of data matching is obtained；
According to the physical address for obtaining, its corresponding legacy data is read；
Meanwhile, new data are written in the address pointer res, and the correspondence renewal address register group physically
Location.
Compared with prior art, the invention has the beneficial effects as follows：The solution of the memory element read/write conflict of the present invention
And device, it is used for the new data that interim storage will write by arranging a new data register, to ensure in read-write punching
When prominent, read request effectively can be read to walk old data, meanwhile, normal response write request；In addition the present invention is using a kind of new
The address pointer that interim storage writes data is ceaselessly changed by the mode of address of cache, can during meeting and read and write same address next time
Correctly to find the space at data place, it is independent of and any manufacturer, and does not affect access bandwidth, effectively solve storage
Need to read the application scenarios of old data during device read/write conflict, make chip Chevron Research Company (CRC) lack a kind of restriction when manufacturer is selected
Condition.
Description of the drawings
Fig. 1 is the flow chart of the solution of memory element read/write conflict in an embodiment of the present invention；
Fig. 2 is the module map of the solving device of memory element read/write conflict in an embodiment of the present invention
Fig. 3 is the structural representation of a specific example of the invention.
Specific embodiment
Describe the present invention below with reference to specific embodiment shown in the drawings.But these embodiments are simultaneously
The present invention is not limited, structure that one of ordinary skill in the art is made according to these embodiments, method or functionally
Conversion is all contained in protection scope of the present invention.
As shown in figure 1, in one embodiment of the present invention, the solution of memory element read/write conflict, including：
S1, new memory module is set up, the memory module includes：Former memorizer, and increase on the basis of former memorizer
Least one set data register, the data storage for former memorizer occur read/write conflict when, interim storage data；
The former memorizer is memory, it typically is n and reads m memory writes, for example：1 reads 1 memory write, 21 memory writes of reading
Deng；The data storage can be made up of d type flip flop；Here is not described in detail.
In a preferred implementation of the invention, the width of the data register is set to and the former memory width phase
Together, depth is set to identical with the write port number of the former memorizer.
In another preferred implementation of the present invention, read 1 memory write, the depth of the data register of setting for 1
Demand can be met for 1, by the introduction of the example below, it will be further understood by the present invention.
Further, methods described also includes：
S2, the address pointer res initial to data register setting.
In the specific embodiment of the invention, it is that the data register arranges an initial address pointer res；This is describedly
The sensing of location pointer res, can change with the read/write conflict of former memorizer, and in a certain proper time, return to
And initial address is pointed to, will below will be described in detail.
Further, methods described also includes：
If S31, under the same clock cycle, to same data register address, it is separately received reading request of data or receives
Write request of data；Then normal response reads request of data, and reads the corresponding data of current reading request address；And it is normal
Response write request of data, and write data in Current Write Request address；
If S32, under the same clock cycle, to same data register address, while receiving reading request of data and write number
According to request, then normal response reading request of data, and reading is current to read the corresponding data of request address；By Current Write Request
Write address be mapped in current address pointer res places memory module, by now address pointers res by coding become
The write address of Current Write Request, and write data on the data register address that the address pointer res is pointed to；Meanwhile,
It is new address pointer res by the current corresponding geocoding of reading of request of data that reads.
In the specific embodiment of the present invention, step S32 is specifically included：
If the two neighboring clock cycle, receive the reading request of data to identical data register address and write data please
Ask；Then after latter clock cycle, the pointer address of the memory module recovers the state to before the previous clock cycle.
It should be noted that in the specific implementation of the present invention, no matter rushing for whether former memorizer occurs read-write
Prominent,, when the reading for receiving data is asked, the reading of equal normal response data is asked, and the data of its response position are read for which
Go out；The present invention is mainly by the change of write address, it is to avoid under the same clock cycle, while receiving for same address
It is written and read the problem clashed during request.
The present invention is understood for convenience, below describes a concrete application example for understanding the present invention.
With reference to shown in Fig. 3, new memory module includes former memorizer and the data register for newly increasing, described when increasing
After data register, i.e., initial address pointer res is arranged to the data register；
Under first clock cycle, entry A receives reading request of data and write request of data simultaneously；Now, normal response
Request of data is read, corresponding data are read from entry A；Under the example, due under the same clock cycle, for original is deposited
The identical address of reservoir, is only capable of responding one of read or write request；Therefore, the number write by data storage interim storage
According to solve the read/write conflict of former memorizer.Accordingly, the write address of corresponding entry A is remapped so as to map to described
In the data register that address pointer res is currently located, specifically, by now address pointers res by being encoded to the ground of entry A
Location；And the data of request write entry A are written in the address pointer res of the data register；Meanwhile, the original is deposited
The geocoding of reservoir entry A is new address pointer res.
Under second clock cycle, entry A receives reading request of data and write request of data again simultaneously；Now,
Normal response reads request of data, from entry A of the data register reads data；By the write address weight of corresponding entry A
New mappings so as to map on the former memorizer that the address pointer res is currently located, specifically, by former memorizer current position
Location pointer res is by being encoded to the address of entry A；And the data of request write entry A are written to the ground of the former memorizer
In the pointer res of location；Meanwhile, the geocoding by entry A of the data register is new address pointer res.
Under 3rd clock cycle, entry A receives reading request of data and write request of data again simultaneously；The clock
Under cycle, the storage of data is identical with data storage method under the first clock cycle, and here does not continue to repeat.
Under 4th clock cycle, entry B receives reading request of data and write request of data simultaneously；Now, normally
Response reads request of data, from entry B of the former memorizer reads data；The write address of corresponding entry B is remapped,
Which is made to map on the former memorizer that the address pointer res is currently located, specifically, by former memorizer now address pointers
Res is by being encoded to the address of entry B；And the data of request write entry B are written to the address pointer of the former memorizer
In res；Meanwhile, the geocoding by entry B of the data register is new address pointer res.
Under 5th clock cycle, entry A receives reading request of data and write request of data again simultaneously；Now,
Normal response reads request of data, from entry A of the data register reads data；By the write address weight of corresponding entry A
New mappings so as to map on the former memorizer that the address pointer res is currently located, specifically, by former memorizer current position
Location pointer res is by being encoded to the address of entry A；And the data of request write entry A are written to the ground of the former memorizer
In the pointer res of location；Meanwhile, the geocoding by entry A of the data register is new address pointer res.
It should be noted that in the specific embodiment of the present invention, realizing that the mode of address of cache has various, here is not
Enumerate, in a preferred embodiment of the invention, the method for the mapping address includes：
Arrange and address register group of the former memorizer with same even depth, the address register group is in former storage
When device occurs read/write conflict, the actual physical address of the former memorizer is stored.
Further, step S32 is specifically included：
Under present clock period, if receiving the reading request of data to same data register address and write request of data；Then
The address register group is searched, the current physical address for reading request of data and write request of data matching is obtained；According to obtaining
The physical address for obtaining, reads its corresponding legacy data；Meanwhile, new data are written to into the address pointer res, and it is right
The physical address in the address register group should be updated.
As from the foregoing：The present invention is used for the new number that interim storage will write by arranging a new data register
According to ensure that read request can be read to walk old data, while interim storage is write data with a kind of mode of new address of cache
Address pointer ceaselessly change, with meet next time read and write same address when correctly can find data place space, together
When do not affect bandwidth.
With reference to shown in Fig. 2, the solving device of the memory element read/write conflict that an embodiment of the present invention is provided, described device
Including：Memory module 100, preset module 200, and processing module 300.Wherein, the memory module 100 includes：Former storage
Device 101, and the least one set data register 103 increased on the basis of former memorizer, the data storage 103 are used for
When there is read/write conflict in former memorizer 101, interim storage data；
The former memorizer 101 is memory, it typically is n and reads m memory writes, for example：11 memory write of reading, 2 are read 1 and write storage
Device etc.；The data storage 103 can be made up of d type flip flop；Here is not described in detail.
In a preferred implementation of the invention, the width of the data register 103 is set to and the former memorizer width
Spend 101 identical, depth is set to identical with the write port number of the former memorizer 101.
In another preferred implementation of the present invention, read 1 memory write, the depth of the data register 103 of setting for 1
Spend and demand can be met for 1, by the introduction of the example below, it will be further understood by the present invention.
Preset module 200 for arranging initial address pointer res to the data register 103.
In the specific embodiment of the invention, preset module 200 is that one initial address of the setting of the data register 103 refers to
Pin res；The sensing of the address pointer res, can change with the read/write conflict of former memorizer 101, and a certain
Proper time, returns to and points to initial address, will below will be described in detail.
Processing module 300 is for, under the same clock cycle, to same data register address, being separately received reading data
When asking or receive write request of data；Often response reads request of data, and reading currently reads the corresponding number of request address
According to；And normal response write request of data, and write data in Current Write Request address；
Under the same clock cycle, to same data register address, while receiving reading request of data and write request of data
When, normal response reads request of data, and reads the corresponding data of current reading request address；Current Write Request write ground
Location is mapped in current address pointer res places memory module, now address pointers res is become by coding and is currently write
Enter the write address of request, and write data on the data register address that the address pointer res is pointed to；Meanwhile, will be current
It is new address pointer res to read the corresponding geocoding of reading of request of data.
The present invention specific embodiment in, processing module 300 specifically for：The two neighboring clock cycle, it is right to receive
When the reading request of data and write request of data of identical data register address；Then after latter clock cycle, will be described
The pointer address of memory module recovers the state to before the previous clock cycle.
It should be noted that in the specific implementation of the present invention, no matter for whether former memorizer 101 occurs read-write
Conflict, its when the reading for receiving data is asked, the reading request of equal normal response data, and by the data of its response position
Read；The present invention is mainly by the change of write address, it is to avoid under the same clock cycle, while receiving for same
Location is written and read the problem clashed during request.
The present invention is understood for convenience, below describes a concrete application example for understanding the present invention.
With reference to shown in Fig. 3, new memory module includes former memorizer and the data register for newly increasing, described when increasing
After data register, i.e., initial address pointer res is arranged to the data register；
Under first clock cycle, entry A receives reading request of data and write request of data simultaneously；Now, normal response
Request of data is read, corresponding data are read from entry A；Under the example, due under the same clock cycle, for original is deposited
The identical address of reservoir, is only capable of responding one of read or write request；Therefore, the number write by data storage interim storage
According to solve the read/write conflict of former memorizer.Accordingly, the write address of corresponding entry A is remapped so as to map to described
In the data register that address pointer res is currently located, specifically, by now address pointers res by being encoded to the ground of entry A
Location；And the data of request write entry A are written in the address pointer res of the data register；Meanwhile, the original is deposited
The geocoding of reservoir entry A is new address pointer res.
Under second clock cycle, entry A receives reading request of data and write request of data again simultaneously；Now,
Normal response reads request of data, from entry A of the data register reads data；By the write address weight of corresponding entry A
New mappings so as to map on the former memorizer that the address pointer res is currently located, specifically, by former memorizer current position
Location pointer res is by being encoded to the address of entry A；And the data of request write entry A are written to the ground of the former memorizer
In the pointer res of location；Meanwhile, the geocoding by entry A of the data register is new address pointer res.
Under 3rd clock cycle, entry A receives reading request of data and write request of data again simultaneously；The clock
Under cycle, the storage of data is identical with data storage method under the first clock cycle, and here does not continue to repeat.
Under 4th clock cycle, entry B receives reading request of data and write request of data simultaneously；Now, normally
Response reads request of data, from entry B of the former memorizer reads data；The write address of corresponding entry B is remapped,
Which is made to map on the former memorizer that the address pointer res is currently located, specifically, by former memorizer now address pointers
Res is by being encoded to the address of entry B；And the data of request write entry B are written to the address pointer of the former memorizer
In res；Meanwhile, the geocoding by entry B of the data register is new address pointer res.
Under 5th clock cycle, entry A receives reading request of data and write request of data again simultaneously；Now,
Normal response reads request of data, from entry A of the data register reads data；By the write address weight of corresponding entry A
New mappings so as to map on the former memorizer that the address pointer res is currently located, specifically, by former memorizer current position
Location pointer res is by being encoded to the address of entry A；And the data of request write entry A are written to the ground of the former memorizer
In the pointer res of location；Meanwhile, the geocoding by entry A of the data register is new address pointer res.
In the specific embodiment of the present invention, the mode of processing modules implement address of cache has various, and here differs string
Lift, in a preferred embodiment of the invention, the memory module 100 also includes：Have with the former memorizer 101 equal deep
The address register group 105 of degree, the address register group 105 for former memorizer 101 occur read/write conflict when, store institute
State the actual physical address of former memorizer 101.
Accordingly, the processing module 300 is additionally operable to：Under present clock period, if receiving to same data register ground
The reading request of data and write request of data of location；The address register group 105 is then searched, current reading request of data is obtained
With the physical address of write request of data matching；According to the physical address for obtaining, its corresponding legacy data is read；Meanwhile,
New data are written to into the address pointer res, and correspondence updates the physical address in the address register group 105.
In sum, the solution and device of memory element read/write conflict of the invention, by arranging a new number
Be used for the new data that will write of interim storage according to depositor, with ensure read/write conflict when, read request effectively can be read to walk
Old data, meanwhile, normal response write request；Interim storage is write by the way of a kind of new address of cache by the present invention in addition
The address pointer of data ceaselessly changes, and the sky at data place can be correctly found during meeting and read and write same address next time
Between, it is independent of and any manufacturer, and does not affect access bandwidth, effectively solving needs to read old number when memory read/write conflicts
According to application scenarios, make chip Chevron Research Company (CRC) select manufacturer when lacked a kind of restrictive condition.
For convenience of description, it is divided into various modules with function when describing apparatus above to describe respectively.Certainly, implementing this
The function of each module can be realized in same or multiple softwares and/or hardware during invention.
Device embodiments described above are only schematic, wherein the module as separating component explanation
Can be or may not be physically separate, as the part that module shows can be or may not be physics mould
Block, you can local to be located at one, or can also be distributed on multiple mixed-media network modules mixed-medias.Which is selected according to the actual needs can
In some or all of module realizing the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property work in the case of, you can to understand and implement.
It should be understood that, although this specification is been described by according to embodiment, but not each embodiment only includes one
Individual independent technical scheme, this narrating mode of description is only that those skilled in the art will should say for clarity
Bright book as an entirety, the technical scheme in each embodiment can also Jing it is appropriately combined, forming those skilled in the art can
With the other embodiment for understanding.
The a series of detailed description of those listed above is only for the feasibility embodiment of the present invention specifically
Bright, they simultaneously are not used to limit the scope of the invention, all equivalent implementations made without departing from skill spirit of the present invention
Or change should be included within the scope of the present invention.
Claims (10)
1. a kind of solution of memory element read/write conflict, it is characterised in that methods described includes：
New memory module is set up, the memory module includes：Former memorizer, and increase on the basis of former memorizer to
Few one group of data register, the data storage for when there is read/write conflict in former memorizer, interim storage data；
Initial address pointer res is arranged to the data register；
If under the same clock cycle, to same data register address, being separately received reading request of data or receiving write
Request of data,
Then normal response reads request of data, and reads the corresponding data of current reading request address；
And normal response write request of data, and write data in Current Write Request address；
If under the same clock cycle, to same data register address, while receive reading request of data and write data please
Ask,
Then normal response reads request of data, and reads the corresponding data of current reading request address；
The write address of Current Write Request is mapped in current address pointer res places memory module, by current address
Pointer res is by being encoded to the write address of Current Write Request, and writes data into the data that the address pointer res is pointed to
On deposit address；
Meanwhile, it is new address pointer res by the current corresponding geocoding of reading of request of data that reads.
2. the solution of memory element read/write conflict according to claim 1, it is characterised in that
The width of the data register is set to identical with the former memory width, and depth is set to and the former memorizer
Write port number it is identical.
3. the solution of memory element read/write conflict according to claim 1, it is characterised in that methods described is specifically wrapped
Include：
If the two neighboring clock cycle, receive the reading request of data to identical data register address and write data please
Ask；
Then after latter clock cycle, the pointer address of the memory module recovers the shape to before the previous clock cycle
State.
4. the solution of memory element read/write conflict according to claim 1, it is characterised in that " by it is presently written please
The write address asked is mapped in current address pointer res places memory module " specifically include：
Arrange and address register group of the former memorizer with same even depth, the address register group is in former storage
When device occurs read/write conflict, the actual physical address of the former memorizer is stored.
5. the solution of memory element read/write conflict according to claim 4, it is characterised in that methods described is also wrapped
Include：
Under present clock period, if receiving the reading request of data to same data register address and write request of data；
The address register group is then searched, the current physical address for reading request of data and write request of data matching is obtained；
According to the physical address for obtaining, its corresponding legacy data is read；
Meanwhile, new data are written in the address pointer res, and the correspondence renewal address register group physically
Location.
6. a kind of solving device of memory element read/write conflict, it is characterised in that described device includes：
Memory module, the memory module include：Former memorizer, and the least one set number increased on the basis of former memorizer
According to depositor, the data storage for former memorizer occur read/write conflict when, interim storage data；
Preset module, for arranging initial address pointer res to the data register；
Processing module, under the same clock cycle, to same data register address, be separately received reading request of data or
When receiving write request of data,
Normal response reads request of data, and reads the corresponding data of current reading request address；
And normal response write request of data, and write data in Current Write Request address；
Under the same clock cycle, to same data register address, while receiving reading request of data and write request of data
When,
Then normal response reads request of data, and reads the corresponding data of current reading request address；
The write address of Current Write Request is mapped in current address pointer res places memory module, by current address
Pointer res is by being encoded to the write address of Current Write Request, and writes data into the data that the address pointer res is pointed to
On deposit address；
Meanwhile, it is new address pointer res by the current corresponding geocoding of reading of request of data that reads.
7. the solving device of memory element read/write conflict according to claim 6, it is characterised in that the data register
Width be set to identical with the former memory width, depth is set to identical with the write port number of the former memorizer.
8. the solving device of memory element read/write conflict according to claim 6, it is characterised in that the processing module tool
Body is used for：
The two neighboring clock cycle, receive the reading request of data to identical data register address and write request of data
When；
Then after latter clock cycle, the pointer address of the memory module is recovered into the shape to before the previous clock cycle
State.
9. the solving device of memory element read/write conflict according to claim 6, it is characterised in that
The memory module also includes：With address register group of the former memorizer with same even depth, the address deposit
Device group is for when former memorizer occurs read/write conflict, storing the actual physical address of the former memorizer.
10. the solving device of memory element read/write conflict according to claim 9, it is characterised in that
The processing module specifically for：
Under present clock period, if receiving the reading request of data to same data register address and write request of data；
The address register group is then searched, the current physical address for reading request of data and write request of data matching is obtained；
According to the physical address for obtaining, its corresponding legacy data is read；
Meanwhile, new data are written in the address pointer res, and the correspondence renewal address register group physically
Location.
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| CN117407321A (en) * | 2023-12-13 | 2024-01-16 | 井芯微电子技术(天津)有限公司 | Read-write request processing method and related device for chip cache |
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