CN108566196A - A kind of cmos driver applied to the control of output signal slew rate - Google Patents
A kind of cmos driver applied to the control of output signal slew rate Download PDFInfo
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- CN108566196A CN108566196A CN201810344436.0A CN201810344436A CN108566196A CN 108566196 A CN108566196 A CN 108566196A CN 201810344436 A CN201810344436 A CN 201810344436A CN 108566196 A CN108566196 A CN 108566196A
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- signal
- delay
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- slew rate
- phase
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
Abstract
The present invention discloses a kind of cmos driver applied to the control of output signal slew rate, which is characterized in that including sequentially connected delay phase-locked loop DLL, sample circuit DFFs and driving circuit driver；Delay phase-locked loop includes sequentially connected phase frequency detector PFD, charge pump circuit CP, loop low pass filter LPF and voltage control delay circuit VCDL.Compared with typical output signal slew rate control output driver, the slew rate control of the present invention using delay phase-locked loop equal time delayed signals, under the influence of PVT changes, when delay phase-locked loop locks, the delay at equal intervals that the phase signal clock of delay locked loop is kept constant, constant time delayed signal is reused to be overlapped, obtain a constant slew rate signal, the driving capability of output driver is controlled because of process deviation so as to improve traditional triple gate slew rate, operating ambient temperature changes and supply voltage changes and generates large effect, the shortcomings that causing output signal slew rate to generate larger change.
Description
Technical field
The invention belongs to technical field of integrated circuits, more particularly to a kind of CMOS applied to the control of output signal slew rate
Driver.
Background technology
The output signal slew rate of driver and the circuit structure of driver, load characteristic, process deviation, working environment temperature
Degree changes related to factors such as supply voltage variations.According to the analysis to signal spectrum, it is known that the rate of signal intensity is got over
Soon, including high fdrequency component energy it is bigger, reduce transmission signal slew rate, can substantially reduce contained in signal
High fdrequency component energy and radiation intensity, to effectively reduce electromagnetic crosstalk caused by signal radiation.And with current institute
The fast lifting of transmission data rate, electromagnetic crosstalk caused by the output signal radio-frequency component of driver and electromagnetic compatibility problem are more
Seriously, it solves electromagnetic interference and is increasingly becoming the faced significant challenge of driver design.Therefore, in design output signal slew rate
When controlling driver, it is necessary to take measures, under the premise of ensureing transmission rate, reduce output signal slew rate.
Traditional slew rate control output driver is as shown in Figure 1, slew rate controls output driver by tri-state in Fig. 1
Door, slew rate output pre-driver and cmos driver three parts composition.The structure is in process deviation, temperature change and confession
Piezoelectric voltage changes under the influence of (Process, Voltage, Temperature, PVT), the phase inverter of predrive and driver
The driving capability of CMOS inverter generates larger variation, also has greatly changed so as to cause slew rate.
Invention content
The purpose of the present invention is to provide a kind of cmos drivers applied to the control of output signal slew rate, to solve to pass
Output signal slew rate of uniting controls driver under the influence of process deviation, operating ambient temperature variation and supply voltage change,
Driving capability changes greatly the problem of causing output signal slew rate to vary widely.Cmos driver of the present invention, Ke Yiyou
Effect ground reduces the raising and lowering speed of output signal hopping edge, and the raising and lowering speed of output signal hopping edge is made to exist
It changes in smaller range under the influence of PVT, realizes the control of output signal slew rate.
To achieve the goals above, one's duty is bought that and is adopted the following technical scheme that：
A kind of cmos driver applied to the control of output signal slew rate, which is characterized in that prolong including sequentially connected
Slow phaselocked loop DLL, sample circuit DFFs and driving circuit driver；Delay phase-locked loop includes sequentially connected phase frequency detector
PFD, charge pump circuit CP, loop low pass filter LPF and voltage control delay circuit VCDL.
Further, two input terminals of phase frequency detector PFD are separately connected reference clock signal CLK and voltage control delay line
The clock signal of circuit VCDL afterbodies output, exports the phase signal between two clock signals；Phase frequency detector
The input terminal of the output end connection charge pump circuit CP of PFD；Charge pump circuit CP is made of biasing circuit and switching circuit, is used for
Convert the phase frequency detector PFD phase signals exported to charging and discharging currents signal；The output end of charge pump circuit CP connects
The input terminal of loop low pass filter LPF；The input of loop low pass filter LPF is the charge and discharge electricity of charge pump circuit CP outputs
Signal is flowed, output voltage signal is converted into；The output end connection voltage control delay circuit VCDL's of loop low pass filter LPF
Input terminal；Voltage control delay line circuit VCDL is made of 32 phase delay units, is inputted as reference clock signal CLK, while by
32 phase delay units of voltage signal of loop low pass filter LPF are controlled, export for 32 equiphase intervals when
Clock signal, and several wherein adjacent equiphase interval timer signals of selection export and give sample circuit DFFs.
Further, several equiphase interval timer signals are specially 8.
Further, sample circuit DFFs is made of several triggers DFF, inputs the phases such as 32 for delay locked loop
The data-signal DATA of several adjacent clock signals and pseudo-random generator in bit interval clock signal, when several are adjacent
Clock signal samples pseudo-random generator data-signal DATA to obtain the defeated of several equal delays by corresponding to trigger DFF
Go out data-signal；The outputting data signals of this several equal delay, which export, gives driving circuit driver.
Further, driving circuit driver is made of 24 CMOS buffers, and each buffer size is identical, provides phase
Same delay.
Further, the outputting data signals of two groups of different equal delays are superimposed by driving circuit driver, and what is obtained is defeated
Go out signal to export to load.
Further, the data-signal DATA of pseudo-random generator generates several etc. after over-sampling circuit DFFs and prolongs
When signal, this several equal time delayed signals are overlapped, and obtain signal POUT1, then signal POUT1 is obtained into line delay
Signal POUT2, then signal POUT2 and signal POUT1 are overlapped, it obtains output signal and exports to load.
Compared with the existing technology, the invention has the advantages that：
Compared with typical output signal slew rate control output driver, slew rate of the invention control is using delay
The equal time delayed signals of phaselocked loop, under the influence of PVT changes, when delay phase-locked loop locks, the phase signal of delay locked loop
The delay at equal intervals that clock is kept constant reuses constant time delayed signal and is overlapped, and obtains a constant slew rate letter
Number, the driving capability of output driver is controlled because of process deviation, working environment temperature so as to improve traditional triple gate slew rate
The shortcomings that degree variation and supply voltage change and generate large effect, output signal slew rate is caused to generate larger change.
Description of the drawings
Fig. 1 is that traditional triple gate exports the structural schematic diagram that slew rate controls driver；
Fig. 2 is a kind of structural schematic diagram of cmos driver applied to the control of output signal slew rate of the present invention；
Fig. 3 is the structural schematic diagram of delay locked loop circuit (DLL) of the present invention；
Fig. 4 is the structural schematic diagram of sample circuit of the present invention (DFFs)；
Fig. 5 is output driver schematic diagram (drivers) of the present invention；
Fig. 6 is the realization principle figure of output signal of the present invention superposition；Wherein, the signal in Fig. 6 A is the input number in Fig. 2
According to DATA signal；Fig. 6 B are 8 signals for waiting delays that the signal of Fig. 6 A generates after over-sampling circuit；Fig. 6 C are in Fig. 6 B
The signal POUT1 that the signal of 8 equal delays is overlapped；Fig. 6 D are that the signal in Fig. 6 C is delayed to obtain signal
POUT2。
Specific implementation mode
Objects and advantages in order to better illustrate the present invention are with reference to the accompanying drawings and examples made the present invention further
Explanation.
Change with PVT for traditional triple gate output signal slew rate control driver, driving capability occurs larger
The problem of changing, output signal slew rate caused to vary widely.The present invention devises a kind of applied to output signal pressure pendulum
The cmos driver of rate control, driving capability do not change with process deviation, operating ambient temperature and supply voltage, and the present invention adopts
It is generated not with the equal time delayed signals of PVT variations with delay locked loop, recycles the signal of 8 equal delays to be overlapped average, in fact
The raising and lowering constant airspeed of existing output signal hopping edge generates and does not change and supply with process deviation, operating ambient temperature
The output slew rate signal of piezoelectric voltage variation.
Below with Fig. 2 slew rate output drivers, the principle of stacking of Fig. 5 driving circuits and Fig. 6 output signals of the present invention is
Basis, the cmos driver applied to the control of output signal slew rate a kind of to the present invention are further described.
It please refers to shown in Fig. 2, a kind of cmos driver applied to the control of output signal slew rate of the present invention, mainly by prolonging
Slow phaselocked loop DLL, sample circuit DFFs and driving circuit driver compositions.
It please refers to shown in Fig. 2 and Fig. 3, delay phase-locked loop includes phase frequency detector PFD, charge pump circuit CP, loop low pass
Filter LPF and voltage control delay circuit VCDL；
Two input terminals of phase frequency detector PFD are separately connected reference clock signal CLK and voltage control delay line circuit VCDL
The clock signal of afterbody output, exports the phase signal between two clock signals；The output of phase frequency detector PFD
The input terminal of end connection charge pump circuit CP, charge pump circuit CP is made of biasing circuit and switching circuit, by phase frequency detector
The phase signal of PFD outputs is converted into charging and discharging currents signal；The output end linkloop low-pass filtering of charge pump circuit CP
The input terminal of device LPF, the input of loop low pass filter LPF is the charging and discharging currents signal of charge pump circuit CP outputs, by it
Be converted to output voltage signal；The input terminal of the output end connection voltage control delay circuit VCDL of loop low pass filter LPF, it is voltage-controlled
Delay line circuit VCDL is made of 32 phase delay units, is inputted for reference clock signal CLK, while by loop low pass wave
32 phase delay units of voltage signal of device LPF are controlled, and are exported as the clock signal at 32 equiphase intervals, and choose
Sample circuit DFFs is given in wherein adjacent (equally spaced multiple) outputs of 8 equiphase interval timers signal.
It please refers to shown in Fig. 4, sample circuit DFFs is made of 8 trigger DFF, and it is 32 etc. of delay locked loop to input
The data-signal DATA of 8 adjacent clock signals and pseudo-random generator in phase intervals clock signal, 8 adjacent clock letters
Number pseudo-random generator data-signal DATA is sampled by corresponding trigger DFF to obtain the output datas of 8 equal delays
Signal；The outputting data signals of this 8 equal delays, which export, gives driving circuit driver.
It please referring to shown in Fig. 5, driving circuit driver is made of 24 CMOS buffers, and each buffer size is identical,
Identical delay is provided；(8 equal time delayed signals P1-P8 fold this 8 output signals respectively by 8 buffer1
Add, after superposition the equal delays of P1-P8 cause 8 buffer1 to sequentially turn on/turn off in the case where waiting delay, the hopping edge of output signal
Gradually rise/fall during saltus step obtains (and the stairstepping signals shown in Fig. 6 of output signal POUT1 in Fig. 5
POUT1)；Equally, 8 equal time delayed signals P1-P8 pass through 8 buffer2 and 8 buffer3 respectively, and this 8 outputs are believed
Number short circuit superposition, there are one obtained output signal POUT2 (and stairstepping signal POUT2 shown in Fig. 6) has relative to POUT1
The delay of buffer2, thus output signal POUT1 and output signal POUT2 form complementary stairstepping signal as shown in Figure 6 D,
Stairstepping signal POUT1 and POUT2 are superimposed again, obtain output signal POUT (the rise/fall jumps in namely Fig. 6 in Fig. 5
Become the output signal POUT along rate uniform).The slew rate of the signal mainly determines by the delay of equal time delayed signals P1-P8, because
And the slew rate of output signal POUT by process deviation, operating ambient temperature and supply voltage variation influenced it is smaller.) present invention
A kind of realization of cmos driver applied to the control of output signal slew rate is defeated based on multiple adjacent time delays to data-signal
Go out signal and be overlapped average principle, as shown in Figure 6.Signal in Fig. 6 A is the input data DATA signal in Fig. 2, is passed through
The signal (x8 signals after DFFS in Fig. 2) of 8 equal delays of Fig. 6 B is generated after sample circuit, this 8 are waited time delayed signals, that is, are schemed
The input signal P1-P8 of 5 output drivers；The signal of this 8 equal delays is recycled to be overlapped, to obtain the letter in Fig. 6 C
Number POUT1 (and output signal POUT1 of Fig. 5 driving circuits), the signal hopping edge saltus step after being as can be seen from the figure superimposed
Speed slows down, and slew rate reduces, but the hopping edge of the signal is stepped signal, is still not able to meet the requirements, then should
Signal has obtained the signal POUT2 (namely output signal POUT2 of Fig. 5 driving circuits) in Fig. 6 D into line delay, then by the letter
Number POUT2 and original signal POUT1 is overlapped, and obtains the signal of more hopping edge saltus step constant airspeed, is wanted to meet
It asks.
Circuit is under the influence of PVT changes, and due to the negative feedback structure of delay locked loop, the input signal of driving circuit begins
It keeps constant eventually namely P1-P8 signals does not change always with the influence of PVT, it will be appreciated from fig. 6 that driver output signal POUT
Driving capability of the rise/fall speed of hopping edge depending on the delay time and driving circuit (driver) of P1-P8, driving electricity
The driving capability on road causes the variation of rise/fall time far below the summation of 8 delay times, thus final output signal
Hopping edge rate depends primarily on the delay of input signal.Due to the frequency and constant phase difference of delay phase-locked loop output signal,
So the output signal slew rate variation of output signal slew rate control driving is very small.
In above structure, the principle based on Signal averaging effectively improves traditional output signal slew rate control letter
Under the influence of PVT changes, the problem of larger change causes slew rate to vary widely occurs for driving capability for number driver.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (6)
1. a kind of cmos driver applied to the control of output signal slew rate, which is characterized in that including sequentially connected delay
Phaselocked loop DLL, sample circuit DFFs and driving circuit driver；Delay phase-locked loop include sequentially connected phase frequency detector PFD,
Charge pump circuit CP, loop low pass filter LPF and voltage control delay circuit VCDL.
2. a kind of cmos driver applied to the control of output signal slew rate according to claim 1, which is characterized in that
Two input terminals of phase frequency detector PFD are separately connected reference clock signal CLK and voltage control delay line circuit VCDL is last
The clock signal of level-one output, exports the phase signal between two clock signals；The output end of phase frequency detector PFD connects
Connect the input terminal of charge pump circuit CP；
Charge pump circuit CP is made of biasing circuit and switching circuit, the phase signal for exporting phase frequency detector PFD
It is converted into charging and discharging currents signal；The input terminal of the output end linkloop low-pass filter LPF of charge pump circuit CP；
The input of loop low pass filter LPF is the charging and discharging currents signal of charge pump circuit CP outputs, is converted into output
Voltage signal；The input terminal of the output end connection voltage control delay circuit VCDL of loop low pass filter LPF；
Voltage control delay line circuit VCDL is made of 32 phase delay units, is inputted for reference clock signal CLK, while by loop
32 phase delay units of voltage signal of low-pass filter LPF are controlled, and the clock letter for 32 equiphase intervals is exported
Number, and several wherein adjacent equiphase interval timer signals of selection export and give sample circuit DFFs.
3. a kind of cmos driver applied to the control of output signal slew rate according to claim 2, which is characterized in that
Several equiphase interval timer signals are specially 8.
4. a kind of cmos driver applied to the control of output signal slew rate according to claim 2, which is characterized in that
Sample circuit DFFs is made of several triggers DFF, is inputted in 32 equiphase interval timer signals for delay locked loop
Several adjacent clock signals and pseudo-random generator data-signal DATA, several adjacent clock signals pass through corresponding touch
Hair device DFF samples pseudo-random generator data-signal DATA to obtain several outputting data signals for waiting delays；If this
The outputting data signals of dry a equal delays, which export, gives driving circuit driver.
5. a kind of cmos driver applied to the control of output signal slew rate according to claim 4, which is characterized in that
Driving circuit driver is made of 24 CMOS buffers, and each buffer size is identical, provides identical delay.
6. a kind of cmos driver applied to the control of output signal slew rate according to claim 5, which is characterized in that
The data-signal DATA of pseudo-random generator generates the signal of several equal delays after over-sampling circuit DFFs, this several
Equal time delayed signals are overlapped, and obtain signal POUT1, then by signal POUT1 into line delay, obtain signal POUT2, then by signal
POUT2 and signal POUT1 are overlapped, and are obtained output signal and are exported to load.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810344436.0A CN108566196B (en) | 2018-04-17 | 2018-04-17 | CMOS driver applied to output signal slew rate control |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810344436.0A CN108566196B (en) | 2018-04-17 | 2018-04-17 | CMOS driver applied to output signal slew rate control |
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| CN108566196B CN108566196B (en) | 2020-07-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2342827B1 (en) * | 2008-10-20 | 2012-07-18 | Telefonaktiebolaget L M Ericsson (PUBL) | Low power linear interpolation digital-to-analog conversion |
| CN102651647A (en) * | 2011-02-23 | 2012-08-29 | 联咏科技股份有限公司 | Delay lock loop and clock pulse signal generation method |
| CN105553449A (en) * | 2015-12-31 | 2016-05-04 | 苏州芯动科技有限公司 | Slew rate self-calibration driving circuit, drive slew rate calibration circuit and calibration method thereof |
-
2018
- 2018-04-17 CN CN201810344436.0A patent/CN108566196B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2342827B1 (en) * | 2008-10-20 | 2012-07-18 | Telefonaktiebolaget L M Ericsson (PUBL) | Low power linear interpolation digital-to-analog conversion |
| CN102651647A (en) * | 2011-02-23 | 2012-08-29 | 联咏科技股份有限公司 | Delay lock loop and clock pulse signal generation method |
| CN105553449A (en) * | 2015-12-31 | 2016-05-04 | 苏州芯动科技有限公司 | Slew rate self-calibration driving circuit, drive slew rate calibration circuit and calibration method thereof |
Non-Patent Citations (3)
| Title |
|---|
| ROBERT CHEN-HAO CHANG: "A Multiphas-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I:REGULAR PAPERS》 * |
| SOON-KYUN SHIN, SEOK-MIN JUNG, JIN-HO SEO等: "A Slew-Rate Controlled Output Driver Using", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
| YOUNG-HO KWAK,INHWA JUNG,CHULWOO KIM: "A Gb/s+ Slew-Rate/Impedance-Controlled Output", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II:EXPRESS BRIEFS》 * |
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| CN108566196B (en) | 2020-07-28 |
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