CN108565214A - A kind of method that PDMS macking techniques prepare silicon slot - Google Patents

A kind of method that PDMS macking techniques prepare silicon slot Download PDF

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Publication number
CN108565214A
CN108565214A CN201810337391.4A CN201810337391A CN108565214A CN 108565214 A CN108565214 A CN 108565214A CN 201810337391 A CN201810337391 A CN 201810337391A CN 108565214 A CN108565214 A CN 108565214A
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pdms
silicon chip
chip substrate
silicon
photosensitive
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CN108565214B (en
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邹赫麟
王秋森
黎晨
杨正
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Dalian University of Technology
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Dalian University of Technology
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Materials For Photolithography (AREA)

Abstract

The invention belongs to field of semiconductor fabrication processes, are related to a kind of method that PDMS macking techniques prepare silicon slot.Step includes:Prepare silicon chip substrate, etching silicon slot and removal masking layer with PDMS masking layers;In the photosensitive PDMS of positive spin coating of silicon chip substrate, intermittent exposure is carried out using mask, rear to dry solidification, the photosensitive unexposed parts PDMS are cured, and photosensitive PDMS exposed portions keep original state;Uncured PDMS is removed with toluene soak;Substrate is rinsed well with isopropanol, after dried up with nitrogen, complete masking layer it is graphical;In silicon chip backside of substrate spin coating non-photosensitivity PDMS, drying;Silicon chip substrate is put into 35% 45% KOH solution and is etched;The silicon chip substrate that etching is completed is put into the concentrated sulfuric acid and boils removal masking layer, obtains silicon slot.The present invention prepares silicon slot using PDMS as masking layer, and manufacture craft is simple, at low cost, good process repeatability, and easy to implement.

Description

A kind of method that PDMS macking techniques prepare silicon slot
Technical field
The invention belongs to field of semiconductor fabrication processes, are related to a kind of method that PDMS macking techniques prepare silicon slot.
Background technology
PDMS (polydimethylsiloxane), abbreviation organosilicon are the english abbreviations of dimethyl silicone polymer, at This is low, using simple, with having good adhesiveness between silicon chip, moreover, the chemical state dimethyl of dimethyl silicone polymer Silicone oil, colourless or light yellow liquid is tasteless, and transparency is high, and there is heat resistance, cold resistance, viscosity to vary with temperature small, surface It is light transmittance 100% that power is small, has thermal conductivity, thermal coefficient 0.134-0.159W/M*K, translucency, and dimethicone is nontoxic It is tasteless, there is physiological inertia, good chemical stability.Electrical insulating property and weatherability, hydrophobicity are good, and have very high shearing resistance Ability is cut, can be used for a long time at -50 DEG C~200 DEG C.With excellent physical characteristic, damp proof insulation is can be directly used for, is damped, Damping defoams, lubrication, polishing etc., is widely used as insulation lubrication, shockproof, grease proofing dirt, dielectric liquid and heat carrier.Except this it Outside, defoaming, releasing agent, paint and chemical product additive are also acted as.Dimethyl silicone polymer (PDMS) is most widely used Organic polymer material based on silicon, be included in micro sprue system in bio-microelectromechanical, gap filler, lubricant, Contact lenses become a kind of polymer material being widely used in micro-fluidic equal fields.
Wet chemical etching technique is the processing method manufactured earliest for micro mechanical structure.So-called wet etching, being exactly will be brilliant Piece, which is placed in the chemical corrosion liquid of liquid, to be corroded, in corrosion process, passing through of material that corrosive liquid will contact it Learning reaction, gradually etch dissolves away.There are many reagent for chemical attack, there is sour corrosion agent, alkaline corrosion agent and organic corrosion Agent etc..According to selected corrosive agent, and isotropic etch and anisotropic etchant can be divided into.The examination of isotropic etch There are many agent, including various salts (such as CN bases, NH yls) and acid, but due to by can obtain high purity reagent, and wish Avoid the limitation for staining the two factors of metal ion, therefore widely used HF-HNO3 etching systems.Anisotropic etch is Refer to has different corrosion rates to the different crystal faces of silicon.Based on this etching characteristic, can process on a silicon substrate various each The micro-structure of sample.Anisotropic etchant is generally divided into two classes, and one kind is organic corrosion agent, including EPW (ethylenediamine, adjacent benzene two Phenol and water) and diamine etc., another kind of is inorganic corrosion agent, including alkaline corrosion liquid, such as KOH, NaOH, NH4OH.
Integrated circuit in the special process of semiconductor manufacturing, such as in process for fabrication of semiconductor device, generally requires The chip of specific thicknesses (main component is silicon (Si)) is worked into certain depth, or corrosion using wet method deep silicon etch liquid To specific remaining thicknesses of layers, this just needs to implement deep etching technique.
Deep etching technique need longer process time and deeper etching depth (depth can reach hundreds of microns, Chip residual thickness after even up to 500 microns or more, or corrosion is less than 20 microns).In the prior art, generally use Wet processing carries out zanjon etching, this is just needed using the materials such as silica (SiO2) and silicon nitride (Si3N4) as masking Layer has protective effect when masking layer carries out deep plough groove etched technique to wafer silicon substrate, and deep plough groove etched technique is with masking layer For mask specific thicknesses, type disk on realize the transfer of figure, to etching required deep trench on disk.
But use silica and silicon nitride as masking layer, often cost is higher, cannot be removed after etching technics dry Only, it causes wafer to damage, leads to fragment, other follow-up techniques are had an impact.Therefore, a kind of covering for low cost is developed Covering technology becomes deep plough groove etched technical field urgent problem to be solved.
Invention content
To solve the above problems, the present invention provides a kind of method that PDMS macking techniques prepare silicon slot.
Technical scheme of the present invention:
A kind of method that PDMS macking techniques prepare silicon slot, includes the following steps:
(1) the silicon chip substrate with PDMS masking layers is prepared
(1.1) it is 5-15 according to volume ratio by PDMS matrixes and curing agent:1 mixing, goes bubble to handle, and is formed containing solidification The PDMS intermixtures of agent, as non-photosensitivity PDMS;
(1.2) by Benzophenone dissolution of crystals in dimethylbenzene, Benzophenone solution, a concentration of 0.1-50g/ of Benzophenone are formed ml;Non-photosensitivity PDMS and Benzophenone the solution mixing that step (1.1) is obtained, wherein the quality of non-photosensitivity PDMS and Benzophenone Than for 30-40:1, incorporation time 10-20 minutes forms the PDMS mixed solutions to ultraviolet-sensitive, as photosensitive PDMS;
(1.3) the photosensitive PDMS that step (1.2) obtains is spin-coated on a surface of silicon chip substrate, as front, just The thickness of photosensitive PDMS on face is 0.1-2000um;The one side of the non-photosensitive PDMS of spin coating is as the back side;Using mask to silicon chip The front of substrate is exposed, the ultraviolet wavelength of exposure<365nm, light exposure 95-400mJ/cm2
(1.4) 10-240min is dried after by the silicon chip substrate after exposure at 85-120 DEG C of temperature, rear purpose of drying is to cure not The PDMS of exposure, the photosensitive unexposed parts PDMS are cured, and photosensitive PDMS exposed portions keep original state;It will be uncured Photosensitive PDMS is removed for 3-5 seconds with toluene soak;Silicon chip substrate is rinsed with isopropanol, isopropanol is dried up with nitrogen;Again by silicon chip base Bottom is dried, and the temperature of drying is 80-120 DEG C, time 5min-6h;Complete the graphical of masking layer;
(1.5) non-photosensitivity PDMS is spin-coated on to the back side of silicon chip substrate, the thickness of the non-photosensitivity PDMS on the back side is 0.1- 2000um;Non-photosensitivity PDMS is dried again, the temperature of drying is 80-120 DEG C, time 5min-6h;Complete silicon chip backside of substrate The preparation of masking layer obtains the silicon chip substrate with PDMS masking layers;
(2) silicon slot is etched
(2.1) KOH is mixed with deionized water, obtains the KOH solution that mass fraction is 35%-45%, isopropanol is added Hydrogen is inhibited to generate;By the face-up of silicon chip substrate, inclination is put into KOH solution;Add in 80-90 DEG C of oil bath or water-bath Heat;
(2.2) silicon chip substrate is taken out every 1h-2h, removes the PDMS for playing glue in silicon chip substrate and corrosion raffinate, makes again Standby PDMS masking layers, continue to etch;Repeat step (1.3), (1.4), (1.5) and (2.1);After the completion of etching, silicon chip base is taken out Bottom washes off the etching raffinate in silicon chip substrate with deionized water;
(3) masking layer is removed
The silicon chip substrate that etching is completed is put into the concentrated sulfuric acid and is heated to boiling, stops heating, it is cooling;Silicon chip substrate is taken Go out, remove remnants PDMS masking layers, be washed with deionized water only, drying obtains silicon slot.
The parameter of the spin coating is 600 revs/min, time 9s of low speed, 1000 revs/min of high speed, time 30s.
The described mode for going bubble to handle be centrifuge remove, vacuumize, mix slowly in one or more combinations;It is excellent Choosing removes bubble removing using vacuumize process, the vacuumize process 5-15min at 40-300Pa, to completely remove in PDMS solution Bubble.
Beneficial effects of the present invention:PDMS masking layers prepared by the present invention have adhesive capacity, are without binder It can directly attach and combine with silicon chip, simple for process as wet etching masking layer using the PDMS masking layers, cost is relatively low and right Silicon chip has good protective effect.
Description of the drawings
Fig. 1 is the preparation technology figure of the photosensitive PDMS layer of the embodiment of the present invention;
Fig. 2 is the preparation technology flow chart a of the silicon slot of the embodiment of the present invention;
Fig. 3 is the preparation technology flow chart b of the silicon slot of the embodiment of the present invention;
Fig. 4 is the preparation technology flow chart c of the silicon slot of the embodiment of the present invention;
Fig. 5 is the preparation technology flow chart d of the silicon slot of the embodiment of the present invention;
Fig. 6 is the preparation technology flow chart e of the silicon slot of the embodiment of the present invention;
Fig. 7 is the preparation technology flow chart f of the silicon slot of the embodiment of the present invention;
In figure:1 photosensitive PDMS layer;2 silicon chip substrates;3 masks;4 unexposed photosensitive PDMS layers;The photosensitive PDMS of 5 exposures Layer;6 non-photosensitivity PDMS layers;7 silicon slots;8 carve the silicon chip of silicon slot.
Specific implementation mode
Below in conjunction with attached drawing and technical solution, the specific implementation mode that further illustrates the present invention.
Embodiment 1
As shown in Figure 1, the preparation method with photosensitive PDMS layer of the present embodiment, includes the following steps:
1, the substrate of PDMS masking layers is prepared
After being cleaned up silicon chip substrate 2 with deionized water, heat to remove moisture removal;
10 are pressed by PDMS matrixes and curing agent:1 is mixed to form PDMS intermixtures, after stirring evenly, in the lower pumpings of 50Pa or so 6min or so is vacuum-treated to remove the bubble in PDMS solution, this intermixture is referred to as non-photosensitivity PDMS;By Benzophenone crystalline substance Body is dissolved in dimethylbenzene, forms Benzophenone solution;Non-photosensitivity PDMS and Benzophenone press 33:1 mass ratio mixes, and incorporation time 15 is divided Clock forms the PDMS solution to ultraviolet-sensitive, after stirring evenly, in lower vacuumize process 6min of 50Pa or so or so;This Kind mixed liquor is referred to as photosensitive PDMS;
By photosensitive PDMS obtained with 600 revs/min, time 9s of low speed, 1000 revs/min of high speed, the spin coating of time 30s Parameter is spin-coated on 2 upper side of silicon chip substrate, and then in lower vacuumize process 6min of 50Pa or so or so, repetition is above-mentioned to vacuumize place Reason, until the photosensitive PDMS in silicon chip substrate 2 does not have bubble;
As shown in figure 3, carrying out intermittent exposure to unexposed photosensitive PDMS layer 1 using mask 3, wherein light exposure is 120mJ/cm2, exposing clearance is 1 μm or so;
240min or so is heated at 85 DEG C or so, so that unexposed PDMS layer 4 is cured, the PDMS layer 5 of exposure is made to keep Original state;Uncured PDMS is removed for 3-5 seconds with toluene soak;Substrate is rinsed well with isopropanol, after blown with nitrogen Dry isopropanol;Substrate is dried again.
By non-photosensitivity PDMS obtained with low speed 600r/min, time 9s, high speed 1000r/min, the spin coating of time 30s is joined Number is spin-coated on 2 downside of silicon chip substrate, and then in lower vacuumize process 6min of 50Pa or so or so, repetition is above-mentioned to vacuumize place Reason, until the non-photosensitivity PDMS layer 6 of 2 downside of silicon chip substrate does not have bubble;Obtain the silicon chip substrate 2 with PDMS layer 6 (as shown in Figure 5).
2, silicon slot is etched
By KOH and water in mass ratio 4:The KOH solution that 6 mixed preparing mass fractions are 40% is added isopropanol and inhibits hydrogen Gas generates, and prepared KOH solution is poured into beaker, a glass bar is put into and leans to beaker, by the photosensitive PDMS of silicon chip spin coating One side upward, lean to glass bar and be put into.Beaker is subjected to 85 DEG C of oil baths or heating water bath, to prevent silicon chip structural region PDMS Glue is played, silicon chip substrate is taken out every 2h, PDMS and corrosion raffinate that glue is played in non-structural region in silicon chip substrate is removed, prepares again PDMS masking layers continue to corrode.After etching, taking out silicon chip substrate, with deionized water to wash off the corrosion on silicon chip residual Liquid obtains the silicon chip (as shown in Figure 6) with silicon slot 7 and PDMS layer 6.
3, masking layer is removed
Silicon chip substrate is coated photosensitive PDMS to be put into beaker up, the concentrated sulfuric acid is poured into, begins to warm up, be heated to dense sulphur When acid boiling, stop heating, after natural cooling, silicon chip extracting repeated the above steps up to removing remnants PDMS masking layers, It is washed with deionized water only, drying obtains the silicon chip substrate (as shown in Figure 7) of only silicon slot 7.
The present embodiment silicon chip substrate 2 obtained with silicon slot 7 is using PDMS as masking layer, manufacture craft letter Single, at low cost, good process repeatability and easy to implement.

Claims (5)

1. a kind of method that PDMS macking techniques prepare silicon slot, which is characterized in that include the following steps:
(1) the silicon chip substrate with PDMS masking layers is prepared
(1.1) it is 5-15 according to volume ratio by PDMS matrixes and curing agent:1 mixing, goes bubble to handle, and formation contains curing agent PDMS intermixtures, as non-photosensitivity PDMS;
(1.2) by Benzophenone dissolution of crystals in dimethylbenzene, Benzophenone solution, a concentration of 0.1-50g/ml of Benzophenone are formed; Non-photosensitivity PDMS and Benzophenone the solution mixing that step (1.1) is obtained, wherein the mass ratio of non-photosensitivity PDMS and Benzophenone is 30-40:1, incorporation time 10-20 minutes forms the PDMS mixed solutions to ultraviolet-sensitive, as photosensitive PDMS;
(1.3) the photosensitive PDMS that step (1.2) obtains is spin-coated on a surface of silicon chip substrate, as front, on front Photosensitive PDMS thickness be 0.1-2000um;The one side of the non-photosensitive PDMS of spin coating is as the back side;Using mask to silicon chip substrate Front be exposed, the ultraviolet wavelength of exposure<365nm, light exposure 95-400mJ/cm2
(1.4) 10-240min is dried after by the silicon chip substrate after exposure at 85-120 DEG C of temperature, rear purpose of drying is that solidification is unexposed PDMS, the photosensitive unexposed parts PDMS are cured, and photosensitive PDMS exposed portions keep original state;It will be uncured photosensitive PDMS is removed for 3-5 seconds with toluene soak;Silicon chip substrate is rinsed with isopropanol, isopropanol is dried up with nitrogen;Silicon chip substrate is dried again Dry, the temperature of drying is 80-120 DEG C, time 5min-6h;Complete the graphical of masking layer;
(1.5) non-photosensitivity PDMS is spin-coated on to the back side of silicon chip substrate, the thickness of the non-photosensitivity PDMS on the back side is 0.1- 2000um;Non-photosensitivity PDMS is dried again, the temperature of drying is 80-120 DEG C, time 5min-6h;Complete silicon chip backside of substrate The preparation of masking layer obtains the silicon chip substrate with PDMS masking layers;
(2) silicon slot is etched
(2.1) KOH is mixed with deionized water, obtains the KOH solution that mass fraction is 35%-45%, isopropanol is added and inhibits Hydrogen generates;By the face-up of silicon chip substrate, inclination is put into KOH solution;Oil bath at 80-90 DEG C or heating water bath;
(2.2) silicon chip substrate is taken out every 1h-2h, removes the PDMS for playing glue in silicon chip substrate and corrosion raffinate, prepares again PDMS masking layers continue to etch;Repeat step (1.3), (1.4), (1.5) and (2.1);After the completion of etching, silicon chip substrate is taken out, The etching raffinate in silicon chip substrate is washed off with deionized water;
(3) masking layer is removed
The silicon chip substrate that etching is completed is put into the concentrated sulfuric acid and is heated to boiling, stops heating, it is cooling;Silicon chip substrate is taken out, Remnants PDMS masking layers are removed, are washed with deionized water only, drying obtains silicon slot.
2. the method that a kind of PDMS macking techniques according to claim 1 prepare silicon slot, which is characterized in that the spin coating Parameter be 600 revs/min, time 9s of low speed, high speed 1000 revs/min, time 30s.
3. the method that a kind of PDMS macking techniques according to claim 1 or 2 prepare silicon slot, which is characterized in that described Go bubble handle mode be centrifuge remove, vacuumize, mix slowly in one or more combinations.
4. the method that a kind of PDMS macking techniques according to claim 1 or 2 prepare silicon slot, which is characterized in that using pumping Bubble removing is removed in vacuum processing, the vacuumize process 5-15min at 40-300Pa, to completely remove the bubble in PDMS solution.
5. the method that a kind of PDMS macking techniques according to claim 3 prepare silicon slot, which is characterized in that use and vacuumize Bubble removing is removed in processing, the vacuumize process 5-15min at 40-300Pa, to completely remove the bubble in PDMS solution.
CN201810337391.4A 2018-04-09 2018-04-09 Method for preparing silicon groove by PDMS masking technology Active CN108565214B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102303843A (en) * 2011-08-15 2012-01-04 中国科学技术大学 Nano fluid channel and manufacturing method thereof
CN102553506A (en) * 2010-12-30 2012-07-11 国家纳米技术与工程研究院 Method for directly forming pattern on polydimethylsiloxane (PDMS) through photoetching
CN103065938A (en) * 2012-12-31 2013-04-24 中国科学院上海微系统与信息技术研究所 Method for preparing direct band-gap germanium thin film
WO2016177888A1 (en) * 2015-05-06 2016-11-10 Danmarks Tekniske Universitet An etching mask and a method to produce an etching mask
CN106683791A (en) * 2016-12-20 2017-05-17 南京工业大学 Method for preparing flexible transparent conductive electrode with multilevel metal grid structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102553506A (en) * 2010-12-30 2012-07-11 国家纳米技术与工程研究院 Method for directly forming pattern on polydimethylsiloxane (PDMS) through photoetching
CN102303843A (en) * 2011-08-15 2012-01-04 中国科学技术大学 Nano fluid channel and manufacturing method thereof
CN103065938A (en) * 2012-12-31 2013-04-24 中国科学院上海微系统与信息技术研究所 Method for preparing direct band-gap germanium thin film
WO2016177888A1 (en) * 2015-05-06 2016-11-10 Danmarks Tekniske Universitet An etching mask and a method to produce an etching mask
CN106683791A (en) * 2016-12-20 2017-05-17 南京工业大学 Method for preparing flexible transparent conductive electrode with multilevel metal grid structure

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