CN108563588B

CN108563588B - Multi-rate interface design method of active power distribution network real-time simulator based on FPGA

Info

Publication number: CN108563588B
Application number: CN201810221838.1A
Authority: CN
Inventors: 李鹏; 王智颖; 王成山; 富晓鹏
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2018-03-18
Filing date: 2018-03-18
Publication date: 2021-02-02
Anticipated expiration: 2038-03-18
Also published as: CN108563588A

Abstract

The multi-rate interface design method of real-time simulator for active distribution network based on FPGA includes: 1) downloading the information of each subsystem to the corresponding FPGA, the subsystem m is connected to the subsystem n, and the simulation step size of the subsystem m is System n is an integer multiple of the simulation step size; 2) Set the simulation time t=0, start the simulation; 3) The simulation time advances by one step, t=t+Δt; 4) Each subsystem completes the simulation calculation and interacts with the simulation interface data; 5) subsystem m sends the received simulation interface data into the averaging unit, and subsystem n sends the received simulation interface data into the interpolation unit; 6) judges whether the physical time reaches t, and if it reaches 7), Otherwise, after the real-time simulator waits until t, enter 7); 7) judge whether the simulation time t reaches the end of the simulation, if so, the simulation ends, otherwise return to 3). The multi-rate interface design method of the present invention effectively improves the simulation speed of a real-time simulator of an active distribution network based on multiple FPGAs.

Description

Multi-rate interface design method of active power distribution network real-time simulator based on FPGA

Technical Field

The invention relates to a multi-rate interface of a real-time simulator. In particular to a multi-rate interface design method of an active power distribution network real-time simulator based on an FPGA.

Background

Along with the massive access of various power distribution side resources such as distributed power sources, energy storage devices, micro-grids and the like, the organization form and the operation characteristics of the active power distribution network are changed deeply and durably. These changes in the active power distribution network make it have greater differences and challenges in planning design, operational optimization, protection control, simulation analysis, etc. compared to conventional power distribution systems. In the aspect of simulation calculation, the dynamic characteristics of various distributed power supplies, energy storage devices, power electronic devices and other novel devices which are widely connected into an active power distribution system are more complex, the requirements cannot be met by steady-state simulation analysis of the traditional power distribution network, and the operation mechanism and the dynamic characteristics of the active power distribution network need to be deeply known by means of fine transient simulation. On this basis, the analysis and research of the detailed dynamic characteristics of the active power distribution network also need to realize the functional requirements of real-time simulation, and especially, the tests and the tests on various controllers, protection devices, intelligent terminals, novel energy management systems and the like need to be carried out in a hardware-in-the-loop (HIL) environment. Currently, the commercial real-time simulators developed abroad include RTDS, ARENE, hyperrsim, NETOMAC, RT-LAB, etc., all of which use serial processors such as dsp (digital Signal processor), cpu (central Processing unit), PowerPC, etc. as underlying hardware computing resources, and achieve computing power of real-time simulation through parallel computing of a plurality of processors.

The complex network structure and the huge system scale of the active power distribution network provide new challenges for the simulation precision, the calculation speed, the hardware resources and the like of the real-time simulator. In an active power distribution network, a power electronic switch has a high-frequency action characteristic, and a smaller simulation step length is needed for the simulation of the element; the simulation scale of the system is further increased by modeling of controllers of the distributed power supply and the energy storage element, controllers of the power electronic converter and the like, and a large burden is brought to hardware computing resources. The real-time simulator based on the serial processor is limited by the signal processing speed and the physical structure, the real-time simulation computing capacity is limited, and meanwhile, the selection of simulation step length and the numerical stability are limited by the transmission delay of data among a plurality of processors.

The FPGA has a large number of parallel bottom layer structures and distributed memories, and depth parallel calculation can be realized; meanwhile, the processing speed of the digital signal is improved by adopting a pipeline operation mode. The FPGA has rich I/O resources, comprises a full-duplex LVDS channel, a user-defined I/O interface, a high-speed transceiver and the like, and can realize board-level interaction of a large amount of data. With the development of FPGA technology, the integrated high-speed transceiver can realize 14.1Gbps data transmission rate, so that high-speed communication among multiple FPGAs becomes possible, and a solid foundation is laid for real-time simulation of a large-scale active power distribution network.

According to the structural characteristics of the active power distribution network, the resolving scale is reduced through system segmentation and parallel solving, and solving tasks of each segmented subsystem are distributed to a plurality of FPGAs, so that the method is an effective means for improving the computing speed and ensuring the real-time performance of simulation. Considering that each divided subsystem may have dynamic characteristics of different time scales, if the whole system adopts the same simulation step length, the selection of the step length size is limited by the time constant of the fast subsystem, and the real-time performance of the simulation is difficult to ensure. On the other hand, the solving scales and solving difficulty degrees of the subsystems are different, actual solving time is often different, and if a uniform simulation step length is set, the FPGAs can wait for each other until all the FPGAs finish solving tasks, so that time redundancy is caused, and the simulation time is increased. Aiming at different subsystems, the simulation step length suitable for the subsystems is adopted, so that the simulation time of the whole system can be effectively saved, and the real-time simulation requirement is met. Meanwhile, a multi-rate simulation interface adapted to the multi-rate simulation interface is required to realize a multi-rate simulation function.

Disclosure of Invention

The invention aims to solve the technical problem of providing a multi-rate interface design method of an active power distribution network real-time simulator based on an FPGA, which can meet the requirements of a multi-rate real-time simulation algorithm.

The technical scheme adopted by the invention is as follows: a multi-rate interface design method of an active power distribution network real-time simulator based on an FPGA comprises the following steps:

1) in an upper computer of an active power distribution network real-time simulator composed of N FPGA, wherein N>1, an active power distribution system to be simulated is divided into N subsystems after being decoupled by a Berilon circuit model according to topological connection relations and FPGA computing resources, basic parameters of elements of the subsystems are read to form a node conductance matrix of an electrical part of each subsystem and a computing matrix of a control part, relevant information of each subsystem is downloaded into the corresponding FPGA, each subsystem corresponds to one FPGA and is arranged in a descending order according to actual resolving time of each subsystem, the number of each subsystem is 1 to N, and the simulation step length of the ith FPGA is set to be t_iThe simulation step length of jth FPGA is t_jWherein i is 1,2, …, N, j is i +1, i +2, …, N, and t is satisfied_i＝M_i，jt_jWherein M is_i，，jSimulation that the simulation step length of the ith FPGA is the jth FPGAM times of true step length, M_i，jTaking a positive integer;

2) defining pairs of subsystems all having a direct connection relation topologically,

j is i +1, i +2, …, N, if the subsystem i is directly connected to the subsystem j, the subsystem number i is added to the set phi of slow subsystem numbers_sIn (2), j is added to the set phi of the fast subsystem numbers_fIn (3), the definition number m ∈ φ_sN is a set phi_fThe number of the subsystem pair corresponding to m one by one;

3) setting the global simulation step length of the simulator as delta t, wherein the delta t is t₁The simulation time is t; defining:

d simulation step length t of mth FPGA in global simulation step length delta t_mSimulation interface data required by nth FPGA simulation obtained by internal calculation_m，n，dThe number of (t) is N_m，nWherein

Simulation interface data_m，n，d(t) is represented by { a }_p(t)}，p＝(d-1)N_m，n+1，(d-1)N_m，n+2，…，(d-1)N_m，n+N_n，n，a_o(t) is emulation interface data_m，n，dThe p-th data of (1);

the mth FPGA sends simulation interface Data to the nth FPGA within the global simulation step length delta t_m，n(t) is

The qth simulation step length t_mInternally transmitted emulation interface Data_m，n(t) is expressed in the form of { data }_m，n，q(t)}，

The nth FPGA simulates the e-th simulation step length t in the global simulation step length delta t_nM is obtained by inner calculationSimulation interface data required by FPGA simulation_n，m，eThe number of (t) is N_n，mWherein

Simulation interface data_n，m，e(t) is represented by the form { b_r(t)}，r＝(e-1)N_n，m+1，(e-1)N_n，m+2，…，(e-1)N_n，m+N_n，m，b_r(t) is emulation interface data_n，m，eThe r-th data in (t);

the nth FPGA sends simulation interface Data to the mth FPGA within the global simulation step length delta t_n，m(t) is

Simulation step length t_nInternally transmitted emulation interface Data_n，m(t) is expressed in the form of { data }_n，m，s(t)}，

The whole real-time simulator is driven by a clock clk;

4) initializing a simulator, setting the simulation time t as 0, and starting simulation;

5) the simulation time is advanced by one step length, and t is t + delta t;

the mth FPGA completes the simulation by using the data read from the average unit of the mth FPGA

After step simulation calculation task, the calculated simulation interface Data is_m，n(t) sending to the nth FPGA;

the nth FPGA completes the simulation by using the data read from the interpolation unit of the nth FPGA

After step simulation calculation task, the calculated simulation interface Data is_n，m(t) sending to the mth FPGA;

6)

the mth FPGA finishes receiving the simulation interface Data sent by the nth FPGA_n，mAfter (t), simulating interface Data_n，m(t) sending the average data into an average unit of the device to be processed to obtain average data;

the nth FPGA finishes receiving the simulation interface Data sent by the mth FPGA_m，nAfter (t), simulating interface Data_m，n(t) sending the data into an interpolation unit of the device to process to obtain interpolation data;

7) judging whether the physical time reaches the simulation time t, if so, entering the next step, otherwise, entering the next step after the real-time simulator is standby to the simulation time t;

8) and judging whether the simulation time T reaches the set simulation finishing time T, if so, finishing the simulation, otherwise, returning to the step 3).

The interpolation unit in the step 5) and the step 6) is a random access memory RAM_m，n，1、RAM_m，n，2、RAM_m，n，3And RAM_m，n，4Read only memory ROM_m，nAnd a first-in first-out queue FIFO_m，n，1Form, using emulation interface Data_m，nLast N of (t-. DELTA.t)_n，mSimulation interface data

Data of interface with simulation_m，n(t) carrying out

Performing linear interpolation operation on the next two points, wherein interpolation data obtained by the interpolation operation of the g time is as follows:

wherein

The specific implementation mode is as follows: will Data_m，n(t) write RAM_m，n，1In (1), Data_m，nLast N of (t-. DELTA.t)_m，nSimulation interface data

And Data_m，n(t) before

Simulation interface data_m，n，l(t) } write into RAM sequentially_m，n，2In which

Respectively from RAM_m，n，1And RAM_m，n，2Reading out all the simulation interface data to obtain

And

computing

And writing the obtained result into RAM_m，n，3In the process, the

Write RAM_m，n，4In the ROM_m，nData stored therein

Is in the format of { X_cTherein of

X_cThe number of each element in the group is equal to N_m，n(ii) a Reading ROM_m，nData stored therein

Respectively connect the RAM_m，n，3And RAM_m，n，4In turn, every N_m，nEach data is a set of repeated reads

Then, obtain

And

and (3) calculating:

and writing the obtained result into FIFO_m，n，1Middle, read FIFO_m，n，1To obtain interpolation data.

The averaging unit in the step 5) and the step 6) is a random access memory RAM_n，m，5Accumulator, FIFO queue_n，m，2，FIFO_n，m，3Form, simulating interface Data_n，m(t) carrying out

And (4) performing secondary average operation, wherein average data obtained by the h-th average operation are as follows:

wherein

The specific implementation mode is as follows: will Data_n，m(t) write FIFO_n，m，2In, from FIFO_n，m，2In the read Data_n，m(t) post write RAM_n，m，5，RAM_n，m，5The read address addr _ r is:

slave RAM_n，m，5In which all data are read out to obtain

Will be provided with

In turn according to each

The data are sent to an accumulator for accumulation to obtain

Personal Data_sumCalculating

And writing the obtained result into FIFO_n，m，3Middle, read FIFO_n，m，3The average data is obtained.

The multi-rate interface design method of the active power distribution network real-time simulator based on the FPGA fully considers the hardware characteristics of the FPGA and the structural characteristics of the active power distribution network, effectively realizes various functional requirements of real-time multi-rate simulation of the active power distribution network by facing a multi-rate simulation algorithm, and lays a foundation for realizing the large-scale active power distribution network real-time simulation based on the FPGA.

Drawings

FIG. 1 is a diagram of an interpolation unit design;

FIG. 2 is a diagram of an averaging unit design;

FIG. 3 is a flow chart of a multi-rate interface design of an active power distribution network real-time simulator based on an FPGA;

FIG. 4 is an active power distribution network real-time simulation platform based on FPGA;

FIG. 5 is an example of a test of an active distribution network including photovoltaic, storage batteries;

FIG. 6 is a detailed structure of a photovoltaic/accumulator unit;

FIG. 7 is a detail of a single stage photovoltaic cell;

FIG. 8 is a DC voltage V of a photovoltaic/accumulator unit_{PV/Battery,dc}A simulation result graph;

FIG. 9 shows the photovoltaic output active power P of the photovoltaic unit 1_PV1A simulation result graph;

FIG. 10 shows photovoltaic cell 2 grid-connected point A phase current I_PV2,aA simulation result graph;

FIG. 11 shows the grid-connected point A phase voltage V of the photovoltaic unit 2_PV2,aAnd (5) a simulation result graph.

Detailed Description

The multi-rate interface design method of the active power distribution network real-time simulator based on the FPGA of the present invention is described in detail below with reference to the embodiments and the accompanying drawings.

The invention discloses a multi-rate interface design method of an active power distribution network real-time simulator based on an FPGA (field programmable gate array), belongs to the field of power system simulation, and is particularly suitable for the field of active power distribution network real-time simulation.

As shown in fig. 3, the method for designing the multi-rate interface of the real-time simulator of the active power distribution network based on the FPGA of the present invention comprises the following steps:

1) in an upper computer of an active power distribution network real-time simulator composed of N FPGA, wherein N>1, an active power distribution system to be simulated is divided into N subsystems after being decoupled by a Berilon circuit model according to topological connection relations and FPGA computing resources, basic parameters of elements of the subsystems are read to form a node conductance matrix of an electrical part of each subsystem and a computing matrix of a control part, relevant information of each subsystem is downloaded into the corresponding FPGA, each subsystem corresponds to one FPGA and is arranged in a descending order according to actual resolving time of each subsystem, the number of each subsystem is 1 to N, and the simulation step length of the ith FPGA is set to be t_iThe simulation step length of jth FPGA is t_jWherein i is 1,2, …, N, j is i +1, i +2, …, N, and t is satisfied_i＝M_i，jt_jWherein M is_i，jThe simulation step length of the ith FPGA is M times of that of the jth FPGA, and M is_i，jTaking a positive integer;

The simulation interface data datam, n, d (t) is expressed in the form of { a }_p(t)}，p＝(d-1)N_m，n+1，(d-1)N_m，n+2，…，(d-1)N_m，n+N_m，n，a_p(t) is emulation interface data_m，n，dThe p-th data of (1);

The nth FPGA simulates the e-th simulation step length t in the global simulation step length delta t_nSimulation interface data required by mth FPGA simulation obtained by internal calculation_n，m，eThe number of (t) is N_n，mWherein

The whole real-time simulator is driven by a clock clk;

5) the simulation time is advanced by one step length, and t is t + delta t;

nth FPGA utilizes fromThe data required by the simulation read in the interpolation unit of the self completes

6)

The interpolation units in the above steps 5) and 6) are, as shown in fig. 1, composed of a random access memory RAM_m，n，1，RAM_m，n，2，RAM_m，n，3，RAM_m，n，4Read only memory ROM_m，nAnd a first-in first-out queue FIFO_m，n，1Form, using emulation interface Data_m，nLast N of (t-. DELTA.t)_n，mSimulation interface data

Data of interface with simulation_m，n(t) carrying out

wherein

And Data_m，n(t) before

And

computing

And writing the obtained result into RAM_m，n，3In the process, the

Write RAM_m，n，4In the ROM_m，nData stored therein

Is in the format of { X_cTherein of

Then, obtain

And

and (3) calculating:

The averaging units described in the above steps 5) and 6), as shown in FIG. 2, are implemented by a RAM_n，m，5Accumulator, FIFO queue_n，m，2，FIFO_n，m，3Form, simulating interface Data_n，m(t) carrying out

wherein

slave RAM_n，m，5In which all data are read out to obtain

Will be provided with

In turn according to each

The data are sent to an accumulator for accumulation to obtain

Personal Data_sumCalculating

Specific examples are given below:

in the embodiment of the invention, the multi-FPGA-based real-time simulator adopts four Stratix V series FPGA5SGSMD5K2F40C2N of Altera company and matched official development boards thereof to complete the real-time simulation of the active power distribution network containing the photovoltaic power generation system. As shown in FIG. 4, the FPGA1 communicates with the other three FPGAs at the same time, and no data interaction exists among the FPGA2, the FPGA3 and the FPGA 4. And optical fibers are adopted among the development boards to realize communication. The whole real-time simulator is driven by a 125MHz clock, and the single-channel data transmission rate between the FPGAs is 2500 Mbps.

The test example is an IEEE 33 node system including photovoltaic cells and storage batteries, as shown in fig. 5, a photovoltaic/storage battery unit and two single-stage photovoltaic power generation units having the same structure are respectively connected to

nodes

18, 22, and 33 of the IEEE 33 node system, the detailed structure of the photovoltaic/storage battery unit is shown in fig. 6, and the detailed structure of the photovoltaic power generation unit is shown in fig. 7. The photovoltaic cell is simulated by a single-diode equivalent circuit, and the storage battery adopts a general equivalent circuit model. In the photovoltaic/storage battery unit, a storage battery is connected with a photovoltaic battery in parallel through a DC/DC converter and a direct current bus, the photovoltaic battery adopts a bipolar form, the DC/DC of the photovoltaic battery is a Boost booster circuit, and the reference value of photovoltaic voltage is set to 750V. The DC/DC in the storage battery pack adopts a bidirectional Boost/Buck circuit, the storage battery is in a Boost circuit mode when discharging, the storage battery is in a Buck voltage reduction circuit mode when charging, the storage battery pack is used for maintaining the constant bus voltage, the reference value of the bus voltage is set to 750V, the inverter adopts PQ control, and the constant output active power and reactive power of the whole hybrid system are maintained. The photovoltaic unit 1 and the photovoltaic unit 2 have the same structural parameters, and the inverter adopts V_dcQ control, reactive power reference set to 0 Var. And when the simulation scene is set to be 2.0s, the grid-connected point of the photovoltaic unit 2 has an A-phase grounding short-circuit fault.

The whole calculation example is simulated on a multi-FPGA real-time simulator, wherein an IEEE 33 node system occupies an FPGA1, and three photovoltaic power generation units respectively occupy an FPGA2, an FPGA3 and an FPGA 4. The simulation step lengths of the photovoltaic/storage battery system and the photovoltaic power generation unit are set to be 4 mu s, and the simulation step length of the IEEE 33 node system is set to be 8 mu s.

Simulation results of the real-time simulator based on the FPGA and the commercial software PSCAD/EMTDC are shown in fig. 8 to 11, and the PSCAD/EMTDC uses a single simulation step size of 4 μ s. As can be seen from the figure, the results given by the two simulation systems are basically consistent, so that the correctness and the effectiveness of the design of the multi-rate interface of the active power distribution network real-time simulator based on the FPGA are verified.

Claims

1. a kind of active distribution network real-time simulator multi-rate interface design method based on FPGA, is characterized in that, comprises the steps:

1) In the host computer of the active power distribution network real-time simulator composed of N FPGAs, where N>1, the active power distribution system to be simulated is based on the topology connection relationship and the computing resources of the FPGA, using the Beryllon circuit. After the model is decoupled, it is divided into N subsystems, the basic parameters of each subsystem element are read, the node conductance matrix of the electrical part of each subsystem and the calculation matrix of the control part are formed, and the relevant information of each subsystem is downloaded to the corresponding In the FPGA, each subsystem corresponds to an FPGA, which is arranged in descending order according to the actual solution time of each subsystem. The number of each subsystem is from 1 to N, and the simulation step size of the i-th FPGA is set to t _i , and the j-th FPGA The simulation step size is t _j , where i=1,2,...,N, j=i+1,i+2,...,N, and t _i =M _i,j t _j , where M _i,j Indicates that the simulation step size of the i-th FPGA is M times the simulation step size of the j-th FPGA, and M _i,j is a positive integer;

2) Define pairs of subsystems that are all topologically directly connected,

If subsystem i is directly connected to subsystem j, add subsystem number i to the set of slow subsystem numbers

, add j to the set of fast subsystem numbers

, define the number

The number n is the set

The number of the subsystem pair corresponding to m one-to-one in ;

3) Set the global simulation step size of the simulator as Δt, Δt=t ₁ , and the simulation time as t; define:

The number of simulation interface data data _m,n,d (t) required for the nth FPGA simulation calculated by the _mth FPGA within the dth simulation step tm within the global simulation step Δt is N _{m ,n} , where

The representation of the simulation interface data data _m,n,d (t) is {a _p (t)}, p=(d-1)N _m,n +1,(d-1)N _m,n +2, ...,(d-1)N _m,n +N _m,n , a _p (t) is the p-th data of the simulation interface data data _m,n,d ;

The number of simulation interface data Data _m,n (t) sent by the mth FPGA to the nth FPGA within the global simulation step size Δt is:

The representation of the simulation interface data Data _m,n (t) sent within the qth simulation step size t _m is {data _m,n,q (t)},

The number of simulation interface data data _n,m,e (t) required for the mth FPGA simulation calculated by the nth FPGA within the eth simulation step _tn within the global simulation step Δt is N _{n, m} , where

The representation of the simulation interface data data _n,m,e (t) is {br (t)}, _r =(e-1)N _n,m +1,(e-1)N _n,m +2, ...,(e-1)N _n,m +N _n,m , br (t) is the _rth data in the simulation interface data data _n,m,e (t);

The number of simulation interface data Data _n,m (t) sent by the nth FPGA to the mth FPGA within the global simulation step size Δt is:

The representation of the simulation interface data Data _n,m (t) sent within the sth simulation step t _n is {data _n,m,s (t)},

The entire real-time simulator is driven by the clock clk;

4) Initialize the simulator, and set the simulation time t=0 to start the simulation;

5) Advance the simulation time by one step, t=t+Δt;

The mth FPGA uses the data required for the simulation read from its own averaging unit to complete

After simulating the calculation task step by step, send the calculated simulation interface data Data _m,n (t) to the nth FPGA;

The nth FPGA uses the data required for the simulation read from its own interpolation unit to complete

After performing the simulation task step by step, send the calculated simulation interface data Data _n,m (t) to the mth FPGA;

6)

After the mth FPGA finishes receiving the simulation interface data Data _n,m (t) sent by the nth FPGA, it sends the simulation interface data Data _n,m (t) into its own averaging unit for processing to obtain average data;

After the nth FPGA finishes receiving the simulation interface data Data _m,n (t) sent by the mth FPGA, it sends the simulation interface data Data _m,n (t) into its own interpolation unit for processing to obtain interpolation data;

7) Judging whether the physical time reaches the simulation time t, if it reaches the simulation time t, then enter the next step, otherwise the real-time emulator waits until the simulation time t, and then enters the next step;

8) Judging whether the simulation time t reaches the set simulation end time T, such as reaching the set simulation end time T, the simulation ends, otherwise return to step 3);

The interpolation unit described in step 5) and step 6) is composed of random access memory RAM _m,n,1 , RAM _m,n,2 , RAM _m,n,3 and RAM _m,n,4 , read-only memory ROM _m,n is composed of FIFO _m,n,1 , and the last N _n,m simulation interface data of simulation interface data Data _m,n (t-Δt) are used.

with the simulation interface data Data _m,n (t)

The second two-point linear interpolation operation, the interpolation data obtained by the gth interpolation operation is:

in

The specific implementation method is: write Data _m,n (t) into RAM _m,n,1 , and write the last N _m,n simulation interface data of Data _m,n (t-Δt)

with Data _m,n (t) before

The simulation interface data {data _m,n,l (t)} are written into RAM _m,n,2 in turn, where

Read all simulation interface data from RAM _{m, n, 1} and RAM _{m, n, 2} respectively, and get

and

calculate

and write the obtained results into RAM _{m, n, 3} , and

Write the data stored in RAM _m,n,4 and ROM _m,n

is of the form {X _c }, where

The number of elements in X _c is equal to N _m,n ; read the data stored in ROM _m,n

Respectively read the data in RAM _{m, n, 3} and RAM _{m, n, 4} in turn by repeating each N _{m, n} data as a group

times, get

and

calculate:

And write the obtained result into FIFO _{m, n, 1} , read the data in FIFO _{m, n, 1} , and get the interpolation data;

The averaging unit described in step 5) and step 6) is composed of random access memory RAM _n,m,5 , accumulator, first-in-first-out queue FIFO _n,m,2 , FIFO _n,m,3 , and the simulation interface Data Data _n,m (t) is carried out

The average data obtained by the h-th averaging operation is:

in

The specific implementation method is: write Data _n,m (t) into FIFO _n,m, 2, read out data Data _n,m (t) from FIFO _n,m,2 and write into RAM _n,m,5 , the read address addr_r of RAM _{n, m, 5} is:

Read all data from RAM _n,m,5 , get

Will

press each

A group of data is sent to the accumulator for accumulation to get

Data _sum , calculate

And write the obtained results into FIFO _{n, m, 3} , read the data in FIFO _{n, m, 3} , and get the average data.