CN108550596A - Device architecture forming method and imaging sensor forming method - Google Patents
Device architecture forming method and imaging sensor forming method Download PDFInfo
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- CN108550596A CN108550596A CN201810469787.4A CN201810469787A CN108550596A CN 108550596 A CN108550596 A CN 108550596A CN 201810469787 A CN201810469787 A CN 201810469787A CN 108550596 A CN108550596 A CN 108550596A
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- 238000003384 imaging method Methods 0.000 title claims abstract description 24
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- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 17
- 238000010276 construction Methods 0.000 claims description 14
- 238000012856 packing Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims description 4
- 229910001930 tungsten oxide Inorganic materials 0.000 claims description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The present invention provides a kind of device architecture forming method and the forming method of imaging sensor.The device architecture forming method includes：Darc layer (dielectric reflecting-resisting-layer) is formed on a semiconductor substrate, using the darc layer as mask, the semiconductor substrate is etched to form first part and the second groove of first groove, again using the photoresist layer of second graphical and darc layer as mask, the semiconductor substrate is etched to form the second part of first groove, the second part of the first groove is connected to the first part of the first groove, the sum of the first part of the first groove and the depth of second part are more than the depth of the second groove, and which simplify technological processes.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, are passed more particularly to a kind of device architecture forming method and image
Sensor forming method.
Background technology
In technical field of semiconductors, imaging sensor is a kind of semiconductor device that optical imagery can be converted into electric signal
Part.Imaging sensor can generally be divided into charge coupled cell (Charge Coupled Device, abbreviation CCD) sensor
With two kinds of cmos image sensor (CMOS Image Sensor, abbreviation CIS).Ccd image sensor
The advantages of be image sensitivity compared with high, noise is small, but ccd image sensor and other devices is integrated relatively difficult, and
Ccd image sensor power consumption is higher.In contrast, CIS imaging sensors due to it is simple for process, easily with other device collection
At, small, light-weight, small power consumption, it is at low cost the advantages that and gradually replace the status of CCD imaging sensors.CIS schemes now
As sensor is widely used in smart phone, digital camera, DV, medical photographic device (such as gastroscope), vehicle
Among the fields such as photographic device.
Currently, CIS imaging sensors in order to obtain higher quantum efficiency, introduce condenser type trench isolations (CDTI,
Capacitive Deep Trench Isolation) and deep trench isolation (DTI, Deep Trench Isolation) is double
Depth groove isolation structure.But inventor has found, the entire technical process for obtaining the dual-depth groove isolation construction is lengthy and tedious, multiple
It is miscellaneous.
Invention content
The purpose of the present invention is to provide a kind of device architecture forming methods, with simplification of flowsheet.
To achieve the goals above, the present invention provides a kind of device architecture forming methods, including：
Dielectric reflecting-resisting-layer is formed on a semiconductor substrate；The first patterned light is formed on the dielectric reflecting-resisting-layer
Photoresist layer, and using the described first patterned photoresist layer as mask, etch the dielectric reflecting-resisting-layer and form the first opening, then
Remove the described first patterned photoresist layer；Using the dielectric reflecting-resisting-layer as mask, etch the semiconductor substrate, with
Corresponding first opening forms first part and the second groove of first groove；Is formed on the dielectric reflecting-resisting-layer
The photoresist layer of two patterned photoresist layers, the second graphical fills first part and the second ditch of the first groove
Slot, and using the photoresist layer of the second graphical as mask etches the dielectric reflecting-resisting-layer and forms the second opening, and described the
Two openings are above the first part of the first groove；And with the photoresist layer of the second graphical and dielectric anti-reflective
It is mask to penetrate layer, etches the semiconductor substrate to form the second part of first groove, the second part of the first groove
Be connected to the first part of the first groove, to form first groove, then remove the photoresist layer of the second graphical with
And the dielectric reflecting-resisting-layer.
Optionally, filled layer is formed in the first groove and the second groove.
Optionally, the thickness of the dielectric reflecting-resisting-layer is
Optionally, the opening width of second opening is more than the width of the first part of the first groove.
Optionally, the first part of the first groove and the depth of the second groove are 0.2~0.6 μm, described
The depth of first groove is 1.5~3 μm.
Optionally, the material of the filled layer is tungsten or tungsten oxide.Further, the step of formation filled layer includes：
Using physical gas-phase deposition or chemical vapor deposition method in the first groove and the second groove
Middle formation packing material；And it is removed except the first groove and the second groove by chemical mechanical milling tech
Packing material, to form filled layer in the first groove and the second groove.
The present invention also provides a kind of forming methods of imaging sensor, including：It is configured using device junction as described above
First groove and second groove are formed at method；And filling is formed in the first groove and the second groove
Layer, to form condenser type groove isolation construction and deep trench isolation structure.
Optionally, described image sensor is CIS imaging sensors, and the condenser type groove isolation construction is for defining
The circuit region of the pixel unit of CIS imaging sensors, the deep trench isolation structure are used to be isolated the phase of CIS imaging sensors
Light in adjacent pixel unit is to avoid mixed light.The condenser type groove isolation construction and the deep trench isolation structure are in ring
Shape, and the deep trench isolation structure surrounds the condenser type groove isolation construction.
Compared with prior art, device architecture forming method provided by the present invention, forms DARC on a semiconductor substrate
Layer (dielectric reflecting-resisting-layer) etches the semiconductor substrate, to form the first of first groove with the darc layer for hard mask
Part and second groove, then using the photoresist layer of the second graphical and darc layer as mask, etch the semiconductor substrate
To form the second part of first groove, the second part of the first groove is connected to the first part of the first groove,
The sum of the first part of the first groove and the depth of second part are more than the depth of the second groove, to simplify work
Skill flow.
Description of the drawings
Fig. 1 is a kind of flow diagram of device architecture forming method in the prior art；
Fig. 2 a~2g are a kind of cross-sectional view of device architecture forming method in the prior art；
Fig. 3 is the flow diagram for the device architecture forming method that one embodiment of the invention provides；
Fig. 4 a~4f are the cross-sectional view for the device architecture forming method that one embodiment of the invention provides；
Description of drawing identification：
10- semiconductor substrates；11- substrates；12- dielectric layers；
The first BARC layers of 21-；The second BARC layers of 22-；23- third BARC layers；
The first photoresist layers of 31-；The second photoresist layers of 32-；
41- second grooves；42- first grooves；
51-CDTI structures；52-DTI structures；
100- semiconductor substrates；110- substrates；120- dielectric layers；
200-DARC layers；200a- first is open；200b- second is open；
310- second grooves；320- first grooves；The first part of 320a- first grooves；The second of 320b- first grooves
Part；
410-CDTI structures；420-DTI structures；The photoresist layer of 520- second graphicals.
Specific implementation mode
Inventor has found that CIS imaging sensors need to use dual-depth groove isolation construction (condenser type groove isolation construction
With deep trench isolation structure).
A kind of condenser type trench isolations (CDTI) and deep trench isolation (DTI) are introduced with reference to Fig. 1 and Fig. 2 a~2g
Structure formation method.
Fig. 2 a are to form the schematic diagram after the first BARC layer on a semiconductor substrate.As shown in Figure 2 a, step S11 is executed,
Form the first BARC layer (bottom layer anti-reflection layer) 21 over the semiconductor substrate 10, the semiconductor substrate 10 include substrate (such as
It is silicon base) 11 and dielectric layer 12 disposed thereon, the dielectric layer oxide layer in this way, first BARC layer 21
Thinner thickness.
Fig. 2 b are the schematic diagram after the first photoetching offset plate figure.As shown in Figure 2 b, step S12 is executed, described first
The first photoresist layer 31 is coated on BARC layer 21, and by exposure, graphical first photoresist layer 31 of developing process, it is described
The figure of first photoresist forms the mask graph of second groove as subsequent etching.
Fig. 2 c are the schematic diagram after forming second groove.As shown in Figure 2 c, step S13 is executed, with the institute after graphical
It is mask to state the first photoresist layer 31, etches first BARC layer 21, removes first photoresist layer 31, then with described the
One BARC layer 21 is that hard mask etches the semiconductor substrate 10, to form second groove 41.
Fig. 2 d are the schematic diagram after the 2nd BARC fillings.As shown in Figure 2 d, first, step S14 is executed, removes first
BARC layer 21, and the 2nd BARC layers 22 are filled in the second groove 41, it is affected when preventing subsequent etching.
Fig. 2 e are the schematic diagram after the second photoetching offset plate figure.As shown in Figure 2 e, step S15 is executed, described second
The 3rd BARC layers 23 are re-formed in the semiconductor substrate 10 after the filling of BARC layer 22, and are coated on third BARC layer 23
Second photoresist layer 32, exposure, develop graphical second photoresist layer 32.
Fig. 2 f are the schematic diagram after forming first groove.As shown in figure 2f, step S16 is executed, with patterned second
Photoresist layer 32 is third BARC layer 23 described in mask etching, then removes second photoresist layer 32, then with the third
BARC layer 23 is that hard mask etches the semiconductor substrate 10, to form the first groove 42 for being located at 41 outside of second groove, then
The 3rd BARC layers 23 are removed, here, the second groove 41 and the etching of the first groove 42 are formed and finished.
Fig. 2 g are that the schematic diagram after filled layer is formed in second groove and first groove.As shown in Figure 2 g, first, step is executed
Rapid S17 forms filled layer in the second groove 41 and the first groove 42, to form CDTI structures 51 and described
The material of DTI structures 52, the filled layer is, for example, tungsten or tungsten oxide.
Based on above-mentioned processing step, inventor in entire technical process the study found that need to carry out Twi-lithography glue
Coating, exposure, development are graphical, and corresponding etching groove (i.e. Twi-lithography technique), need progress BARC layer twice
The filling with etching and first BA RC is formed, whole process processing step is lengthy and tedious, complicated, and process costs are higher.Meanwhile
The price of BARC is more expensive, causes process materials cost higher.
In addition, inventor also found, since the material of BARC layer and the material of photoresist are all made of resinae,
When photoresist removes, BARC layer can be influenced by some so that part BARC layers is removed.
Based on the studies above, in device architecture forming method of the invention, use material for the DARC conducts of silicon oxynitride
Hard mask etch semiconductor substrates, to form first part and the second groove of first groove, then with the second graphical
Photoresist layer and darc layer form the second part of first groove as mask etching semiconductor substrate, and entire technical process obtains
Simplification has been arrived, while having also reduced cost.
Below in conjunction with the drawings and specific embodiments to a kind of device architecture forming method and imaging sensor of the present invention
Forming method is described in further detail.According to following explanation, advantages and features of the invention will become apparent from.It should be noted that
Attached drawing is all made of very simplified form and uses non-accurate ratio, only to convenient, lucidly aid illustration is of the invention
The purpose of embodiment.In addition, in order to simple and clear.
A kind of device architecture forming method that the present embodiment is provided.Fig. 3 is that device architecture provided in this embodiment is formed
The flow diagram of method.As shown in figure 3, this method comprises the following steps：
Step S21：Darc layer (dielectric reflecting-resisting-layer) is formed on a semiconductor substrate；
Step S22：The first patterned photoresist layer is formed on the dielectric reflecting-resisting-layer, and with first figure
The photoresist layer of change is mask, etches the dielectric reflecting-resisting-layer and forms the first opening, then removes the described first patterned light
Photoresist layer；
Step S23：Using the dielectric reflecting-resisting-layer as mask, the semiconductor substrate is etched, in correspondence described first
Opening forms first part and the second groove of first groove；
Step S24：Second graphical described in the photoresist layer of second graphical is formed on the dielectric reflecting-resisting-layer
Photoresist layer fills first part and the second groove of the first groove, and is to cover with the photoresist layer of the second graphical
Film etches the dielectric reflecting-resisting-layer and forms the second opening, and second opening is in the first part of the first groove
Side；
Step S25：Using the photoresist layer of the second graphical and dielectric reflecting-resisting-layer as mask, the semiconductor is etched
To form the second part of first groove, the second part of the first groove and the first part of the first groove connect substrate
It is logical, to form first groove, then remove the photoresist layer of the second graphical and the dielectric reflecting-resisting-layer；And
Step S26：Filled layer is formed in the first groove and the second groove.
It is, for example, that image passes to be provided for the embodiments of the invention a kind of device architecture with reference to Fig. 3 and Fig. 4 a~4f
Sensor, further is, for example, that the forming method of CIS imaging sensors describes in detail.
Fig. 4 a are the schematic cross-section after forming darc layer in the present embodiment.As shown in fig. 4 a, step S21 is executed,
Darc layer 200 is formed in semiconductor substrate 100.The semiconductor substrate 100 includes substrate (being, for example, silicon base) 110 and is situated between
Matter layer 120, the dielectric layer 120 are, for example, oxide layer, and the thickness of the darc layer 200 isIt is general next
It says, the thickness of DARC can be adjusted according to the line width of groove or the difference of photoresist type of etching.In the present embodiment
In, the thicker darc layer of use (dielectric reflecting-resisting-layer) substitutes existing used relatively thin BARC layer (bottom anti-reflection layer),
It advantageously reduces material cost.
Fig. 4 b are the schematic cross-section after removing the first patterned photoresist layer in the present embodiment.As shown in Figure 4 b,
Step S22 is executed, forms the first patterned photoresist layer on the darc layer 200, and with the described first patterned light
Photoresist layer is mask, etches the darc layer 200, and the first opening 200a, first opening are formed in the darc layer 200
200a exposes the semiconductor substrate 100, then removes the described first patterned photoresist layer.First patterned photoresist layer
Figure be used for defining the first opening 200a, the opening width of the groove in subsequent step is defined by the first opening 200a.It is excellent
Choosing, the etching of the darc layer 200 uses dry etching, e.g. oxygen gas plasma is used to etch, and in the present embodiment
Etching in subsequent step is all made of oxygen gas plasma etching.
In the present embodiment, the first patterned photoresist layer is removed by the way of oxygen ashing.
Fig. 4 c are the schematic cross-section after the first part and second groove for forming first groove in the present embodiment.Such as figure
Shown in 4c, step S23 is executed, is mask with the darc layer 200, etches the semiconductor substrate 100, in correspondence described first
Second groove 310 is formed at opening 200a, while forming the first part of first groove in the positions corresponding first opening 200a
320a.The first part 320a of the first groove and the depth of the second groove 310 are 0.2~0.6 μm.In this implementation
In example, 310 depth of the second groove is identical with first part's 320a depth of the first groove, e.g. 0.4 μm.
From the foregoing, it will be observed that this step had both formd second groove (being, for example, the groove of CDTI structures) using etching technics, together
When yet form first groove first part 320a (be, for example, DTI structures groove a part), compared with prior art,
Reduce processing step.
Fig. 4 d are the schematic cross-section after the photoresist of removal second graphical in the present embodiment.As shown in figure 4d, it holds
Row step S24 forms the photoresist layer 520 of second graphical, the photoresist of the second graphical on the darc layer 200
The 520 filling second groove 310 of layer, and be mask with the photoresist layer of the second graphical 520, etch the darc layer
200, the second opening 200b is formed in the DARC layers 200, the second opening 200b exposes the semiconductor substrate 100, described
Second opening 200b is located above the first part 200a of the first groove.In the photoresist for forming the second graphical
The first part 320a of the second groove 310 and the first groove has been also filled up when 520.Thus, directly in ditch
Photoresist layer is filled in slot, reduces the processing step of trench fill.
In the present embodiment, the second opening 200b of the darc layer 200 is only located at the first part of the first groove
The top of 320a, the second opening 200b are used for defining the opening width of first groove in subsequent step.In the present embodiment, institute
State the second opening 200b opening width be more than the first groove first part 320a width, be conducive in second graph
The photoresist layer 520 of change it is graphical when caused map migration do not influence being normally carried out for subsequent etching.Further, described
The opening width of the photoresist layer 520 of second graphical is e.g. bigger than the width of the first part 320a of the first groove
30nm。
Fig. 4 e are the schematic cross-section after the second part for forming first groove in the present embodiment.As shown in fig 4e, it holds
Row step S25 is mask with the photoresist layer 520 and darc layer 200 of the second graphical, etches the semiconductor substrate
100 to form the second part 320b of first groove, and the of the second part 320b of the first groove and the first groove
A part of 320a connections, to form first groove 320, the depth of the first groove is preferably 1.5~3 μm, then removes institute
State the photoresist layer 520 and the darc layer 200 of second graphical.In the present embodiment, second of the first groove
320b is divided to be connected to the first part 320a of the first groove, and the depth of the first groove 320 is, for example, 2 μm, preferably
, the opening width of the first groove 320 is wide compared to the width of other parts, and the depth of width along groove is gradual
Narrow, it is whole trapezoidal.
Since the material of DARC is silicon oxynitride, in the removal of photoresist by minor impact, and BARC due to
Material and the material of photoresist are all made of resinae, in the removal of photoresist by large effect, are unfavorable for subsequently carving
Etching technique in the thicker DARC layers of formation thickness, can further carry out repeatedly using it as the etching technics of mask.Cause
This, in the present embodiment using DARC layer substitute BARC, and technique by the formation of the once darc layer of thicker degree instead of existing
Lower thickness twice BARC layer formation.Its compared with prior art, which simplify processing steps, while avoiding because of work
Semiconductor substrate etching homogeneity caused by skill complexity is poor and BARC fills insufficient problem.
Fig. 4 f are structural schematic diagram of the present embodiment after metal filling processes.As shown in fig. 4f, step S26 is executed,
Filled layer is formed in the first groove 320 and the second groove 310.The material of the filled layer is, for example, tungsten or oxidation
Tungsten.
Wherein, the step of forming the filled layer include：
Step S26a：Using physical gas-phase deposition (PVD) or chemical vapor deposition method (CVD) described first
Packing material is formed in groove 320 and the second groove 310；And
Step S26b：By chemical mechanical milling tech remove the first groove 320 and the second groove 310 it
Outer packing material, to form filled layer in the first groove 320 and the second groove 310.
The embodiment of the present invention also provides a kind of forming method of imaging sensor, is formed using device architecture as described above
Method forms first groove and second groove；And
Form filled layer in the first groove and the second groove, with formed condenser type groove isolation construction with
And deep trench isolation structure, the material of the filled layer is, for example, tungsten or tungsten oxide.
Described image sensor is, for example, CIS imaging sensors, and the condenser type groove isolation construction is for defining CIS figures
As the circuit region of the pixel unit of sensor, the deep trench isolation structure is used to be isolated the adjacent picture of CIS imaging sensors
Light in plain unit is to avoid mixed light.
Specifically, each pixel unit of the CIS imaging sensors has condenser type trench isolations (CDTI) structure
With deep trench isolation (DTI) structure, condenser type trench isolations (CDTI) structure is used to define the circuit region of pixel,
In pixel unit, and its plan view shape is annular (being, for example, straight-flanked ring).Deep trench isolation (DTI) structure is used for
The light in the adjacent pixel unit of CIS imaging sensors is isolated to avoid mixed light, is located at the boundary of pixel unit, and it is overlooked
Shape is annular (being, for example, straight-flanked ring).The DTI structures surround the CDTI structures, and the quantity example of the CDTI structures
1 in this way, the quantity of the DTI structures is, for example, 1, and the common plan view shape of the two is, for example, that " returning " word shape is presented, and is cutd open
Face Pictorial examples reference chart 4f in this way.
There are one CDTI structures and a DTI structures for pixel unit tool in the present embodiment.Certainly, in other implementations
In example, the quantity of CDTI structures and DTI structures can be changed according to actual needs.
In conclusion in a kind of device architecture forming method provided by the present invention, pass through shape on a semiconductor substrate
At darc layer, and using darc layer as hard mask etch semiconductor substrates, to form first part and the second ditch of first groove
Slot, then the first part of first groove is further etched, to form the second part of first groove, to complete the first ditch
The etching of slot and second groove, whole process simplify processing step.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of device architecture forming method, which is characterized in that including：
Dielectric reflecting-resisting-layer is formed on a semiconductor substrate；
The first patterned photoresist layer is formed on the dielectric reflecting-resisting-layer, and with the described first patterned photoresist layer
For mask, etches the dielectric reflecting-resisting-layer and form the first opening, then remove the described first patterned photoresist layer；
Using the dielectric reflecting-resisting-layer as mask, the semiconductor substrate is etched, to form the in correspondence first opening
The first part of one groove and second groove；
The photoresist layer of second graphical, the photoresist layer filling of the second graphical are formed on the dielectric reflecting-resisting-layer
The first part of the first groove and second groove, and using the photoresist layer of the second graphical as mask, described in etching
Dielectric reflecting-resisting-layer forms the second opening, and second opening is above the first part of the first groove；And
Using the photoresist layer of the second graphical and dielectric reflecting-resisting-layer as mask, the semiconductor substrate is etched to form
The second part of one groove, the second part of the first groove are connected to the first part of the first groove, to form
One groove, then remove the photoresist layer of the second graphical and the dielectric reflecting-resisting-layer.
2. the method as described in claim 1, which is characterized in that further include：
Filled layer is formed in the first groove and the second groove.
3. the method as described in claim 1, which is characterized in that the thickness of the dielectric reflecting-resisting-layer is
4. the method as described in claim 1, which is characterized in that the opening width of second opening is more than the first groove
First part width.
5. the method as described in claim 1, which is characterized in that the first part of the first groove and the second groove
Depth is 0.2~0.6 μm, and the depth of the first groove is 1.5~3 μm.
6. method as claimed in claim 2, which is characterized in that the material of the filled layer is tungsten or tungsten oxide.
7. method as claimed in claim 2, which is characterized in that formed filled layer the step of include：
Using physical gas-phase deposition or chemical vapor deposition method in the first groove and the second groove shape
At packing material；And
The packing material except the first groove and the second groove is removed by chemical mechanical milling tech, in institute
It states in first groove and the second groove and forms filled layer.
8. a kind of forming method of imaging sensor, which is characterized in that including：
First groove and second groove are formed using the device architecture forming method as described in any one of claim 1 to 7；
And
Filled layer is formed in the first groove and the second groove, to form condenser type groove isolation construction and depth
Groove isolation construction.
9. method as claimed in claim 8, which is characterized in that described image sensor is CIS imaging sensors, the capacitance
Formula groove isolation construction is used to define the circuit region of the pixel unit of CIS imaging sensors, and the deep trench isolation structure is used
Light in the adjacent pixel unit of isolation CIS imaging sensors is to avoid mixed light.
10. method as claimed in claim 9, which is characterized in that the condenser type groove isolation construction and the deep trench every
It is annular in shape from structure, and the deep trench isolation structure surrounds the condenser type groove isolation construction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810469787.4A CN108550596A (en) | 2018-05-16 | 2018-05-16 | Device architecture forming method and imaging sensor forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023178907A1 (en) * | 2022-03-24 | 2023-09-28 | 上海芯物科技有限公司 | Manufacturing process and structure for backside-illuminated sensor having deep trench isolation |
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