CN108549750A - Placement-and-routing's method of large capacity SRAM - Google Patents
Placement-and-routing's method of large capacity SRAM Download PDFInfo
- Publication number
- CN108549750A CN108549750A CN201810262607.5A CN201810262607A CN108549750A CN 108549750 A CN108549750 A CN 108549750A CN 201810262607 A CN201810262607 A CN 201810262607A CN 108549750 A CN108549750 A CN 108549750A
- Authority
- CN
- China
- Prior art keywords
- sram
- signal wire
- large capacity
- small
- routing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention provides a kind of placement-and-routing's methods of large capacity SRAM, including：N small-capacity memory is spliced into the static RAM SRAM of large capacity, and layering is carried out to SRAM；The cabling that Clock Tree form is carried out to the signal wire that each small-capacity memory in the bottom module shares, makes same signal while reaching each small-capacity memory；The signal wire of the bottom module is distributed into according to Clock Tree form to the center of the SRAM in the top level structure, then is gone out from centre position to the boundary cloth of the SRAM；State is corrected into sequential, the retention time of the SRAM is violated and settling time violates and is modified operation.Placement-and-routing's method of large capacity SRAM provided by the present invention reduces the degree of freedom of each signal, makes it easier to control, and is easily accomplished the timing closure entirely designed.
Description
Technical field
The present invention relates to integrated circuit back-end physical Design technical field, more particularly to a kind of layout cloth of large capacity SRAM
Line method.
Background technology
In a chip design, memory module occupies always prodigious proportion, static random storage on chip-area overhead
Device（SRAM）As a member in memory module, above situation equally exists.With the development of society, the sharp increase of data volume,
People generally also can apply to SRAM design in electronic product at the individual chips of one piece of large capacity.One piece of large capacity SRAM is
It is spliced by the memory of multiple low capacities, more complicated selection circuit and control circuit etc. is had in entire circuit.Such as
Fruit realizes its function, very labor intensive and time with the method for customization.And the unconventional chip of sram chip, do not post
Storage is to the path of register, and clock is given in the non-external world again, this physics for just needing us to cast aside conventional digital chip is set
Thought is counted, a kind of placement-and-routing's method of completely new suitable large capacity sram chip is probed into out.
Invention content
The present invention provides a kind of placement-and-routing's methods of large capacity SRAM, and its purpose is to solve large capacity SRAM's
Sequential is difficult to correct, the big problem of timing closure difficulty.
In order to achieve the above object, the embodiment provides a kind of placement-and-routing's method of large capacity SRAM, packets
It includes：
N small-capacity memory is spliced into the static RAM SRAM of large capacity, and layering cloth is carried out to SRAM
Line；Wherein, the bottom module of the SRAM is made of m small-capacity memory, and top level structure is by n/m bottom module composition；
The cabling that Clock Tree form is carried out to the signal wire that each small-capacity memory in the bottom module shares, makes same letter
Number simultaneously reach each small-capacity memory；
By the signal wire of the bottom module in the top level structure according to Clock Tree form to the center of the SRAM
It is distributed into, then is gone out from centre position to the boundary cloth of the SRAM；
State is corrected into sequential, the retention time of the SRAM is violated and settling time violates and is modified operation.
Wherein, in the static RAM SRAM that n small-capacity memory is spliced into large capacity, and it is right
After SRAM carries out the step of layering, the degree of freedom of each signal wire of the small-capacity memory is reduced to（m+n/m）.
Wherein, the shared signal wire of each small-capacity memory carries out Clock Tree form in described to the bottom module
Cabling, after the step of making same signal while reaching each small-capacity memory, the single signal wire of the bottom module
Degree of freedom be reduced to 1 from m, the degree of freedom in the SRAM is reduced to（1+n/m）.
Wherein, in the signal wire by the bottom module in the top level structure according to Clock Tree form to described
The center of SRAM is distributed into, then after the step of going out from centre position to the boundary cloth of the SRAM, the single signal wire
Degree of freedom be reduced to 1 in the top level structure, the degree of freedom in the SRAM is reduced to 2.
Wherein, the sequential that enters corrects state, is violated to the retention time of the SRAM and settling time violates and carries out
Correcting the step of operating is specially：
In sequential makeover process, the amendment of retention time violation is first carried out, then carries out the amendment of settling time violation.
Wherein, the signal wire by the bottom module in the top level structure according to Clock Tree form to described
The center of SRAM is distributed into, then the step of going out from centre position to the boundary cloth of the SRAM is specially：
After the signal wire of the bottom module is inputted to the inside center of the SRAM, IO diffusions around, the SRAM's
Selecting module and decoding module are arranged in the center of the SRAM, and the IO on four sides of the SRAM from center to two
Side-sway is put.
The said program of the present invention has following advantageous effect：
Placement-and-routing's method of large capacity SRAM described in the above embodiment of the present invention is spelled by being grouped to small-capacity memory
It connects, layering is carried out to SRAM, so that circuit design is become simple, operate simple and clear, timing closure will carry significantly
Height, and then save design time.
Description of the drawings
Fig. 1 is the flow diagram of placement-and-routing's method of the large capacity SRAM of the present invention；
Fig. 2 is the domain structure schematic diagram of the bottom module of the present invention；
Fig. 3 is the layout structure schematic diagram of the top level structure of the present invention.
Specific implementation mode
To keep the technical problem to be solved in the present invention, technical solution and advantage clearer, below in conjunction with attached drawing and tool
Body embodiment is described in detail.
The present invention is difficult to correct for the sequential of existing large capacity SRAM, and the big problem of timing closure difficulty provides
A kind of placement-and-routing's method of large capacity SRAM.
As shown in Figure 1 to Figure 3, the embodiment provides a kind of placement-and-routing's methods of large capacity SRAM, including：
Step 1, n small-capacity memory is spliced into the static RAM SRAM of large capacity, and SRAM is carried out
Layering；Wherein, the bottom module of the SRAM is made of m small-capacity memory, and top level structure is by n/m bottom module
It constitutes；
Step 2, the cabling that Clock Tree form is carried out to the signal wire that each small-capacity memory in the bottom module shares, makes
Same signal reaches each small-capacity memory simultaneously；
Step 3, by the signal wire of the bottom module in the top level structure according to Clock Tree form into the SRAM
Heart position is distributed into, then is gone out from centre position to the boundary cloth of the SRAM；
Step 4, state is corrected into sequential, the retention time of the SRAM is violated and settling time violates and is modified behaviour
Make.
Method described in the above embodiment of the present invention is applied to typical large capacity SRAM circuit, the SRAM in embodiment
It is made of the small-capacity memory of 128 4096x8, input port has data D [0-8], address A [0-19], control read-write
W, when W is low, chip is in write state, when W is high, and chip is in the state read；Select 16 small-capacity memory groups
It is spliced into a complete SRAM circuit at a bottom module, then by 8 bottom modules, so that circuit design is become simple, behaviour
Make to get up simple and clear, timing closure will greatly improve, and then save design time.
Wherein, in the static RAM SRAM that n small-capacity memory is spliced into large capacity, and it is right
After SRAM carries out the step of layering, the degree of freedom of each signal wire of the small-capacity memory is reduced to（m+n/m）.
Method described in the above embodiment of the present invention selectes address A [1] by taking above-mentioned large capacity SRAM circuit as an example,
A [1] is transferred on 16 small-capacity memories in the bottom module, degree of freedom 16, in 8 bottom module groups of top layer
At complete SRAM circuit, A [1] leads to 8 identical bottom modules, and degree of freedom 8, the two adds up, to A [1]
For degree of freedom be 24, degree of freedom is smaller to be more easy to control, and then the easier convergence of sequential.
Wherein, the shared signal wire of each small-capacity memory carries out Clock Tree form in described to the bottom module
Cabling, after the step of making same signal while reaching each small-capacity memory, the single signal wire of the bottom module
Degree of freedom be reduced to 1 from m, the degree of freedom in the SRAM is reduced to（1+n/m）.
Method described in the above embodiment of the present invention is by taking above-mentioned large capacity SRAM circuit as an example, each low capacity storage
It is a concurrency relation without directly contacting between device；In order to shorten the time that data read and are written, to make all signals all several
The small-capacity memory is synchronously arrived at, does not allow there is the case where mutually waiting between signal, in order to achieve the above object, to institute
The shared signal wire of some small-capacity memories carries out the cabling of Clock Tree form, in bottom module, single signal wire from
It is reduced to 1 by spending from 16, the degree of freedom in the SRAM is reduced to 9, only need to be in the bus of each signal in sequential later is corrected
Upper operation, accurate and effective.
Wherein, in the signal wire by the bottom module in the top level structure according to Clock Tree form to described
The center of SRAM is distributed into, then after the step of going out from centre position to the boundary cloth of the SRAM, the single signal wire
Degree of freedom be reduced to 1 in the top level structure, the degree of freedom in the SRAM is reduced to 2.
Method described in the above embodiment of the present invention is by taking above-mentioned large capacity SRAM circuit as an example, in the cloth of top level structure
In office, all signals are first inputted to sram chip inside center, and then IO diffusions again around, selecting module MUX and are translated
Positions of the code module Decoder close to design centre；All IO, which swing sideward on four side of chip from center, to be put, and is shortened and is walked line length
Degree；By taking A [1] as an example, the degree of freedom of top level structure A [1] is reduced to 1 from 8, and total degree of freedom is reduced to 2.
Wherein, the sequential that enters corrects state, is violated to the retention time of the SRAM and settling time violates and carries out
Correcting the step of operating is specially：
In sequential makeover process, the amendment of retention time violation is first carried out, then carries out the amendment of settling time violation.
Method described in the above embodiment of the present invention further includes sequential amendment, first corrects retention time violation, then correct
Settling time violates, and can easily complete placement-and-routing's work of large capacity SRAM timing closures.
Wherein, the signal wire by the bottom module in the top level structure according to Clock Tree form to described
The center of SRAM is distributed into, then the step of going out from centre position to the boundary cloth of the SRAM is specially：
After the signal wire of the bottom module is inputted to the inside center of the SRAM, IO diffusions around, the SRAM's
Selecting module and decoding module are arranged in the center of the SRAM, and the IO on four sides of the SRAM from center to two
Side-sway is put.
Placement-and-routing's method of large capacity SRAM described in the above embodiment of the present invention passes through to small-capacity memory point
Group splicing carries out layering to SRAM, so that circuit design is become simple, operates simple and clear, timing closure will be big
It is big to improve, and then save design time.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of placement-and-routing's method of large capacity SRAM, which is characterized in that including：
N small-capacity memory is spliced into the static RAM SRAM of large capacity, and layering cloth is carried out to SRAM
Line；Wherein, the bottom module of the SRAM is made of m small-capacity memory, and top level structure is by n/m bottom module composition；
The cabling that Clock Tree form is carried out to the signal wire that each small-capacity memory in the bottom module shares, makes same letter
Number simultaneously reach each small-capacity memory；
By the signal wire of the bottom module in the top level structure according to Clock Tree form to the center of the SRAM
It is distributed into, then is gone out from centre position to the boundary cloth of the SRAM；
State is corrected into sequential, the retention time of the SRAM is violated and settling time violates and is modified operation.
2. placement-and-routing's method of large capacity SRAM according to claim 1, which is characterized in that described by n little Rong
Amount memory is spliced into the static RAM SRAM of large capacity, and after the step of carrying out layering to SRAM,
The degree of freedom of each signal wire of the small-capacity memory is reduced to（m+n/m）.
3. placement-and-routing's method of large capacity SRAM according to claim 2, which is characterized in that described to the bottom
The shared signal wire of each small-capacity memory carries out the cabling of Clock Tree form in module, makes same signal while reaching each
After the step of small-capacity memory, the degree of freedom of the single signal wire of the bottom module is reduced to 1 from m, in the SRAM
Degree of freedom be reduced to（1+n/m）.
4. placement-and-routing's method of large capacity SRAM according to claim 3, which is characterized in that described by the bottom
The signal wire of module is distributed into according to Clock Tree form to the center of the SRAM in the top level structure, then by interposition
After setting the step of going out to the boundary cloth of the SRAM, the degree of freedom of the single signal wire is reduced to 1 in the top level structure,
Degree of freedom in the SRAM is reduced to 2.
5. placement-and-routing's method of large capacity SRAM according to claim 1, which is characterized in that described to enter sequential amendment
State, violating the step of being modified operation to the retention time violation of the SRAM and settling time is specially：
In sequential makeover process, the amendment of retention time violation is first carried out, then carries out the amendment of settling time violation.
6. placement-and-routing's method of large capacity SRAM according to claim 1, which is characterized in that described by the bottom mould
The signal wire of block is distributed into according to Clock Tree form to the center of the SRAM in the top level structure, then by centre position
The step of going out to the boundary cloth of the SRAM be specially：
After the signal wire of the bottom module is inputted to the inside center of the SRAM, IO diffusions around, the SRAM's
Selecting module and decoding module are arranged in the center of the SRAM, and the IO on four sides of the SRAM from center to two
Side-sway is put.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810262607.5A CN108549750A (en) | 2018-03-28 | 2018-03-28 | Placement-and-routing's method of large capacity SRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810262607.5A CN108549750A (en) | 2018-03-28 | 2018-03-28 | Placement-and-routing's method of large capacity SRAM |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108549750A true CN108549750A (en) | 2018-09-18 |
Family
ID=63517087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810262607.5A Pending CN108549750A (en) | 2018-03-28 | 2018-03-28 | Placement-and-routing's method of large capacity SRAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108549750A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1281254A (en) * | 2000-08-29 | 2001-01-24 | 中国科学院微电子中心 | Process for preparing very large scale integrated circuit (VLSIC) |
| US20040153985A1 (en) * | 2003-01-31 | 2004-08-05 | Terachip Inc. | Layout methodology and system for automated place and route |
| US20050034093A1 (en) * | 2001-10-26 | 2005-02-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for designing the same |
-
2018
- 2018-03-28 CN CN201810262607.5A patent/CN108549750A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1281254A (en) * | 2000-08-29 | 2001-01-24 | 中国科学院微电子中心 | Process for preparing very large scale integrated circuit (VLSIC) |
| US20050034093A1 (en) * | 2001-10-26 | 2005-02-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for designing the same |
| US20040153985A1 (en) * | 2003-01-31 | 2004-08-05 | Terachip Inc. | Layout methodology and system for automated place and route |
Non-Patent Citations (4)
| Title |
|---|
| 刘祥远等: "高性能VLSI设计中时钟分布网络的问题与解决方法", 《计算机工程与科学》 * |
| 张婷婷: "ASIC后端设计中的时钟树综合优化研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 杨朱黎: "时钟偏差补偿技术的研究及应用", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 杨清宝: "嵌入式SRAM的高速、低功耗设计及优化", 《中国优秀博硕士学位论文全文数据库（硕士） 信息科技辑》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11687454B2 (en) | Memory circuit and cache circuit configuration | |
| US9690502B2 (en) | Systems and methods for segmenting data structures in a memory system | |
| US6430088B1 (en) | Embedded static random access memory for field programmable gate array | |
| US20200006306A1 (en) | Configurable random-access memory (ram) array including through-silicon via (tsv) bypassing physical layer | |
| JPS5919367A (en) | Gate array with memory | |
| JPH03263687A (en) | Multi-port memory | |
| CN107111566A (en) | Dynamic random access memory (DRAM) part for the memory module of high-performance, high power capacity with register | |
| EP0646925B1 (en) | Fully scalable memory apparatus | |
| JPH03715B2 (en) | ||
| CN105629811A (en) | Multiplex input-output interface circuit supporting multiple testing functions and generation method thereof | |
| US9026747B2 (en) | Memory device with a logical-to-physical bank mapping cache | |
| CN108549750A (en) | Placement-and-routing's method of large capacity SRAM | |
| CN111857562A (en) | Method and memory module for configuring vendor specific registers | |
| US7196963B1 (en) | Address isolation for user-defined configuration memory in programmable devices | |
| CN103426452A (en) | Memory cascade and packaging methods, and device thereof | |
| TW202230352A (en) | Memory circuit architecture | |
| CN209266027U (en) | A kind of quick reading circuit of difference, storage chip and memory | |
| CN107491400A (en) | A kind of hard disk information storage method and device | |
| US5363337A (en) | Integrated circuit memory with variable addressing of memory cells | |
| JPS58150198A (en) | System for checking memory | |
| US9424073B1 (en) | Transaction handling between soft logic and hard logic components of a memory controller | |
| US20220244867A1 (en) | Fabric Memory Network-On-Chip Extension to ALM Registers and LUTRAM | |
| US10283177B1 (en) | Method and system for controller hold-margin of semiconductor memory device | |
| CN107464583A (en) | A kind of self-timing circuit and static RAM for static RAM | |
| US5373464A (en) | CCD array memory device having dual, independent clocks of differing speeds |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180918 |
|
| RJ01 | Rejection of invention patent application after publication |