CN209266027U - A kind of quick reading circuit of difference, storage chip and memory - Google Patents
A kind of quick reading circuit of difference, storage chip and memory Download PDFInfo
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- CN209266027U CN209266027U CN201822139549.5U CN201822139549U CN209266027U CN 209266027 U CN209266027 U CN 209266027U CN 201822139549 U CN201822139549 U CN 201822139549U CN 209266027 U CN209266027 U CN 209266027U
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Abstract
The utility model discloses a kind of quick reading circuits of difference, storage chip and memory, 0 or 1 thinking is exported based on differential comparator, it is that 0 or 1 combine by the storage content of storage unit, pass through PCH and latch control signal, two bit line control terminals of energy are filled within the T1 time of PCH signal high level, two bit line control terminals are controlled within the T2 time of latch signal high level carries out either end electric discharge, in this, as two inputs of difference main circuit, due to the characteristic of difference channel, it can be realized the high speed judgement of two input signals, to quickly export the content of storage unit.
Description
Technical field
The utility model relates to a kind of reading circuit of storage unit, the quick reading circuit of especially a kind of difference, storage
Chip and memory.
Background technique
It is often switched using metal-oxide-semiconductor as logic judgment signal in flash memory circuit or storage circuit, and the opening of metal-oxide-semiconductor
It is by the voltage that is applied on metal-oxide-semiconductor as control with closing, but voltage control metal-oxide-semiconductor switch has prolonging centainly
When, have become a performance bottleneck in high speed flash memory circuit, the especially reading of memory cell content uses traditional electricity
Pressing decision circuitry to be read out data, speed is very slow, has seriously dragged slowly the processing speed of flash memory.
Utility model content
To solve the above problems, the utility model provides a kind of quick reading circuit of difference, storage can be quickly read
The content of unit, directly 0 or 1 data of output.
The technical solution adopted by the utility model to solve the problem is as follows:
A kind of quick reading circuit of difference, including be made of metal-oxide-semiconductor difference main circuit, PCH control terminal, latch signal control
End, the first bit line control terminal and second line traffic control end processed, the PCH control terminal are connected to the difference main circuit as switch
Control terminal, the latch signal control terminal connect the difference main circuit and digitally, the first bit line control terminal and second
Bit line control terminal connects the difference main circuit, and the first bit line control terminal and second line traffic control respectively as input terminal
The input signal at end is not identical, data output end of the output end of the difference main circuit as storage unit.
Further, the difference main circuit is made of 6 metal-oxide-semiconductors, respectively M0, M1, M2, M3, M4 and M5, the M0-
The drain electrode that the source electrode of M3 is all connected with Vcc, the M0 and M1 connects the drain electrode of the M4, and the M2 connects the M5 with the drain electrode of M3
Drain electrode, the drain electrode of the M4 connects the first bit line control terminal, and the drain electrode of the M5 connects second line traffic control end,
The grid of the M1 and M4 is connected to output end of the drain electrode of the M5 as the difference main circuit, the grid of the M2 and M5
It is connected to the drain electrode of the M4, the source electrode of the M4 and M5 are connected to the latch signal control terminal.
Further, the PCH control terminal includes the PCH phase inverter an of single-input single-output, the PCH phase inverter it is defeated
It is connected to the grid of the M0 out.
Further, the latch signal control terminal includes metal-oxide-semiconductor M6, and the drain electrode of the M6 connects the difference main circuit,
Grid connects Latch signal, and source electrode connects digitally.
Further, the first bit line control terminal includes capacitor C0 and the first bit line, described in the connection of the one end the capacitor C0
The drain electrode of M4 and first bit line, the other end connect digitally；Second line traffic control end includes capacitor C1 and second
Line, the one end the capacitor C2 connects the drain electrode of the M5 and second bit line, the other end connect digitally；First bit line
It is not identical with the output signal of the second bit line.
Further, the capacitor C0 is identical with the capacitance of capacitor C1.
Further, the output end of the difference main circuit connects the output phase inverter of a single-input single-output, described defeated
The output end output 0 or 1 of phase inverter out.
A kind of memory chip includes a kind of any of the above-described quick reading circuit of difference.
A kind of memory is provided at least one processor chip, includes that a kind of any of the above-described difference quickly reads electricity
Road.
The beneficial effects of the utility model are: the utility model exports 0 or 1 thinking based on differential comparator, will store
The storage content of unit is that 0 or 1 combine, through PCH and latch control signal, within the T1 time of PCH signal high level
Two bit line control terminals of energy are filled, two bit line control terminals progress either ends are controlled within the T2 time of latch signal high level and are put
Electricity, due to the characteristic of difference channel, can be realized the high speed of two input signals in this, as two inputs of difference main circuit
Judgement, to quickly export the content of storage unit.
Detailed description of the invention
The utility model is described in further detail with reference to the accompanying drawings and examples.
Fig. 1 is the integrated circuit figure of the utility model embodiment；
Fig. 2 is the time diagram of each control signal of the utility model embodiment.
Specific embodiment
Referring to Fig.1, one embodiment of the utility model provides a kind of quick reading circuit of difference, including by metal-oxide-semiconductor
Difference main circuit, PCH control terminal, latch signal control terminal, the first bit line control terminal and the second line traffic control end of composition, it is described
PCH control terminal is connected to the difference main circuit as switch control terminal, and the latch signal control terminal connects the difference master
Circuit and digitally, the first bit line control terminal connects the main electricity of the difference respectively as input terminal with second line traffic control end
Road, and the first bit line control terminal and the input signal at second line traffic control end be not identical, the output of the difference main circuit
Hold the data output end as storage unit.
Difference channel is based in the present embodiment, the input at the first bit line control terminal described first and second line traffic control end is believed
It number is determined, is needed to the first bit line control terminal and second line traffic control end by the carry cell cases of the bit line of storage array
The different unit of carry is selected in PGM (program, programming) unit and ERASE (erase, erasable) unit respectively, that is, is deposited
It stores up array and uses complementation unit structure, the input of the first bit line control terminal and second line traffic control end is determined by structure
Signal；Secondly PCH (platform controller) signal and latch signal control clock respectively and beat the metal-oxide-semiconductor in the difference main circuit
It is open and close, thus the output result of the control difference main circuit；Since PCH signal itself and latch signal are also conventional deposit
Control signal in storage road, the present embodiment do not increase too many circuit element relative to traditional storage circuit, still
The reading manner for directly passing through level height is changed, 0 or 1 output is realized using differential comparison, is had in quickly reading
The advantages of appearance.
Preferably, the utility model another embodiment provides for a kind of quick reading circuit of difference, the difference masters
Circuit is made of 6 metal-oxide-semiconductors, respectively M0, M1, M2, M3, M4 and M5, and the source electrode of the M0-M3 is all connected with Vcc, the M0
The drain electrode of the M4 is connected with the drain electrode of M1, the drain electrode of the M2 and M3 connect the drain electrode of the M5, the drain electrode connection of the M4
The grid of the first bit line control terminal, the drain electrode connection second line traffic control end of the M5, the M1 and M4 are connected to
The grid of output end of the drain electrode of the M5 as the difference main circuit, the M2 and M5 are connected to the drain electrode of the M4, institute
The source electrode for stating M4 and M5 is connected to the latch signal control terminal.
The present embodiment shows in particular the composition of the difference main circuit, actually symmetric circuit, wherein M0, M1 and M4
It is left side, M2, M3 and M5 are right sides, and intermediate connections are the connecting pin Vcc and the latch signal control terminal, the PCH control
End and latch signal control terminal are based on timing, control the switch of metal-oxide-semiconductor, realize and input to the difference of the difference main circuit.
Preferably, the utility model another embodiment provides for a kind of quick reading circuit of difference, the PCH control
End includes the PCH phase inverter of a single-input single-output, and the output of the PCH phase inverter is connected to the grid of the M0.This reality
It applies and adds the shaping that PCH phase inverter is used for clock signal in example, reduce interference.
Preferably, the utility model another embodiment provides for a kind of quick reading circuit of difference, the latch letter
Number control terminal includes metal-oxide-semiconductor M6, and the drain electrode of the M6 connects the difference main circuit, and grid connects Latch signal, source electrode connection
Digitally.Wherein Latch signal is latch signal.
Preferably, the utility model another embodiment provides for a kind of quick reading circuit of difference, described first
Line traffic control end includes capacitor C0 and the first bit line, the one end the capacitor C0 connect the M4 drain electrode and first bit line, separately
One end connects digitally；Second line traffic control end includes capacitor C1 and the second bit line, described in the connection of the one end the capacitor C2
The drain electrode of M5 and second bit line, the other end connect digitally；The output signal of first bit line and the second bit line not phase
Together, meanwhile, the capacitor C0 is identical with the capacitance of capacitor C1.
Pass through the charging of capacitor this gives the first bit line control terminal and second line traffic control end and releases
Realize the scheme of different outputs, wherein the capacitance of capacitor C0 and C2 is 20f, and capacitor C0 and C2 when releasing different into
Row, can only control one of them charge of releasing, discharge time and depth of discharge are controlled by the clock signal of latch signal.
Preferably, the utility model another embodiment provides for a kind of quick reading circuit of difference, the difference masters
The output end of circuit connects the output phase inverter of a single-input single-output, the output end output 0 or 1 of the output phase inverter.
The present embodiment, by output signal shaping, obtains more good differential level signal using phase inverter.
A kind of memory chip includes a kind of quick reading circuit of difference of any of the above-described embodiment.
A kind of memory is provided at least one processor chip, include any of the above-described embodiment a kind of difference it is fast
Fast reading sense circuit.
Referring to Fig.1, one embodiment of the utility model provides a kind of quick reading circuit of difference, including one by 6
Difference main circuit, PCH control terminal, latch signal control terminal, the first bit line control terminal and the second line traffic control of a metal-oxide-semiconductor composition
End, the PCH control terminal are connected to the difference main circuit as switch control terminal, described in the latch signal control terminal connects
Difference main circuit and digitally, the first bit line control terminal connects the difference respectively as input terminal with second line traffic control end
Divide main circuit, and the first bit line control terminal and the input signal at second line traffic control end be not identical, the difference main circuit
Data output end of the output end as storage unit.
The difference main circuit is made of 6 metal-oxide-semiconductors, respectively M0, M1, M2, M3, M4 and M5, the source of the M0-M3
The drain electrode that pole is all connected with Vcc, the M0 and M1 connects the drain electrode of the M4, and the drain electrode of the M2 and M3 connect the leakage of the M5
Pole, the drain electrode of the M4 connect the first bit line control terminal, and the drain electrode of the M5 connects second line traffic control end, described
The grid of M1 and M4 is connected to output end of the drain electrode of the M5 as the difference main circuit, and the M2 is connected with the grid of M5
To the drain electrode of the M4, the source electrode of the M4 and M5 are connected to the latch signal control terminal.
The PCH control terminal includes the PCH phase inverter an of single-input single-output, the output connection of the PCH phase inverter
To the grid of the M0.The latch signal control terminal includes metal-oxide-semiconductor M6, and the drain electrode of the M6 connects the difference main circuit,
Grid connects Latch signal, and source electrode connects digitally.The output end of the difference main circuit connects a single-input single-output
Export phase inverter, the output end output 0 or 1 of the output phase inverter.
The first bit line control terminal includes capacitor C0 and the first bit line, and the one end the capacitor C0 connects the drain electrode of the M4
With first bit line, the other end is connected digitally；Second line traffic control end includes capacitor C1 and the second bit line, the electricity
Appearance one end C2 connects the drain electrode of the M5 and second bit line, the other end connect digitally；First bit line and second
The output signal of line is not identical.The capacitor C0 is identical with the capacitance of capacitor C1 and is 20f.
The storage array of the present embodiment uses complementation unit structure, therefore the first bit line control terminal and second line traffic control
The input signal at end processed is not identical, actually refers to be respectively connected to different units on first bit line and the second bit line,
The first situation is to access PGM unit on second bit line when accessing ERASE unit on first bit line；Feelings in second
Condition is to access ERASE unit on second bit line when accessing PGM unit on first bit line.
The step of reference Fig. 2, the present embodiment control sequential is the height electricity that the PCH control terminal input duration is T1
Voltage increases in the wordline of ordinary mail number while storage array, and first bit line and the second bit line fill capacitor C0 and C2
Electricity, then PCH control terminal is switched to low level and latch signal control terminal input duration is the high level signal of T2,
In the T2 time, for the first above-mentioned situation, the charge of the capacitor C0 is released, and the charge of capacitor C2 is basically unchanged, institute
Difference main circuit output 0 is stated, for above-mentioned second situation, the charge of the charge C2 is released, and the charge of capacitor C0 is basic
It is constant, the difference main circuit output 1.
The present embodiment is in such a way that the characteristic of difference channel is instead of conventional voltage-level reading storing data, due to difference
Circuit only two input terminals are compared, therefore can quickly output difference as a result, be suitable for the higher flash memory products of speed.
The above, the only preferred embodiment of the utility model, the utility model are not limited to above-mentioned implementation
Mode, as long as its technical effect for reaching the utility model with identical means, all should belong to the protection scope of the utility model.
Claims (9)
1. a kind of quick reading circuit of difference, it is characterised in that: including be made of metal-oxide-semiconductor difference main circuit, PCH control terminal,
Latch signal control terminal, the first bit line control terminal and second line traffic control end, the PCH control terminal are connected to the main electricity of the difference
As switch control terminal, the latch signal control terminal connects the difference main circuit and digitally, the first bit line control on road
End processed connects the difference main circuit, and the first bit line control terminal and respectively as input terminal with second line traffic control end
The input signal of two bit line control terminals is not identical, data output end of the output end of the difference main circuit as storage unit.
2. the quick reading circuit of a kind of difference according to claim 1, it is characterised in that: the difference main circuit is by 6
Metal-oxide-semiconductor composition, respectively M0, M1, M2, M3, M4 and M5, the source electrode of the M0-M3 are all connected with Vcc, the drain electrode of the M0 and M1
The drain electrode of the M4 is connected, the drain electrode of the M2 and M3 connect the drain electrode of the M5, described first of the drain electrode connection of the M4
The grid of line traffic control end, the drain electrode connection second line traffic control end of the M5, the M1 and M4 are connected to the leakage of the M5
The grid of output end of the pole as the difference main circuit, the M2 and M5 are connected to the drain electrode of the M4, the M4 and M5's
Source electrode is connected to the latch signal control terminal.
3. the quick reading circuit of a kind of difference according to claim 2, it is characterised in that: the PCH control terminal includes one
The PCH phase inverter of a single-input single-output, the output of the PCH phase inverter are connected to the grid of the M0.
4. the quick reading circuit of a kind of difference according to claim 1 or 2, it is characterised in that: the latch signal control
End includes metal-oxide-semiconductor M6, and the drain electrode of the M6 connects the difference main circuit, and grid connects Latch signal, source electrode connection number
Ground.
5. the quick reading circuit of a kind of difference according to claim 2, it is characterised in that: the first bit line control terminal packet
Include capacitor C0 and the first bit line, the one end the capacitor C0 connect the M4 drain electrode and first bit line, other end connection number
Word；Second line traffic control end includes capacitor C1 and the second bit line, the one end the capacitor C2 connect the M5 drain electrode and
Second bit line, the other end connect digitally；The output signal of first bit line and the second bit line is not identical.
6. the quick reading circuit of a kind of difference according to claim 5, it is characterised in that: the capacitor C0's and capacitor C1
Capacitance is identical.
7. the quick reading circuit of a kind of difference according to claim 1, it is characterised in that: the output of the difference main circuit
The output phase inverter of one single-input single-output of end connection, the output end output 0 or 1 of the output phase inverter.
8. a kind of memory chip, it is characterised in that: include the fast fast reading of a kind of difference as claimed in claim 1
Sense circuit.
9. a kind of memory is provided at least one processor chip, it is characterised in that: including any just like claim 1-7
The quick reading circuit of a kind of difference.
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| CN201822139549.5U CN209266027U (en) | 2018-12-19 | 2018-12-19 | A kind of quick reading circuit of difference, storage chip and memory |
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| CN201822139549.5U CN209266027U (en) | 2018-12-19 | 2018-12-19 | A kind of quick reading circuit of difference, storage chip and memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109493906A (en) * | 2018-12-19 | 2019-03-19 | 珠海博雅科技有限公司 | A kind of quick reading circuit of difference, storage chip and memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109493906A (en) * | 2018-12-19 | 2019-03-19 | 珠海博雅科技有限公司 | A kind of quick reading circuit of difference, storage chip and memory |
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Address after: 519000 unit a1106-1107, block a, entrepreneurship building, Tsinghua Science Park, 101 University Road, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee after: Zhuhai Boya Technology Co.,Ltd. Address before: Unit a1005-1007, block a, pioneering building, Tsinghua Science Park, 101 University Road, Tangjiawan Town, Zhuhai City, Guangdong Province, 519080 Patentee before: ZHUHAI BOYA TECHNOLOGY Co.,Ltd. |
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