CN108539965B - PWM pulse control method based on full-bridge circuit, storage medium and terminal - Google Patents
PWM pulse control method based on full-bridge circuit, storage medium and terminal Download PDFInfo
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- CN108539965B CN108539965B CN201810401932.5A CN201810401932A CN108539965B CN 108539965 B CN108539965 B CN 108539965B CN 201810401932 A CN201810401932 A CN 201810401932A CN 108539965 B CN108539965 B CN 108539965B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
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- Dc-Dc Converters (AREA)
Abstract
The invention provides a PWM pulse control method based on a full-bridge circuit, which at least comprises the following steps: sampling the output voltage in a preset modulation period to obtain a voltage sampling result, calculating the sampling result by adopting a PID (proportion integration differentiation) controller, and calculating to obtain an opening time value for an MOS (metal oxide semiconductor) tube in a full-bridge circuit; and adjusting the duty ratio of the PWM pulse according to the relationship between the preset upper limit threshold value and the preset lower limit threshold value and the opening time value. In addition, the embodiment of the invention also provides a storage medium and a terminal. By applying the embodiment of the invention, the problem of complex calculation of adjusting the PWM phase by adopting a phase-shifting control algorithm in the prior art is solved.
Description
Technical Field
The present invention relates to the technical field of PWM pulse control based on a full-bridge circuit, and in particular, to a PWM pulse control method based on a full-bridge circuit, a storage medium, and a terminal.
Background
The high-power switch power supply is switched on and off at high speed by controlling a switch tube through a circuit. The direct current is converted into alternating current with high frequency and provided to a transformer for transformation, so as to generate one or more groups of required voltages. A common high-power supply power part circuit is usually in a full-bridge topology structure, and the control of the DC/DC output voltage is realized through the regulation of PWM pulses.
PWM control techniques control the switching on and off of the semiconductor switching device so that the output receives a series of pulses of equal amplitude and unequal width, which are used to replace a sine wave or other desired waveform. The width of each pulse is modulated according to a certain rule, so that the magnitude of the output voltage of the inverter circuit can be changed, and the output frequency can also be changed.
In the prior art, the control of the DC/DC output voltage is usually realized by adopting a traditional phase-shift PWM pulse control method, and the traditional phase-shift control algorithm is complicated.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a PWM pulse control method based on a full-bridge circuit, a storage medium and a terminal, which are used to solve the problem of complicated computation of adjusting a PWM phase by using a phase-shift control algorithm in the prior art.
To achieve the above and other related objects, the present invention provides a PWM pulse control method based on a full-bridge circuit, which at least includes: sampling the output voltage in a preset modulation period to obtain a voltage sampling result, calculating the sampling result by adopting a PID (proportion integration differentiation) controller, and calculating to obtain an opening time value for an MOS (metal oxide semiconductor) tube in a full-bridge circuit; and adjusting the duty ratio of the PWM pulse according to the relationship between the preset upper limit threshold value and the preset lower limit threshold value and the opening time value.
Preferably, the full bridge circuit includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first capacitor, a second capacitor and an inductor; the first end of the first capacitor is connected with the drain electrode of the first MOS tube and the drain electrode of the fourth MOS tube, the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the source electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, the second end of the first capacitor is connected with the source electrode of the second MOS tube and the source electrode of the third MOS tube, and the second capacitor and the inductor which are connected in series are connected between the source electrode of the first MOS tube and the source electrode of the fourth MOS tube.
Preferably, the step of adjusting the duty ratio of the PWM pulse according to the relationship between the preset upper threshold and lower threshold and the on-time value includes: judging whether the opening time value is in an interval formed by the upper limit threshold value and the lower limit threshold value; if yes, adjusting the duty ratio of the PWM pulse according to the opening time value.
Preferably, when the on-time value is not located in the interval formed by the upper threshold and the lower threshold, the method further includes: obtaining a first absolute value corresponding to the difference between the opening time value and the upper limit threshold value and a second absolute value corresponding to the difference between the opening time value and the lower limit threshold value; judging whether the first absolute value is larger than the second absolute value; if so, adjusting the duty ratio of the PWM pulse according to the upper limit threshold value; if not, the duty ratio of the PWM pulse is adjusted according to the lower limit threshold value.
Preferably, before the determining whether the first absolute value is greater than the second absolute value, the method further comprises: acquiring the smaller value of the first absolute value and the second absolute value; judging whether the smaller value is larger than a preset threshold value or not; if so, the step of judging whether the first absolute value is larger than the second absolute value is not executed.
Preferably, the duty ratio of the PWM pulse is adjusted according to the on-time value, and the gate on-time of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor is adjusted according to the on-time value.
Preferably, the upper threshold is 4.917us, and the lower threshold is 0.083us
In addition, the embodiment of the invention also provides a step of implementing any one of the PWM pulse control methods based on the full-bridge circuit when the program is executed by the processor.
And, a terminal comprising a processor memory having stored thereon program instructions, characterized in that: the processor runs the program instructions to realize the steps in any one of the PWM pulse control methods based on the full-bridge circuit,
as described above, the PWM pulse control method based on the full-bridge circuit, the storage medium and the terminal according to the present invention have the following advantages: 1. in the adjusting process, the phase shift calculation of the driving waveforms of the upper tube and the lower tube is not needed any more, only the opening time (Ton) of the upper tube is related to the gain of the circuit, and the control algorithm is greatly simplified and reliable; 2. the lower tube driving of the two groups of bridge arms is kept unchanged, and the upper tube driving is completely symmetrical (without the problems of lag and lead), so that the problem that the ZVS of the power tube is difficult to realize under the light-load working condition is solved.
Drawings
Fig. 1 is a flow chart of a control method based on a full bridge circuit according to the present invention.
Fig. 2 is a circuit diagram of a full bridge circuit according to the present invention.
FIG. 3 is a timing diagram of a phase shift control algorithm in the prior art.
Fig. 4 is a timing diagram illustrating the PWM pulse duty ratio of the full-bridge circuit based control method according to the present invention.
Description of the element reference numerals
S101 to S103
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, a schematic flow chart of a PWM pulse control method based on a full-bridge circuit according to an embodiment of the present invention is provided, where the PWM pulse control method based on the full-bridge circuit at least includes:
s101, sampling the output voltage in a preset modulation period to obtain a voltage sampling result.
It should be noted that, in the embodiment of the present invention, the adjusting process of the control method based on the full-bridge circuit is periodic, so that the process of sampling the output voltage is also periodic, and the period of sampling the voltage is inevitably smaller than the adjusting period of the whole full-bridge circuit, and the time corresponding to the specific period, which is not specifically limited herein.
It will be understood by those skilled in the art that sampling the output voltage will result in a plurality of discrete sampled voltage values, and in particular, the sampling time of the discrete voltage sampled values may be recorded, such as u (t1), u (t2), and so on.
And S102, calculating the sampling result by adopting a PID controller, and calculating to obtain a turn-on time value of the MOS tube in the full-bridge circuit.
It should be noted that, in the industrial production process, process variables such as temperature, pressure, flow rate, liquid level, etc. of the production device are often required to be maintained at a certain value or changed according to a certain rule so as to meet the requirements of the production process. The PID controller adjusts the deviation of the whole control system according to the PID control principle, so that the actual value of the controlled variable is consistent with the preset value required by the process. Different control laws are suitable for different production processes, and the corresponding control laws must be reasonably selected, otherwise the PID controller cannot achieve the expected control effect. Specifically, a control loop includes three parts: the controller determines a determination by an output device in response to the controller obtaining a measurement from the sensor and then subtracting the measurement from the desired measurement to obtain an error. The error is then used to calculate a correction to the system as an input result so that the system can eliminate the error from its output result. In a PID loop, the correction algorithm includes three steps, eliminating the current error, averaging the past error, and predicting the future error through the change of the error.
Specifically, a calculation formula of the PID controller is adopted, which is specifically expressed as:
wherein err in the formula refers to a difference value between an output voltage sampling value and a set value. The three parts in the formula respectively refer to a proportional link, an integral link and a differential link aiming at error calculation, the three parts are added after calculation, and u (x) is final output. Specifically, u (x) and the on-time of the MOS transistor are in a positive correlation quantity, the on-time is obtained by a positive correlation coefficient K, and if T1 is the on-time value, u (x) is KT 1.
And S103, adjusting the duty ratio of the PWM pulse according to the relationship between the preset upper limit threshold value and the preset lower limit threshold value and the opening time value.
Specifically, in the embodiment of the present invention, the step of adjusting the duty ratio of the PWM pulse according to the relationship between the preset upper threshold and the preset lower threshold and the on-time value includes: judging whether the opening time value is in an interval formed by the upper limit threshold value and the lower limit threshold value; if yes, adjusting the duty ratio of the PWM pulse according to the opening time value. Assuming that the calculated on-time value is 2.15us, the preset upper threshold value is 3.80us, and the preset lower threshold value is 0.09us, since 2.15us is smaller than 3.80us and larger than 0.09us, the duty ratio of the PWM pulse is adjusted by the on-time value of 2.15 us.
In addition, if the value of the on-time is not in the interval formed by the preset upper threshold and the preset lower threshold, the embodiment of the present invention further provides a solution, where the method further includes: obtaining a first absolute value corresponding to the difference between the opening time value and the upper limit threshold value and a second absolute value corresponding to the difference between the opening time value and the lower limit threshold value; judging whether the first absolute value is larger than the second absolute value; if so, adjusting the duty ratio of the PWM pulse according to the upper limit threshold value; if not, the duty ratio of the PWM pulse is adjusted according to the lower limit threshold value.
It will be appreciated that by comparing the first and second absolute values, it is possible to determine whether the on-time value is adjacent to the upper threshold or adjacent to the lower threshold, and if so, to adjust the duty cycle of the PWM pulse with the threshold at that end.
In order to solve the problems of the PID controller computing value overflowing during the operation, before the determining whether the first absolute value is greater than the second absolute value, the method further includes: acquiring the smaller value of the first absolute value and the second absolute value; judging whether the smaller value is larger than a preset threshold value or not; if so, the step of judging whether the first absolute value is larger than the second absolute value is not executed. The adjustment of the duty cycle of the PWM pulse may be performed when the minimum value of the first absolute value and the second absolute value is not greater than the preset threshold by comparing the minimum value with the preset threshold, and at this time, since the comparison of the first absolute value and the second absolute value has been performed, the duty cycle of the PWM pulse may be adjusted directly according to whether it is determined to be the upper limit threshold or the lower limit threshold.
In a specific implementation manner of the present invention, when the switching period is 100KHz (corresponding to a period of 10us), the upper threshold is 4.917us, and the lower threshold is 0.083 us.
As shown in fig. 2, in the embodiment of the present invention, the full bridge circuit includes: the circuit comprises a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, a fourth MOS transistor T4, a first capacitor C1, a second capacitor C2 and an inductor L; the first end of the first capacitor C1 is connected to the drain of the first MOS transistor T1 and the drain of the fourth MOS transistor T4, the source of the first MOS transistor T1 is connected to the drain of the second MOS transistor T2, the source of the fourth MOS transistor T4 is connected to the drain of the third MOS transistor T3, the second end of the first capacitor C1 is connected to the source of the second MOS transistor T2 and the source of the third MOS transistor T3, and the second capacitor C2 and the inductor L which are connected in series are connected between the source of the first MOS transistor T1 and the source of the fourth MOS transistor T4. The gates of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 are respectively adjusted by the PWM pulse duty ratio, and the PWM pulse duty ratio is mainly adjusted by the gate on time of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4. As shown in fig. 3, the phase control algorithm of the prior art adjusts the duty ratio by adjusting the phase of VT1 and VT4, VT2 and VT3 drives, and the more VT1 and VT4, and VT2 and VT3 conduct the overlapping portions, the larger the duty ratio, the less the overlapping portion, and the smaller the duty ratio. The relative phases of VT1 and VT4, VT2 and VT3 need to be controlled in real time, the phases need to be adjusted in real time according to the magnitude of the output load, dead time of VT1 and VT2, VT2 and VT2 needs to be ensured, and the algorithm and the control strategy are complex, so the calculation complexity is high. It can be understood that T2 and T3 are down tubes, and the driving is PWM with a fixed duty ratio of 50%, and no further adjustment is needed, and only the driving of the upper tubes T1 and T4 (due to the symmetrical arrangement of MOS tubes, only the driving of the upper tubes T2 and T3 may be dynamically adjusted).
In the embodiment of the invention, the specific adjusting process is as shown in fig. 4, the driving waveform of the lower tube is fixed, only the driving waveform of the upper tube is dynamically adjusted according to the result of closed-loop control, the on-time is adjusted in the shaded area shown in fig. 4, and the dead time is the dead time of the rising edge and the falling edge reserved for driving the upper tube. Because the dead time of the driving of the lower tubes (T2 and T3) and the dead time of the upper tubes (T1 and T4) are fixed values, no extra operation amount is needed to be added in the whole adjusting process for dynamic adjustment, and the software control process is greatly simplified.
In addition, as can be understood by those skilled in the art, in the control idea of the common phase-shifted full bridge, the delay arm may have a situation that it is difficult to realize the ZVS switching on the power tube under the light-load working condition, and in the method, the lower tube drives of the two sets of bridge arms are all kept unchanged, and the upper tube drives are completely symmetrical (there is no problem of lag or lead), so that the problem that the ZVS is difficult to realize under the light-load working condition is avoided.
In summary, according to the PWM pulse control method based on the full-bridge circuit, the storage medium and the terminal provided by the present invention, the output voltage is sampled within the preset modulation period to obtain the voltage sampling result, and the PID controller is adopted to calculate the sampling result, so as to calculate the on-time value for the MOS transistor in the full-bridge circuit; and adjusting the duty ratio of the PWM pulse according to the relationship between the preset upper limit threshold value and the preset lower limit threshold value and the opening time value. Therefore, in the adjusting process, the phase shift calculation of the driving waveforms of the upper tube and the lower tube is not needed any more, only the turn-on time (Ton) of the upper tube (or only the lower tube) is related to the gain of the circuit, and the control algorithm is greatly simplified and reliable; 2. the lower tube driving of the two sets of bridge arms is kept unchanged, and the upper tube driving is completely symmetrical (no lag or lead problem exists), so that the problem that the ZVS (zero voltage switching-on) of the power tube is difficult to realize under the light-load working condition is solved, the ZVS characteristic of the MOS tube is realized, and the electric energy conversion efficiency is improved by effectively reducing the switching loss of the MOS tube. The invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A PWM pulse control method based on a full-bridge circuit is characterized by at least comprising the following steps:
sampling the output voltage in a preset modulation period to obtain a voltage sampling result, wherein the voltage sampling data are discrete sampling data;
the output voltage is periodically sampled, and the sampling period is less than the regulation period of the whole full-bridge circuit;
calculating the sampling result by adopting a PID controller, and calculating to obtain an opening time value for an MOS tube in the full-bridge circuit;
the value u (x) of the on-time is obtained according to the following formula:
the method comprises the following steps that (1) err in a formula represents a difference value between an output voltage sampling value and a set value, and err (t) in the formula refers to a proportion link aiming at error calculation; in said formula
Refers to an integration element for error calculation; in said formula
Refers to the differentiation element for error calculation;
the method comprises the following steps of adjusting the duty ratio of PWM pulses according to the relation between a preset upper limit threshold value and a preset lower limit threshold value and the opening time value, and adjusting the duty ratio of the PWM pulses according to the relation between the preset upper limit threshold value and the preset lower limit threshold value and the opening time value, wherein the steps comprise: judging whether the opening time value is in an interval formed by the upper limit threshold value and the lower limit threshold value; if so, adjusting the duty ratio of the PWM pulse according to the opening time value;
when the on-time value is not in the interval formed by the upper threshold and the lower threshold, the method further comprises:
obtaining a first absolute value corresponding to the difference between the opening time value and the upper limit threshold value and a second absolute value corresponding to the difference between the opening time value and the lower limit threshold value;
judging whether the first absolute value is larger than the second absolute value;
if so, adjusting the duty ratio of the PWM pulse according to the upper limit threshold value;
if not, adjusting the duty ratio of the PWM pulse according to the lower limit threshold;
prior to said determining whether said first absolute value is greater than said second absolute value, said method further comprises:
acquiring the smaller value of the first absolute value and the second absolute value;
judging whether the smaller value is larger than a preset threshold value or not;
if so, the step of judging whether the first absolute value is larger than the second absolute value is not executed.
2. The full-bridge circuit-based PWM pulse control method of claim 1, wherein said full-bridge circuit comprises: the MOS transistor comprises a first MOS transistor (T1), a second MOS transistor (T2), a third MOS transistor (T3), a fourth MOS transistor (T4), a first capacitor (C1), a second capacitor (C2) and an inductor (L);
the first end of the first capacitor (C1) is connected with the drain of the first MOS tube (T1) and the drain of the fourth MOS tube (T4), the source of the first MOS tube (T1) is connected with the drain of the second MOS tube (T2), the source of the fourth MOS tube (T4) is connected with the drain of the third MOS tube (T3), the second end of the first capacitor (C1) is connected with the source of the second MOS tube (T2) and the source of the third MOS tube (T3), and the second capacitor (C2) and the inductor (L) which are connected in series are connected between the source of the first MOS tube (T1) and the source of the fourth MOS tube (T4).
3. The full-bridge circuit-based PWM pulse control method of claim 2, wherein said adjusting the duty cycle of PWM pulses according to said on-time value,
and adjusting the grid conduction time of the first MOS transistor (T1), the second MOS transistor (T2), the third MOS transistor (T3) and the fourth MOS transistor (T4) according to the turn-on time value.
4. The full-bridge circuit-based PWM pulse control method according to any one of claims 1-3, wherein said upper threshold is 4.917us, and said lower threshold is 0.083 us.
5. A readable storage medium, on which a computer program is stored, wherein the program, when executed by a processor, implements the steps of the full bridge circuit based PWM pulse control method according to any one of claims 1 to 4.
6. A terminal comprising a processor memory having stored thereon program instructions, characterized in that: the processor runs the program instructions to realize the steps in the PWM pulse control method based on the full bridge circuit according to any one of 1 to 4.
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| CN103259443A (en) * | 2013-05-23 | 2013-08-21 | 吕莹 | Limited dual-polarity-controlled full bridge inverter |
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| CN102611287A (en) * | 2012-03-12 | 2012-07-25 | 重庆环亚电子有限公司 | Method for realizing full-bridge ZVS (Zero Voltage Switch) and ZCS (Zero Current Switch) drive and circuit thereof |
| CN103219911A (en) * | 2013-04-10 | 2013-07-24 | 卧龙电气集团股份有限公司 | Off-network inverter based on dead beat control method and working method thereof |
| CN103259443A (en) * | 2013-05-23 | 2013-08-21 | 吕莹 | Limited dual-polarity-controlled full bridge inverter |
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