CN108538331B - First read strategy in memory - Google Patents

Abstract

There is provided an apparatus, comprising: a block of memory cells; and control circuitry configured to perform an operation involving sensing of selected memory cells of the block in response to a command to perform the operation, and after the operation, perform a soft erase of the block of memory cells. Also disclosed is a method: applying a pass voltage to unselected memory cells of the connected set of memory cells, applying a sense voltage to selected memory cells of the connected set of memory cells; sensing the selected memory cell while applying the sensing voltage; after sensing, driving the control gate voltage of the unselected memory cells from the pass voltage to a lower level, resulting in a downward coupling of the voltage of the channels of the connected set of memory cells; generating a hole current in the channel to neutralize the voltage of the channel when the control gate voltage is driven at a lower level; and floating the control gate voltage of the unselected memory cells after the hole current is generated.

Description

First read strategy in memory

The present application is a divisional application of an invention patent application having an application number of 201810149225.1 and an invention name of "first reading countermeasure in memory" filed on 13/2/2018.

Technical Field

The present technology relates to the operation of memory devices.

Background

The use of semiconductor memory devices in various electronic devices has become increasingly popular. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

Charge storage materials (such as floating gates) or charge trapping materials may be used in such memory devices to store charge representing data states. The charge trapping material may be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is a bit-cost scalable (BiCS) architecture, which includes a stack of alternating conductive and dielectric layers.

The memory device includes memory cells, which may be arranged in strings, for example, with select gate transistors provided at ends of the strings to selectively connect channels of the strings to source lines or bit lines. However, operating such memory devices presents various challenges.

Disclosure of Invention

In one embodiment, an apparatus comprises: a block of memory cells connected to a set of word lines; a voltage detector connected to one or more word lines of the set of word lines, the voltage detector configured to perform an evaluation of a voltage of the one or more word lines; and control circuitry in communication with the voltage detector, the control circuitry configured to determine a set of read voltages for reading selected memory cells in a block based on the evaluation.

One method comprises the following steps: in response to a read command directed to a selected memory cell of the block, prior to reading the selected memory cell, determining whether a condition for applying a pre-read voltage pulse to the selected memory cell is satisfied; if the condition is satisfied, applying a pre-read voltage pulse to the selected memory cell prior to reading the selected memory cell; and if the condition is not satisfied, reading the selected memory cell without applying the pre-read voltage pulse to the selected memory cell.

Another related apparatus contains means for performing each of the above steps. The aforementioned components may, for example, comprise components of the memory device 100 of fig. 1A and 2. The power control module 116, for example, controls the power and voltages applied to the word lines, select gate lines, and bit lines during memory operations. Further, the above-described components may include the components of fig. 24A and 24B, including voltage drivers, switches, and pass transistors. The components may also include any of the control circuits in fig. 1A and 2, such as control circuit 110 and controller 122.

In another embodiment, an apparatus comprises: timing means for periodically determining when to refresh a threshold voltage of a set of memory cells, the set of memory cells including one or more blocks of memory cells; and means for applying voltage pulses to a set of word lines connected to the memory cells of each of the one or more blocks in response to the timing means.

In another embodiment, an apparatus comprises: a block of memory cells; and control circuitry configured to sense selected memory cells of the block in response to a read or program command directed to the selected memory cells, followed by performing a soft erase of the block of memory cells.

Drawings

FIG. 1A is a block diagram of an exemplary memory device.

FIG. 1B depicts an exemplary memory cell 200.

Fig. 1C depicts various features disclosed herein.

FIG. 1D illustrates an example of the temperature sensing circuit 115 of FIG. 1A.

FIG. 2 is a block diagram of an exemplary memory device 100 depicting additional details of the controller 122.

Fig. 3 is a perspective view of a memory device 600 including a set of blocks in an exemplary 3D configuration of the memory structure 126 of fig. 1.

Fig. 4 depicts an exemplary cross-sectional view of a portion of one of the blocks of fig. 3.

Figure 5 depicts a graph of memory hole/pillar diameters in the stack of figure 4.

Fig. 6 depicts a close-up view of region 622 of the stack of fig. 4.

Fig. 7A depicts an exemplary view of NAND strings in a sub-block in a 3D configuration according to fig. 4.

Fig. 7B depicts word lines and SGD layers in the exemplary block set according to fig. 4.

FIG. 8A depicts an exemplary Vth distribution of memory cells under a first read condition compared to a second read condition, where eight data states are used.

FIG. 8B depicts an exemplary bit sequence for the lower, middle, and upper pages of data for the Vth distribution of FIG. 8A, and associated read voltages.

Fig. 9 depicts waveforms for an exemplary programming operation.

FIG. 10A depicts a graph of example waveforms in a programming operation, showing the upward coupling of word line voltages.

Fig. 10B shows a graph corresponding to the channel voltage (Vch) of fig. 10A.

FIG. 10C depicts a graph of exemplary waveforms in a read operation, showing the upward coupling of word line voltages.

Fig. 10D shows a graph of channel voltage (Vch) corresponding to fig. 10C.

FIG. 10E depicts the waveform of FIG. 10C, showing the decay of the upward coupling voltage of the word line.

FIG. 10F depicts a graph of channel voltage according to FIG. 10E.

FIG. 10G depicts a graph of Vth of memory cells connected to an upward-coupled word line according to FIGS. 10E and 10F.

FIG. 11A depicts the control gate and channel voltages on a memory cell acting as a capacitor when the control gate voltage is lowered in a sense operation.

FIG. 11B depicts a portion of a memory cell showing injection of electrons into the charge trapping region during weak programming.

FIG. 12A depicts an example memory string configuration just prior to discharging the word lines at the end of a sense operation.

FIG. 12B depicts the configuration of an exemplary memory string just after the word lines are discharged at the end of the sense operation.

FIG. 12C depicts an exemplary memory string configuration when the word lines are coupled up through the channel.

FIG. 12D depicts an exemplary memory string configuration when the word lines have completed coupling up.

Fig. 13A depicts an exemplary process according to block 10 in fig. 1C.

FIG. 13B depicts a graph of shift in Vth versus time for different data states.

FIG. 13C depicts a graph of read voltage versus trend of detected word line voltage.

FIG. 13D depicts a graph of read voltage versus detected word line voltage, where two sets of read voltages are used in the exemplary embodiment of FIG. 13C.

FIG. 13E depicts another exemplary process according to block 10 in FIG. 1C.

FIG. 14A depicts an exemplary process according to block 11 in FIG. 1C.

FIG. 14B depicts another exemplary process according to block 11 in FIG. 1C.

FIG. 15A depicts a graph of exemplary waveforms in a read operation similar to FIG. 10C, where a pre-read voltage pulse is applied prior to the read operation.

Fig. 15B shows a graph corresponding to the channel voltage (Vch) of fig. 15A.

FIG. 15C depicts a plot of pre-read voltage pulse duration versus time since the last sense operation in accordance with step 1402b of the process of FIG. 14A.

FIG. 15D depicts a plot of pre-read voltage pulse duration versus detected word line voltage in accordance with step 1402c of the process of FIG. 14A.

FIG. 15E depicts a plot of pre-read voltage pulse duration versus temperature according to step 1402d of the process of FIG. 14A.

FIG. 15F depicts a graph of error count versus programming pulse width according to the process of FIG. 14A.

FIG. 16A depicts an exemplary process according to block 12 in FIG. 1C.

FIG. 16B depicts a graph of periodic voltage pulses according to the process of FIG. 16A.

FIG. 16C is a graph showing the channel voltage according to FIG. 16B.

Fig. 16D depicts a graph of pulse period versus temperature according to block 1602a of fig. 16A.

FIG. 17A depicts an exemplary process according to block 13 in FIG. 1C.

FIG. 17B depicts a graph of an exemplary erase voltage applied to a substrate during a normal erase operation.

FIG. 17C depicts a graph of verify voltages applied to word lines in a block according to FIG. 17B.

Fig. 18A depicts the configuration of the example memory string 1200 of fig. 12A when holes are introduced into the channel from the substrate and the channel begins to neutralize in a soft erase operation according to step 1702 of fig. 17.

FIG. 18B depicts the configuration of an exemplary memory string when the channel is fully neutralized in a soft erase operation according to step 1702 of FIGS. 17 and 18A.

FIG. 19A depicts a diagram of exemplary waveforms in a read operation followed by a soft erase.

FIG. 19B shows the channel voltage during soft erase.

FIG. 19C shows the SGS transistor voltage during soft erase.

FIG. 19D depicts the p-well voltage during soft erase.

FIG. 20A depicts the configuration of an exemplary memory string just after discharging the word lines at the end of the sense operation, where coupling is used to lower the SGD and SGS transistor voltages in a soft erase operation according to step 1702 of FIG. 17.

Fig. 20B depicts the configuration of an exemplary memory string just after discharging the word lines at the end of the sense operation, where the SGD and SGS transistor voltages are reduced using the driven negative voltage in the soft erase operation according to step 1702 of fig. 17.

Fig. 20C depicts the configuration of an exemplary memory string when holes are introduced into the channel from the SGD and SGS transistors using GIDL, and the channel begins to neutralize, in a soft erase operation according to step 1702 of fig. 17 and according to fig. 20A or 20B.

FIG. 21A depicts a graph of exemplary waveforms in a read operation followed by a soft erase, according to FIGS. 20A and 20C, in which the pass voltage is ramped down to VpassL before ramping down to 0V.

FIG. 21B depicts channel voltages during one example of soft erase.

FIG. 21C depicts SGS and/or SGD transistor voltages during one example of soft erase.

FIG. 21D depicts the p-well voltage during one example of soft erase.

FIG. 22A depicts a graph of exemplary waveforms in a read operation followed by a soft erase.

FIG. 22B depicts channel voltage during one example of soft erase.

FIG. 22C depicts SGS and/or SGD transistor voltages during one example of soft erase.

FIG. 22D depicts the p-well voltage during one example of soft erase.

Fig. 23 shows an exemplary block diagram of the sensing block 51 in the column control circuit of fig. 1A.

FIG. 24A depicts an exemplary circuit for providing voltages to a block of memory cells.

FIG. 24B depicts an exemplary circuit according to FIG. 24B for detecting word line voltage according to the process of FIG. 13A.

Fig. 25 depicts a memory device 2500 in which voltage pulses are performed for multiple die, one die at a time, according to the process of fig. 16A.

Detailed Description

Techniques are provided for improving the accuracy of read operations in memory devices. Corresponding memory devices are also provided.

In some memory devices, the memory cells are connected to one another, such as NAND strings in a block or sub-block. Each NAND string includes a number of series-connected memory cells between one or more drain-side SG transistors (SGD transistors) of the NAND string connected to the drain side of the bit line and one or more source-side SG transistors (SGs transistors) of the NAND string connected to the source side of the source line. Further, the memory cells may be arranged with a common control gate line (e.g., word line) serving as a control gate. The set of word lines extends from the source side of the block to the drain side of the block. The memory cells may be connected in other types of strings and in other ways.

The memory cells may include data memory cells capable of storing user data, and dummy or non-data memory cells incapable of storing user data. The dummy word line is connected to the dummy memory cell. One or more dummy memory cells may be provided at the drain and/or source ends of the string of memory cells to provide a gradual transition in channel gradient.

During a program operation, memory cells are programmed according to a word line programming sequence. For example, programming may begin with a word line at the source side of the block and proceed to a word line at the drain side of the block. In one approach, each word line is fully programmed before the next word line is programmed. For example, the first word line WL0 is programmed using one or more programming passes until programming is complete. Next, the second word line WL1 is programmed using one or more program passes until programming is complete, and so on. The program pass may contain a set of elevated programming voltages that are applied to the word lines in a respective program loop or program-verify iteration, such as shown in fig. 9. A verify operation may be performed after each program voltage to determine whether the memory cell has completed programming. When programming is completed for a memory cell, it can be locked out from further programming while continuing to program other memory cells in subsequent programming loops.

Memory cells may also be programmed according to a sub-block programming order, in which case memory cells in one sub-block or portion of a block are programmed before memory cells in another sub-block are programmed.

Each memory cell may be associated with a data state according to write data in a program command. Based on its data state, the memory cell will remain in the erased state or programmed to the programmed data state. For example, in a one-bit-per-cell memory device, there are two data states, including an erased state and a programmed state. In a two-bit per cell memory device, there are four data states, including the erased state and the three higher data states, referred to as the A, B and C data states. In a three-bit-per-cell memory device, there are eight data states, including the erased state and seven higher data states, referred to as the A, B, C, D, E, F, and G data states (see FIG. 8A). In a four-bit-per-cell memory device, there are sixteen data states, including an erased state and fifteen higher data states. The data states may be referred to as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15 data states, where S0 is the erased state.

After the memory cells are programmed, the data may be read back in a read operation. The read operation may involve applying a series of read voltages to the word line while the sense circuit determines whether a cell connected to the word line is in a conductive or non-conductive state. If the cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. The read voltage is set to a level that is expected to be between the threshold voltage levels of adjacent data states.

However, it has been observed that the Vth of a memory cell can vary depending on when a read operation occurs. For example, Vth may vary among memory cells depending on the upward coupling state of the word line when a read operation occurs. A "first read" condition may be defined in which the word line is not coupled upward, and a "second read" condition may be defined in which the word line is coupled upward.

After a power-up event in the memory device, the memory cell may be in a first read condition. When the memory device is powered up for use, an operation to check for bad blocks may occur. This operation involves applying 0V or other low voltage to the word line. Thus, any up-coupling of the word line voltage is discharged.

When the word line voltage is set to a low level, the word line may also discharge in the block. This may occur when an operation is performed in another block while that block is inactive. Because the word line discharges over time, the cell may also be in the first read condition after a long time has elapsed after the last sense operation. The upward coupling of the word lines causes Vth to shift among cells due to inadvertent programming or erasing. This Vth does not occur because the word line is not significantly coupled up when in the first read condition.

When a read occurs a short time (e.g., a few seconds or minutes) after the last sensing operation, the cell may be in a second read condition. Because the word line is relatively strongly coupled upward when in the second read condition, there is programming or erasing of the cell due to the word line voltage, and a corresponding shift in Vth. In particular, a word line having an upward coupling voltage may result in weak programming of cells having a relatively low Vth (lower than the upward coupling voltage) (e.g., cells in a lower programmed data state), resulting in Vth shifts up for these cells. Furthermore, there may be a weak erase of cells with a relatively high Vth (above the upward coupling voltage) (e.g., cells in a higher programmed data state), resulting in a Vth shift down for these cells.

As the word line discharges, the cell gradually transitions from the second read condition to the first read condition over time (e.g., one hour).

The upward coupling of the word line voltage is caused by the voltage of a sensing operation, such as a verify operation occurring in connection with a program operation, or a read operation occurring after the program operation is completed. Sensing of a cell involves applying a sensing voltage (e.g., a read/verify voltage) to a selected word line. At the same time, a read pass voltage is applied to the unselected word lines, and then stepped down. This downward stepping temporarily lowers the channel voltage due to capacitive coupling. Also due to capacitive coupling, this causes a rise or up-coupling of the word line voltage when the channel voltage rises back to its nominal level. For cells in a lower data state, the Vth gradually decreases as electrons trapped in the charge trapping material of the cell are released and return to the channel. For cells in a higher data state, Vth gradually rises as electrons are removed from the channel. See fig. 8A.

When a read operation occurs, it is not known whether the cell is in the first read condition or the second read condition, or perhaps somewhere in between. One approach is to track the elapsed time since a power-up event or a previous sensing operation. However, this elapsed time may not accurately indicate whether or to what extent the word lines are coupled upward, since other factors such as environmental factors and process variations may be relevant. Furthermore, each block would need to be tracked separately.

The techniques provided herein address the above and other issues.

Fig. 1C depicts various features disclosed herein. The first feature includes detecting the up-coupled state of the word line and setting the read voltage accordingly (block 10). The second feature includes applying a pre-read voltage pulse just prior to the read operation (block 11). A third feature includes periodically applying voltage pulses to all word lines in the block (block 12). This may occur independently of a read command and involve refreshing the threshold voltage of the memory cell to a second read condition. The fourth feature includes performing a soft erase (block 13) just after the read or program operation.

Various other features and advantages are described below.

FIG. 1A is a block diagram of an exemplary memory device. A memory device 100, such as a non-volatile storage system, may include one or more memory die 108. Memory die 108 includes a memory structure 126 of memory cells (such as an array of memory cells), control circuitry 110, and read/write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read/write circuits 128 contain multiple sense blocks 51, 52, … …, 53 (sense circuits) and allow a page of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory die 108. The controller may be separate from the memory die. Commands and data may be transferred between host 140 and controller 122 via data bus 120, and between the controller and the one or more memory die 108 via lines 118.

The memory structure may be 2D or 3D. The memory structure may include one or more arrays of memory cells, including a 3D array. The memory structure may include a monolithic 3D memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, without an intervening substrate. The memory structure may include any type of non-volatile memory that is monolithically formed into one or more physical levels of an array of memory cells having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with operation of the memory cells, whether the associated circuitry is above or within the substrate.

Control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. As discussed further below, the state machine may contain a clock 112a to determine the elapsed time since the last sense operation. As described further below, a storage area 113 may be provided, for example, for a read voltage set. In general, the memory area may store operating parameters and software/code. As an example, the timer 113a may be used to determine when to periodically apply voltage pulses to the word line, as described below with respect to fig. 13E and 16A. A temperature sensor 115 may also be provided. See fig. 1D.

In one example, the state machine is programmable by software. In other embodiments, the state machine is implemented entirely in hardware (e.g., circuitry) without software.

The on-chip address decoder 114 provides an address interface between that used by the host or a memory controller to the hardware address used by the decoders 124 and 132. The power control module 116 controls the power and voltages applied to the word lines, select gate lines, and bit lines during memory operations. It may include drivers for word lines, SGS and SGD transistors, and source lines. See fig. 24. In one approach, the sense block may include a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

In some embodiments, some of the components may be combined. In various designs, one or more of the components (alone or in combination), other than the memory structure 126, may be conceived to be at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one or combination of the following: control circuitry 110, state machine 112, decoders 114 and 132, power control module 116, sense blocks 51, 52, … …, 53, read/write circuits 128, controller 122, and the like.

The off-chip controller 122, which in one embodiment is a circuit, may include a processor 122c, storage devices (memory) such as a ROM 122a and a RAM 122b, and an Error Correction Code (ECC) engine 245. The ECC engine may correct several read errors.

A memory interface 122d may also be provided. A memory interface in communication with ROM, RAM, and the processor is circuitry that provides an electrical interface between the controller and the memory die. For example, the memory interface may change the format or timing of signals, provide buffers, isolate from surges, latch I/O, and so forth. The processor may issue commands to control circuitry 110 (or any other component of the memory die) via memory interface 122 d.

The storage device includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor may access the code from a storage 126a of the memory structure (such as a reserved area of memory cells in one or more word lines).

For example, the controller may use code to access the memory structure, such as for program, read, and erase operations. The code may include boot code and control code (e.g., an instruction set). Boot code is software that initializes the controller and enables the controller to access the memory structure during a boot or startup process. The controller may use code to control one or more memory structures. Upon power up, the processor 122c retrieves boot code from the ROM 122a or the storage device 126a for execution, and the boot code initializes system components and loads control code into the RAM 122 b. Once the control code is loaded into RAM, it is executed by the processor. The control code contains drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

In general, the control code may contain instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and to provide voltage waveforms including those discussed further below. The control circuitry may be configured to execute instructions to perform the functions described herein.

In one example, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid state memory) that stores processor-readable code (e.g., software) to program the one or more processors to perform the methods described herein. The host may also contain additional system memory, one or more input/output interfaces, and/or one or more input/output devices in communication with one or more processors.

Other types of non-volatile memory besides NAND flash memory may also be used.

Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), and other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

The memory device may be formed of passive and/or active elements in any combination. As non-limiting examples, the passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching memory elements such as antifuses or phase change materials, and optionally steering elements such as diodes or transistors. Also by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

The plurality of memory elements may be configured such that they are connected in series or such that each element is individually accessible. As a non-limiting example, flash memory devices of NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of transistors connected in series, including a memory cell and SG transistors.

A NAND memory array may be configured such that the array is comprised of multiple strings of memory, where a string is comprised of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, the memory elements may be configured such that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and the memory elements may be configured in other ways.

The semiconductor memory elements located within and/or on the substrate may be arranged in two or three dimensions, such as a 2D memory structure or a 3D memory structure.

In a 2D memory structure, the semiconductor memory elements are arranged in a single plane or as a single memory device level. Typically, in 2D memory structures, the memory elements are arranged in a plane (e.g., a plane in the x-y direction) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate may be a wafer on or in which layers of the memory element are formed, or it may be a carrier substrate that is attached to the memory element after formation. As a non-limiting example, the substrate may comprise a semiconductor such as silicon.

The memory elements may be arranged in an ordered array in a single memory device level, such as a plurality of rows and/or columns. However, the memory elements may be arranged in an irregular or non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

The 3D memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, forming a structure in three dimensions (i.e., in x, y, and z directions, where the z direction is substantially perpendicular to a major surface of the substrate and the x and y directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, the 3D memory structure may be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, the 3D memory array may be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to a major surface of the substrate (i.e., in the y-direction)), with each column having a plurality of memory elements. The columns may be arranged in a 2D configuration (e.g., in an x-y plane), resulting in a 3D arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions may also constitute a 3D memory array.

As a non-limiting example, in a 3D NAND memory array, the memory elements can be coupled together to form NAND strings within a single level (e.g., x-y) memory device level. Alternatively, the memory elements can be coupled together to form a vertical NAND string that traverses multiple horizontal memory device levels. Other 3D configurations are contemplated in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements spanning multiple memory levels. The 3D memory array may also be designed in a NOR configuration and a ReRAM configuration.

Typically, in monolithic 3D memory arrays, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may comprise a semiconductor such as silicon. In monolithic 3D arrays, the layers making up each memory device level of the array are typically formed on the layers of the memory device levels below the array. However, the layers of adjacent memory device levels of the monolithic 3D memory array may be shared, or have intervening layers between memory device levels.

The 2D array may be formed separately and then packaged together to form a non-monolithic memory device with multi-layer memory. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels one on top of the other. The substrate may be thinned or removed from its memory device level prior to stacking, but since the memory device level is initially formed over a separate substrate, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

The operation of and communication with the memory elements typically requires associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. This associated circuitry may be on the same substrate as the memory element and/or on a separate substrate. For example, the controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.

Those skilled in the art will recognize that the present technology is not limited to the 2D and 3D exemplary structures described, but rather covers all relevant memory structures as described herein and as understood by those skilled in the art to the spirit and scope of the present technology.

FIG. 1B depicts an exemplary memory cell 200. The memory cell includes a control gate CG receiving a word line voltage Vwl, a drain at voltage Vd, a source at voltage Vs, and a channel at voltage Vch.

FIG. 1D illustrates an example of the temperature sensing circuit 115 of FIG. 1A. The circuit includes pmosfets 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 denote currents. Voutput is a temperature-based output voltage provided to analog-to-digital (ADC) converter 129. Vbg is a temperature dependent voltage. Voltage level generation circuit 135 uses Vbg to set a number of voltage levels. For example, the reference voltage may be divided down into several levels by a resistive voltage divider circuit.

The ADC compares Voutput with the voltage levels and selects the closest match among the voltage levels, outputting the corresponding digital value (VTemp) to the processor. This is data indicative of the temperature of the memory device. In one approach, the ROM fuse 123 stores data that relates the matching voltage level to temperature. The processor then uses the temperature to set a temperature-based parameter in the memory device.

Vbg is obtained by adding the base-emitter voltage (Vbe) across the transistor 131b to the voltage drop across the resistor R2. The bipolar transistor 133a has a larger area (N times) than the transistor 133 b. The PMOS transistors 131a and 131b are equal in size and arranged in a current mirror configuration such that the currents I1 and I2 are substantially equal. We know that Vbg ═ Vbe + R2 × I2 and I1 ═ Ve/R1, so that I2 ═ Ve/R1. Thus, Vbg ═ Vbe + R2 × kT ln (N)/R1 × q, where T is temperature, k is boltzmann's constant, and q is the unit of charge. The source of the transistor 134 is connected to the supply voltage Vdd, and the node between the drain of the transistor and the resistor R3 is the output voltage Voutput. The gate of the transistor 134 is connected to the same terminal as the gates of the transistors 131a and 131b, and the current through the transistor 134 mirrors the current through the transistors 131a and 131 b.

FIG. 2 is a block diagram of an exemplary memory device 100 depicting additional details of the controller 122. As used herein, a flash memory controller is a device that manages data stored on a flash memory and communicates with a host, such as a computer or electronic device. The flash memory controller may have various functions in addition to the specific functions described herein. For example, a flash memory controller may format the flash memory to ensure that the memory is operating correctly, map out bad flash memory cells, and allocate spare memory cells to replace future failed cells. Portions of the spare cells may be used to hold firmware to operate the flash memory controller and implement other features. In operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to which data is to be read/written, the flash memory controller may translate the logical address received from the host into a physical address in the flash memory. (alternatively, the host may provide the physical address). The flash memory controller may also perform various memory management functions such as, but not limited to, wear leveling (spreading writes to avoid wear of particular blocks of memory that are repeatedly written) and garbage collection (after a block is full, only moving valid pages of data to a new block so that a full block can be erased and reused).

The interface between controller 122 and non-volatile memory die 108 may be any suitable flash interface. In one example, the memory device 100 may be a card-based system, such as a Secure Digital (SD) or micro-SD card. In an alternative embodiment, the memory system may be part of an embedded memory system. For example, flash memory may be embedded in a host, such as in the form of a Solid State Disk (SSD) drive installed in a personal computer.

In some embodiments, memory device 100 includes a single channel between controller 122 and non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel.

The controller 122 includes a front-end module 208 that interfaces with a host, a back-end module 210 that interfaces with one or more non-volatile memory die 108, and various other modules that perform the functions described in detail below.

For example, the components of the controller may take the form of: a packaged functional hardware unit (e.g., a circuit) designed for use with other components, a portion of program code (e.g., software or firmware) executable by a processor (e.g., a microprocessor or processing circuitry that typically performs a particular one of the associated functions), or self-contained hardware or software components that interface with a larger system. For example, each module may contain an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, a gate, or any other type of hardware or combination thereof. Alternatively or additionally, each module may comprise software stored in a processor readable device (e.g., memory) to program the processor to cause the controller to perform the functions described herein. The architecture shown in fig. 2 is an exemplary embodiment that may (or may not) use components (e.g., RAM, ROM, processor, interfaces) of the controller 122 illustrated in fig. 1A.

The controller 122 may include a repair circuit (repair circuit) 212 for repairing memory cells or blocks of memory. Repair may include refreshing data about its current location or reprogramming data into a new word line or block as part of performing unstable (erratic) word line maintenance, as described below.

Referring again to the modules of controller 122, buffer manager/bus controller 214 manages buffers in Random Access Memory (RAM)216 and controls internal bus arbitration (arbitration) of controller 122. The RAM may include DRAM and/or SRAM. DRAM or dynamic random access memory is a type of semiconductor memory in which the memory stores in the form of a charge. Each memory cell in a DRAM is made of a transistor and a capacitor. Data is stored in the capacitor. The capacitor discharges charges due to leakage, and thus the DRAM is a volatile device. To retain data in memory, the device must be refreshed regularly. In contrast, an SRAM or SRAM will retain the value as long as power is supplied.

A Read Only Memory (ROM)218 stores system boot code. Although illustrated in fig. 2 as being located separate from the controller, in other embodiments, one or both of the RAM 216 and the ROM 218 may be located in the controller. In other embodiments, portions of both RAM and ROM may be located within controller 122 and external to the controller. Further, in some embodiments, controller 122, RAM 216, and ROM 218 may be located on separate semiconductor die.

The front end module 208 includes a host interface 220 and a physical layer interface (PHY)222 that provides an electrical interface with a host or a next level bank controller. The choice of the type of host interface 220 may depend on the type of memory used. Examples of host interface 220 include, but are not limited to, SATA express, SAS, fibre channel, USB, PCIe, and NVMe. The host interface 220 typically facilitates the transfer of data, control signals, and timing signals.

The back end module 210 contains an Error Correction Controller (ECC) engine 224 that encodes data bytes received from the host, and decodes and error corrects data bytes read from the non-volatile memory. The command sequencer 226 generates command sequences, such as program and erase command sequences, for transfer to the non-volatile memory die 108. A RAID (redundant array of independent die) module 228 manages the generation of RAID parity and recovers failed data. RAID parity may be used as an additional level of integrity protection for the data being written to the memory device 100. In some cases, the RAID module 228 may be part of the ECC engine 224. It should be noted that RAID parity may be added as an additional die or dies referred to by the common name (common name), but it may also be added within an existing die, e.g., as an additional plane, or an additional block, or an additional word line within a block. Memory interface 230 provides command sequences to non-volatile memory die 108 and receives status information from the non-volatile memory die. Flash control layer 232 controls the overall operation of back end module 210.

Additional components of memory device 100 include a media management layer 238 that performs wear leveling of the memory cells of non-volatile memory die 108. The memory system also contains other discrete components 240 such as an external electrical interface, external RAM, resistors, capacitors, or other components that may interface with the controller 122. In alternative embodiments, one or more of the physical layer interface 222, RAID module 228, media management layer 238, and buffer management/bus controller 214 are optional components that are not required in the controller 122.

A Flash Translation Layer (FTL) or a Media Management Layer (MML)238 may be integrated as part of flash management, which handles flash errors and interfaces with the host. In particular, MML may be a module in flash management and may be responsible for housekeeping (intermenals) of NAND management. In particular, MML 238 may include an algorithm in the memory device firmware that converts writes from the host into writes to memory structures 126 (e.g., flash memory) of die 108. MML 238 may be required because: 1) flash memory may have limited endurance; 2) flash memory may only be written in multiple pages; and/or 3) the flash memory may not be able to be written unless it is erased as a block. MML 238 is aware of these potential limitations of flash memory that may not be visible to the host. Accordingly, MML 238 attempts to convert a write from the host to a write into flash memory. Unstable bits can be identified and recorded using MML 238. This recording of unstable bits can be used to assess the health of the block and/or word line (memory cells on the word line).

Controller 122 may interface with one or more memory die 108. In one example, the controller and the plurality of memory die (together comprising the memory device 100) implement a Solid State Drive (SSD) that can emulate, replace, or be used in place of a hard disk drive in a host, as a Network Attached Storage (NAS) device, and so forth. Additionally, it is not necessary to make the SSD operate as a hard disk drive.

Fig. 3 is a perspective view of a memory device 600 including a block set of an exemplary 3D configuration of the memory structure 126 of fig. 1A. On the substrate are exemplary blocks BLK0, BLK1, BLK2 and BLK3 of memory cells (storage elements), and a peripheral region 604 having circuits used by the blocks. For example, the circuit may include a voltage driver 605, which may be connected to the control gate layer of the block. In one approach, control gate layers at a common height in a block are commonly driven. The substrate 601 may also carry the circuitry under the blocks, and one or more lower metal layers patterned as conductive paths to carry the signals of the circuitry. The blocks are formed in a middle area 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned into conductive paths to carry signals of the circuit. Each block includes a stacked region of memory cells, where alternating levels of the stack represent word lines. In one possible approach, each block has opposing tiered sides with vertical contacts extending upward from the opposing tiered sides to an upper metal layer to form connections to the conductive paths. Although four tiles are shown as an example, two or more tiles extending in the x and/or y direction may be used.

In one possible approach, the blocks are in a plane, and the length of the plane in the x-direction represents the direction in which signal paths to word lines extend in one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which signal paths to bit lines extend in one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device. The blocks may also be arranged in multiple planes.

Fig. 4 illustrates an exemplary cross-sectional view of a portion of one block of fig. 3. The block includes a stack 616 of alternating conductive and dielectric layers. In this example, the conductive layers include, in addition to data word line layers (or word lines) WLL0-WLL10, two SGD layers, two SGS layers, and four dummy word line layers (or word lines) WLD1, WLD2, WLD3, and WLD 4. The dielectric layer is labeled DL0-DL 19. Further, regions of the stack including NAND strings NS1 and NS2 are depicted. Each NAND string includes a memory hole 618 or 619 that is filled with material forming a memory cell adjacent to a word line. Region 622 of the stack is shown in more detail in fig. 6.

The stacked body includes a substrate 611. In one approach, a portion of the source lines SL includes an n-type source diffusion layer 611a in the substrate, which is in contact with the source terminal of each string of memory cells in the block. In one possible embodiment, the n-type source diffusion layer 611a is formed in a p-type well region 611b, the p-type well region 611b is in turn formed in an n-type well region 611c, and the n-type well region 611c is in turn formed in a p-type semiconductor substrate 611 d. In one approach, the n-type source diffusion layer may be shared by all blocks in the plane.

NS1 has a source terminal 613 at the bottom 616b of the stack and a drain terminal 615 at the top 616a of the stack. Local interconnects, such as local interconnect 617, may be provided periodically across the stack. The local interconnects may be metal-filled slits that extend through the stack, such as to connect a source line/substrate to a line above the stack. The slits may be used during the formation of the word lines and subsequently filled with metal. The local interconnect includes a conductive region 617a (e.g., metal) within an insulating region 617 b. A portion of bit line BL0 is also depicted. Conductive via 621 connects the drain terminal 615 of NS1 to BL 0.

In one approach, a block of memory cells includes a stack of alternating control gates and dielectric layers, and the memory cells are arranged in memory holes that extend vertically in the stack.

In one approach, each tile includes a staircase edge, with vertical interconnects connected to each layer (including the SGS, WL, and SGD layers) and extending up to a horizontal path to the voltage source.

For example, this example includes two SGD transistors, two drain side dummy memory cells, two source side dummy memory cells, and two SGS transistors in each string. In general, the use of dummy memory cells is optional, and one or more dummy memory cells may be provided. Further, one or more SGD transistors and one or more SGS transistors may be provided in the memory string.

An insulating region 620 may be provided to separate portions of the SGD layer from each other to provide an independently driven SGD line for each sub-block. In this example, the word line layer is common to two adjacent sub-blocks. See also fig. 7B. In another possible implementation, the insulating region 620 extends down to the substrate to separate the word line layers. In this case, the word line layer is divided in each subblock. In any case, though, the word line layers of a block may be joined to each other at their ends so that they are driven in common within the block, as shown in fig. 7B.

Figure 5 depicts a graphical representation of the memory hole/pillar diameter in the stack of figure 4. The vertical axis is aligned with the stack of fig. 4 and depicts the width (e.g., diameter) of the pillars (wMH) formed by the material in the memory holes 618 and 619. In such memory devices, the memory holes etched through the stack have a high aspect ratio (aspect ratio). For example, a depth to diameter ratio of about 25-30 is common. The reservoir bore may have a circular cross-section. Due to the etching process, the memory hole and resulting pillar width may vary along the length of the hole. Typically, the diameter tapers from the top to the bottom of the reservoir hole (solid line). That is, the memory hole is tapered, narrowing at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, causing the diameter to widen slightly before tapering from the top to the bottom of the memory hole (long dashed line). For example, in this example, the memory hole width is greatest at the level of WL9 in the stack. The memory hole width is slightly smaller at the level of WL10 and gradually becomes smaller at the level of WL8 to WL 0.

Due to the non-uniformity in the diameter of the memory holes and the resulting pillars, the programming and erase speeds of the memory cells may vary based on their location along the memory holes. With a relatively small diameter at the bottom of the memory hole, the electric field across the tunnel oxide is relatively strong, so that program and erase speeds are higher for memory cells in the word line adjacent to the relatively small diameter portion of the memory hole. The amount of word line up coupling and discharge is therefore relatively greater than the memory cells in the word lines adjacent to the relatively larger diameter portion of the memory hole.

In another possible embodiment, the stack is manufactured in two levels, indicated by dashed lines. The bottom level is first formed with a respective memory hole. The top level is then formed with respective memory holes that align with the memory holes in the bottom level. Each memory hole is tapered such that a double tapered memory hole is formed, where the width increases, then decreases and increases again from the bottom to the top of the stack.

Fig. 6 depicts a close-up view of region 622 of the stack of fig. 4. Memory cells are formed at different levels of the stack, at the intersections of the word line layers and the memory holes. In this example, SGD transistors 680 and 681 are provided over dummy memory cells 682 and 683 and data memory cell MC. Several layers may be deposited, for example, using atomic layer deposition, along the Sidewalls (SW) of the memory holes 630 and/or within each word line layer. For example, each pillar 699 or pillar formed of material within a memory hole may contain a charge trapping layer 663 or material such as silicon nitride (Si)₃N₄) Or other nitride film, a tunneling layer 664 (tunnel oxide), a channel 665 (e.g., comprising polysilicon), and a dielectric core 666. The word line layer may include a blocking oxide/blocking high-k material 660, a metal barrier (barrier)661, and a conductive metal 662 such as tungsten as a control gate. For example, control gates 690, 691, 692, 693 and 694 are provided. In this example, all layers except metal are provided in the memory hole. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form pillar Active Areas (AA) of the NAND string.

When programming a memory cell, electrons are stored in the portion of the charge trapping layer associated with the memory cell. These electrons are introduced into the charge trapping layer from the channel and pass through the tunneling layer. The Vth of a memory cell increases in proportion to (e.g., as the amount of stored charge increases). During an erase operation, electrons are returned to the channel.

Each of the memory holes may be filled with a plurality of ring-shaped layers including a blocking oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each of the memory holes is filled with a body material, and a plurality of halo layers are between the core region and the word lines in each memory hole.

The NAND string can be considered to have a floating body channel because the length of the channel is not formed on the substrate. Further, the NAND strings are provided by a plurality of word line layers stacked one above the other in a stack, and separated from each other by dielectric layers.

FIG. 7A depicts an exemplary view of NAND strings in a sub-block according to the 3D configuration of FIG. 4. Exemplary memory cells are depicted that extend along the word lines in each sub-block in the x-direction. For simplicity, each memory cell is depicted as a cube. SB0 includes NAND strings 700n, 701n, 702n, and 703 n. SB1 includes NAND strings 710n, 711n, 712n, and 713 n. SB2 includes NAND strings 720n, 721n, 722n, and 723 n. SB3 includes NAND strings 730n, 731n, 732n and 733 n. The bit lines are connected to a set of NAND strings. For example, bit line BL0 is connected to NAND strings 700n, 710n, 720n and 730n, bit line BL1 is connected to NAND strings 701n, 711n, 721n and 731n, bit line BL2 is connected to NAND strings 702n, 712n, 722n and 732n, and bit line BL3 is connected to NAND strings 703n, 713n, 723n and 733 n. A sense circuit may be connected to each bit line. For example, the sensing circuits 400, 400a, 400b, and 400c are connected to bit lines BL0, BL1, BL2, and BL3, respectively. A NAND string is an example of a vertical memory string (e.g., a vertical string) that extends upward from a substrate.

Programming and reading can occur in one word line and one sub-block at a time for the selected cell. This allows each selected cell to be controlled by a respective bit line and/or source line. For example, an exemplary set 795 of memory cells in SB0 is connected to WLL 4. Similarly, sets 796, 797, and 798, which include data memory cells in SB1, SB2, and SB3, are connected to WLL 4.

Fig. 7B depicts word lines and SGD layers in the exemplary block set according to fig. 4. Blocks BLK0, BLK1, BLK2 and BLK2 are depicted. The Word Line Layer (WLL) in each block is depicted, along with an exemplary SGD line. One SGD line is provided in each sub-block. BLK0 includes subblocks SB0, SB1, SB2 and SB 3. Each circle represents a memory hole or string. In practice, the sub-blocks are elongated in the x-direction and contain thousands of memory strings. Additionally, more blocks than those depicted are arranged in multiple rows on the substrate. The word line layer and the SGD/SGS layer may receive voltages from row decoder 2410. See also fig. 24A and 24B.

FIG. 8A depicts an exemplary Vth distribution of memory cells in a first read condition compared to a second read condition, where eight data states are used. The eight data states are merely examples, as other numbers, such as four, sixteen, or more, may also be used. For the Er, a, B, C, D, E, F and G states, we know the Vth distributions 820, 821, 822, 823, 824, 825, 826 and 827 under the second read condition, respectively, and know 820a, 821a, 822a, 823a, 824a, 825a, 826a and 827a under the first read condition, respectively. For the A, B, C, D, E, F and G states, we have program verify voltages VvA, VvB, VvC, VvD, VvE, VvF and VvG, respectively. Also depicted are read voltages VrAH, VrBH, VrCH, VrDH, VrEL, VrFL and VrGL, respectively, under the second read condition, and read voltages VrAL, VrBL, VrCL, VrDL, VrEH, VrFH and VrGH, respectively, under the first read condition. Also depicted are exemplary encodings of bits of 111, 110, 100, 000, 010, 011, 001, and 101, respectively. The bit format is: UP/MP/LP. An erase verify voltage VvEr is used during an erase operation.

This example indicates that when the data state is relatively high or low, the shift in the Vth distribution for the first read condition is relatively larger than when the data state is in the middle range, as compared to the second read condition. The shift may be progressively larger for progressively lower or higher data states. In one example, under a first read condition, the read voltages for VrAL, VrBL, VrCL and VrDL are optimal for the relatively lower states of a, B, C and D, respectively, and the read voltages for VrEH, VrFH and VrGH are optimal for the relatively higher states of E, F and G, respectively. Similarly, under the second read condition, the read voltages of VrAH, VrBH, VrCH and VrDH are optimal for the relatively lower states of a, B, C and D, respectively, and the read voltages of VrEL, VrFL and VrGL are optimal for the relatively higher states of E, F and G, respectively. Thus, in one possible implementation, the lower of the two read voltages per state is optimal under the first read condition for the lower state, and the higher of the two read voltages per state is optimal under the first read condition for the higher state.

The optimum read voltage is typically midway between the Vth distributions for adjacent data states. Accordingly, as the Vth distribution shifts, the optimum read voltage shifts.

The first read condition may occur when there is a long delay since the last program or read operation. An exemplary sequence is: the block is programmed, one hour is waited, and then the block is read. The first read condition may also occur when there is power up/down. An exemplary sequence is: the block is programmed, powered up/down, and then read. The first read condition may also occur when there are other blocks to program or read. An exemplary sequence is: one block is programmed, another block is programmed, and then the one block is read.

FIG. 8B depicts an exemplary bit sequence for the lower, middle, and upper pages of data, and associated read voltages. In this case, the memory cells each store three bits of data in one of eight data states. An exemplary bit allocation for each state is depicted. The lower, middle or upper portion may represent data of the lower, middle or upper page, respectively. In addition to the erased state Er, seven programmed data states A, B, C, D, E, F and G were used. With these bit sequences, the data of the lower page can be determined by reading the memory cells using read voltages (e.g., control gate or word line voltages) of VrA and VrE. If Vth < VrA or Vth > VRE, the Lower Page (LP) bit is 1. If VrA < Vth < ═ VrE, LP is 0. In general, a memory cell can be sensed by a sensing circuit while a read voltage is applied. If the memory cell is in a conductive state at the sensing time, its threshold voltage (Vth) is less than the read voltage. If the memory cell is in a non-conductive state, its Vth is greater than the read voltage.

The read voltage for reading a page of data is determined by the transition from 0 to 1 or 1 to 0 in the encoded bit (codeword) of each state. For example, the LP bit transitions from 1 to 0 between Er and A and 0 to 1 between D and E. Accordingly, the read voltage of LP is VrA and VRE.

The data of the middle page may be determined by reading the memory cells using the read voltages VrB, VrD and VrF. If Vth < VrB or VrD < Vth < ═ VrF, the Middle Page (MP) bit is 1. If VrB < Vth < ═ VrD or Vth > VrF, MP is 0. For example, the MP bit transitions from 1 to 0 between A and B, 0 to 1 between C and D, and 1 to 0 between E and F. Accordingly, the read voltages of MP are VrB, VrD and VrF.

The data of the upper page can be determined by reading the memory cells using the read voltages of VrC and VrG. If Vth < VrC or Vth > VrG, the Upper Page (UP) bit is 1. If VrC < Vth < ═ VrG, UP is 0. For example, the UP bit transitions from 1 to 0 between B and C, and from 0 to 1 between F and G. Accordingly, the read voltage of UP is VrC and VrG. The read voltages are depicted as VrA, VrB, VrC, VrD, VrE, VrF, and VrG, where each of these voltages can represent either the first read value or the second read value, taking its optimum value.

Fig. 9 depicts waveforms for an exemplary programming operation. The horizontal axis depicts Program Loop (PL) number and the vertical axis depicts control gate or word line voltage. In general, a program operation may involve applying a pulse train to a selected word line, where the pulse train includes multiple program loops or program-verify iterations. The program portion of the program-verify iteration includes a program voltage and the verify portion of the program-verify iteration includes one or more verify voltages.

In one approach, each programming voltage comprises two steps. Also, Incremental Step Pulse Programming (ISPP) is used in this example, where the program voltage is stepped up in each successive Programming loop using a fixed or varying Step size. This example uses ISPP in a single programming pass to complete programming. ISPP can also be used in each programming pass in a multi-pass operation.

Waveform 900 includes a series of programming voltages 901, 902, 903, 904, 905, … … 906, which are applied to the word line selected for programming and to the associated set of non-volatile memory cells. As an example, one or more verify voltages may be provided after each program voltage based on the target data state being verified. 0V may be applied to the selected word line between the program and verify voltages. For example, after each of the programming voltages 901 and 902, an A-state and B-state verify voltages (waveform 910) for VvA and VvB, respectively, may be applied. After each of program voltages 903 and 904, the A-state, B-state, and C-state verify voltages (waveform 911) for VvA, VvB, and VvC can be applied. After a number of additional programming loops (not shown), E-state, F-state, and G-state verify voltages of VvE, VvF, and VvG (waveform 912) can be applied after the final program voltage 906.

FIG. 10A depicts a graph of example waveforms in a programming operation, showing the upward coupling of word line voltages. The time period shown represents one program-verify iteration. The horizontal axis depicts time and the vertical axis depicts word line voltage Vwl. The program voltage 1000 is applied to the selected word line from t0-t4 and reaches a magnitude of Vpgm. The program voltage may be temporarily suspended at an intermediate level, such as Vpass, to avoid a single large transition that may have undesirable coupling effects. The pass voltage 1005 is applied to the unselected word lines from t0-t19, and reaches a magnitude of Vpass that is high enough to provide the cells in a conductive state so that a sensing (e.g., verify) operation can occur for the cells of the selected word line. The pass voltage includes a raised portion, a fixed magnitude portion (e.g., at Vpass), and a lowered portion. Alternatively, the pass voltage may be raised faster relative to the program voltage, reaching Vpass at t 0.

A verify voltage 1010 is applied to the selected word line. In this example, all seven verify voltages are applied, one after the other. Eight-level memory devices are used in this example. Verify voltages of VvA, VvB, VvC, VvD, VvE, VvF and VvG are applied at t8, t9, t10, t11, t12, t13 and t14, respectively. The sensing circuit may be activated during each verify voltage. From t15-t16, the waveform decreases from VvG to 0V or other steady state level.

For unselected word lines, the decrease in Vpass will cause the cell to transition from a conductive state to a non-conductive state. In particular, when Vpass is lowered below the cutoff level Vcutoff (dotted line at t 18), the channel of the cell will become cutoff, e.g., the cell will become non-conductive. When the cell becomes non-conductive, it acts as a capacitor with the control gate being one plate and the channel being the other plate. The cell becomes non-conductive when Vcg < Vcutoff or Vcg < (Vth + Vsl), where Vcg is the control gate voltage (word line voltage) of the cell, Vth is the threshold voltage of the cell, and Vsl is the source line voltage, which in turn is approximately the voltage at the source terminal of the cell. For cells in the highest programmed state (e.g., the G-state), Vth can be as low as VvG (or lower due to post-program charge loss) and as high as Vth at the upper tail of the G-state in Vth distribution 827 or 827a in fig. 8A. Vcutoff may therefore be as low as VVG + Vsl or as high as Vth + Vsl at the upper tail of the G state. As the pass voltage 1005 decreases from Vcutoff to 0V, the channel capacitively couples downward by a similar amount, as shown by curve 1015 in FIG. 10B.

When Vsl is large, the voltage swing will be large when the channel is turned off. However, since Vch is Vsl, the minimum down-coupling level of Vch will be substantially independent of Vsl. For example, a 6V swing on the word line voltage (e.g., Vcutoff-6V) with Vsl equal to 1V will result in a minimum down-coupling level of Vch that is about the same as a 5V swing on the word line voltage (e.g., Vcutoff-5V) with Vsl equal to 0V.

Curve 1012 represents the upward coupling of the word line voltage from t19-t 20. The up-coupling is shown as occurring relatively quickly, but this is not to scale. In practice, verify operations (e.g., from t5-t19) may consume about 100 microseconds, while the upward coupling of the word line may be significantly longer, in the millisecond range, such as 10 milliseconds.

Fig. 10B shows a graph corresponding to the channel voltage (Vch) of fig. 10A. For unselected memory strings (strings that do not have cells programmed in the current programming loop), Vch will be boosted to a level such as 8V (not shown), for example, from t0-t4, during the programming voltage. This boosting is achieved by providing the SGD and SGS transistors of the unselected string in a non-conductive state to float Vch. When Vpass and Vpgm are applied to the word lines, Vch is coupled higher due to capacitive coupling. For a selected memory string (a string with cells programmed in the current programming loop), Vch is typically grounded, as shown during the programming voltage.

During the verify voltage, Vch may be, for example, initially at about 1V for the selected memory string. Vch is about the same as Vsl for the channel of the selected memory string. Vsl is set based on the type of sensing used. Examples include negative sensing where Vsl is about 1V, and positive sensing where Vsl is about 0V and a negative word line voltage is used. Regardless of the level of Vsl or the type of sensing used, the techniques described herein are applicable.

The channel is capacitively coupled down to the lowest level from t18-t19, and then returns to the final level, e.g., 0V, starting from t19-t 20. If the word line voltage is allowed to begin floating at t19, the voltage (curve 1012) is capacitively coupled higher by the rise in Vch. The voltage of the word line floats to the peak level Vwl _ couppled _ up, thereby reaching the second read condition. For example, Vcutoff may be 6V, such that there is a 6V change (e.g., 6-0V) in the word line voltage, which couples to the channel. In the case where Vch is initially 1V and 90% coupling ratio, the minimum Vch may be, for example, about 1-6 × 0.9 ═ 4.4V. Accordingly, there is a 4.4V rise on Vch, which is coupled to a word line, e.g., the control gate of the cell. Vwl _ couppled _ up may be about 4.4 × 0.9 ═ 4V. By disconnecting the word line from the word line driver, the voltage of the word line is floated.

FIG. 10C depicts a graph of exemplary waveforms in a read operation, showing the upward coupling of word line voltages. The read operation is similar to the verify operation in that both are sense operations and both can provide an upward coupling of the word line voltage. The horizontal axis depicts time and the vertical axis depicts word line voltage Vwl. Pass voltages 1115, 1116 and 1117 are applied to unselected word lines from t0-t3, t4-t8 and t9-t12, respectively, and have a magnitude of Vpass. The pass voltage includes a raised portion, a portion of Vpass, and a lowered portion. For each of the lower, middle and upper pages, the read voltage includes separate waveforms 1120 (at the levels of VrAH and VrEL), 1121 (at the levels of VrBH, VrDH and VrFL) and 1122 (at the levels of VrCH and VrGL), respectively, consistent with fig. 8A and 8B. As an example, the read voltage is optimized for the second read condition and is applied to the selected word line. Eight-level memory devices are used in this example.

For unselected word lines, the decrease in Vpass will cause the cell to transition from a conductive state to a non-conductive state, as discussed. the dotted line at t13 indicates when the G-state cell becomes non-conductive. As the pass voltage 1117 decreases from Vcutoff to 0V, the channel capacitively couples downward by a similar amount, as represented by curve 1035 in FIG. 10D. As the channel voltage rises after t14, the word line voltage floats and couples higher to Vwl _ coupled _ up.

Fig. 10D shows a graph of channel voltage (Vch) corresponding to fig. 10C. The channel is capacitively coupled down to the lowest level of Vch _ min from t13-t14, and then returns to the final level of, for example, 0V, starting from t14-t 15. If the voltage of the word line is allowed to begin floating at t14, the voltage (curve 1032) is capacitively coupled higher by the rise in Vch (curve 1035). The voltage of the word line floats to the peak level of Vwl _ coupled _ up as discussed.

FIG. 10E depicts the waveform of FIG. 10C, which shows the decay of the voltage of the upward coupling of the word line. The time scale is different than in fig. 10A-10D and represents a longer time period, such as one or more hours. The curve 1123 shows the read voltages during the time periods t0-t1 (corresponding to the waveforms 1120-1122 in FIG. 10C). The curve 1123a shows the pass voltage (corresponding to the waveform 1115-1117 in FIG. 10C). Curve 1125 depicts Vwl rising to the upward coupling level (Vwl _ coupled _ up) due to coupling (in time periods t1-t 2), and then the decay of Vwl in time periods t2-t 3. Overall, the rise in Vwl occurs relatively quickly compared to the time period of decay.

FIG. 10F depicts a graph of channel voltage according to FIG. 10E. In time period t1-t2, the decrease is followed by an increase (curve 1126). Vch is about 0V from t2-t3 (curve 1127).

FIG. 10G depicts a graph of Vth of memory cells connected to an upward-coupled word line, consistent with FIGS. 10E and 10F. For cells in an exemplary data state, such as the A-state, from t0-t1, Vth is at the initial level Vth _ initial. This represents the first read condition. Due to the coupling simultaneous with the rise in Vch, Vth rises from t1-t2 (curve 1128) to the peak level of Vth _ coupled _ up. This represents a second read condition. Vth then gradually decreases from t1-t3 back to Vth _ initial.

FIG. 11A depicts the control gate voltage and channel voltage on a memory cell, which acts as a capacitor when the control gate voltage drops in a sense operation. The first read problem is caused by the stacking of 3D word line planes or layers, where the channel of the memory cell is floating and not coupled to the substrate as in 2D flash NAND architectures. Wordline coupling and electron trapping in the oxide-nitride-oxide (ONO) layer are the source of the first read problem.

As discussed, after a read/verify operation, when the read pass voltage (Vpass) applied on the word line is ramped down, the G-state cell (e.g., having a Vth of 5V) turns off the channel when Vpass drops to 5V. When Vpass further drops to Vss, the floating channel potential is then pushed down to a negative value. Next, after the end of the read operation, the negative voltage (about-4.5V) in the channel shown above rises by attracting positive charges. Since the data word lines are floated, the amount of holes needed to charge the channel is relatively small, so the selected and unselected word lines can quickly couple up to about 4V (assuming a 90% coupling ratio). The potential on the word line is held at about 4V for a period of time. This attracts and traps electrons in the tunnel ONO layer and causes Vth to shift up or down for lower or higher data states, respectively. Since the word line is coupled to the floating channel potential, the word line voltage is thereby raised to about 4V after the read operation.

The top plate represents the control gate or word line and the bottom plate represents the channel. Capacitor 1040 represents the memory cell when the word line voltage drops from 8V (vpass) to 5V (Vcutoff, such as VvG or slightly higher) and Vch is 0V. Capacitor 1042 represents the memory cell when the word line voltage reaches 0V, so that Vch is coupled down to about-4.5V. The capacitor 1044 represents the memory cell when the associated word line voltage begins to float. Capacitor 1046 represents the memory cell when the associated word line voltage reaches Vwl _ couppled _ up under the second read condition. If the Vth of a memory cell is less than 4V (e.g., the cell is in an erased state or a less programmed state), the memory cell will be weakly programmed such that its Vth is raised. If the Vth of a memory cell is greater than 4V (e.g., the cell is in a higher programmed state), the memory cell will be weakly erased so that its Vth drops. The capacitor 1048 represents the memory cell after a long time (e.g., one hour or more) has elapsed, such that the word line has been discharged to a first read condition.

When the data word line voltage is floating, the amount of holes needed to charge the channel is relatively small. Thus, as an example, the selected word line may be coupled up to about 4V relatively quickly. The potential on the selected word line is held at about 4V for a period of time, attracting electrons trapped in the tunnel oxide-nitride-oxide (ONO) layer and causing Vth to shift upward. If waiting long enough before the next read operation, the upwardly coupled potential of the word line will discharge and the trapped electrons will be released. The first read condition will occur again.

FIG. 11B depicts a portion of the memory cell MC of FIG. 6 showing injection of electrons into the charge trapping region during weak programming. The memory cell includes a control gate 694, a metal barrier 661a, a blocking oxide 660a, a charge trapping layer 663, a tunneling layer 664, a channel 665, and a dielectric core 666. Due to the boosted word line voltage, an electric field (E) is generated that attracts electrons (see example electrons 1050) into the charge trapping layer, raising Vth. This weak programming can be caused by the Poole-Frenkel effect, where an electrical insulator can conduct power. This is a tunneling of electrons through trapping. Weak erase similarly involves an electric field that repels electrons from the charge trapping layer, lowering Vth.

FIG. 12A depicts an exemplary memory string 1200 configuration just prior to discharging the word lines at the end of a sense operation. This is, for example, just before the word line voltage starts to ramp down from Vpass, e.g., at t17 in FIG. 10A and t12 in FIG. 10C. As mentioned, the first read problem is caused by the high Vth cells (e.g., G-state cells) turning off the channel during discharge of the word line. Vch is coupled down through the discharge word line. Subsequently, holes enter the channel to neutralize the channel voltage, e.g., Vch rises from a negative voltage to about 0V. This boost couples the word line voltage up to about 4V, for example. This boosted word line voltage ultimately results in electron trapping in the interface between the tunnel oxide and the polysilicon tunnel, and charge redistribution in the charge trapping layer of the memory cells, raising the Vth of some of the cells to the second read condition. After some time has elapsed (such as one or more hours), or if the word line is exposed to a steady state voltage for some time, the word line will eventually discharge back to about 0V. This discharge is due to current passing through the SGS transistor and leaking into the substrate. The cell then returns to the first read condition. The optimal read level varies based on whether the cell is in (or somewhere in between) the first read condition or the second read condition. If the read level is optimized for the first read condition and the second read condition exists, or if the read level is optimized for the second read condition and the first read condition exists, a large number of read errors will result.

The memory string 1200 extends between a p-well 1205 and a bit line 1202, and includes memory cell control gates 1211, 1212, 1213, … …, 1214, and 1215 between an SGS transistor control gate 1210 and an SGD transistor control gate 1216. The string includes a channel region 1204 (e.g., a tunneling layer within a charge trapping layer) within a memory thin film layer 1203. A central dielectric core 1201 is also depicted. The string is shown in cross-section with the control gate and layer surrounding the memory hole. Further, as an example, the memory cells with control gates 1211 and 1215 are programmed to the G state (the highest state in this example), and the memory cells with control gates 1212 and 1214 are in an arbitrary state.

The SGD control gate is at a voltage of Vsgd (e.g., 3-4V), the memory cell control gates 1211-1215 are at a voltage of Vpass (e.g., 8-10V), the SGS control gate is at a voltage of Vsgs (e.g., 3-4V), the p-well can be at 1V (Vsl) and the bit line can be at 1-2V. Because the sense circuit is activated for a sense operation, exemplary electrons ("e-") enter the channel from the bit line. This results in a channel voltage of about 0V. During the discharge or ramp down of the word line, the G-state cell turns off (becomes non-conductive), causing the channel voltage to float and couple down, as mentioned.

FIG. 12B depicts the configuration of an exemplary memory string just after the word lines are discharged at the end of the sense operation. At this time, the channel voltage is negative (Vch <0V), as indicated by the reduced number of electrons, and each of the control gates reaches 0V. The bit line voltage may also be set to 0V.

FIG. 12C depicts an exemplary memory string configuration when the word lines are coupled up through the channel. The negative channel voltage causes a lateral field across the SGS transistor which causes holes to gradually enter the channel from the p-well. The holes will neutralize the field across the SGS transistor and combine with electrons, gradually raising the channel voltage towards 0V. At this time, the word line voltages float so that they couple up as Vch rises. This is indicated by the label "float higher".

FIG. 12D depicts an exemplary memory string configuration when the word lines have completed coupling up. In this case, the channel is completely neutralized so that Vch becomes 0V. As an example, the word line voltage is at an upwardly coupled level of about 4V.

Fig. 13A depicts an exemplary process according to block 10 in fig. 1C. This feature includes detecting the up-coupled state of the word line and setting the read voltage accordingly. Step 1300 includes receiving a read command for a selected memory cell (e.g., connected to a selected word line) in a block. For example, a command may be received at the controller 122 from a host. In other cases, the read command is generated internally within the memory device 100 (FIG. 1A). Step 1301 includes sensing the word line voltage in the block. In one approach, the sensed word line is predetermined in the block and need not be the same as the selected word line connected to the selected memory cell. Sensing of one or more word lines is possible. For example, the voltage detector may be configured to perform an evaluation of the voltage of one or more word lines. For further exemplary details, see fig. 24B. Step 1302 includes selecting a set of read voltages based on the sensed word line level. The sensed word line level indicates whether the memory cell is in the first read condition, the second read condition, or somewhere in between. See, e.g., fig. 13B-13D. Step 1303 includes performing a read operation in the block using the selected set of read voltages. In this approach, an optimal set of read voltages that minimize read errors may be selected based on the current upward coupling state of the word line.

FIG. 13B depicts a graph of shift of Vth versus time for different data states. As mentioned, under a first read condition, a Vth shift down can be seen for one or more lower states, essentially no change in Vth can be seen for one or more mid-range states, and a Vth shift up can be seen for one or more higher states. These shifts are relative to the Vth level under the second read condition.

Time t0 represents the time of the sensing operation when the cell is in the first read condition. Because the word line is discharged and the Vth of the cell is relatively far away from the Vth of the second read condition for each programmed data state, the magnitude of the shift in read voltage is greatest at this time. As time continues from 0 to tf, the shift gradually decreases in magnitude. In one approach, a shift of 0V may be achieved at tf. Separate curves are provided for the programmed states labeled A, B, C, D, E, F, and G, where the curves for A, B, C, D show a shift down and the curves for E, F, and G show a shift up. This example shows eight data states, but similar trends can be seen for other numbers of data states.

FIG. 13C depicts a graph showing the trend of read voltage versus detected word line voltage. The horizontal axis depicts a Word Line (WL) voltage, which may be sensed using a circuit such as that shown in fig. 24B. The vertical axis depicts read voltages in accordance with FIG. 8A, including lower and higher read voltages for each programmed data state. The graph shows that the read voltage increases with the sensed WL voltage for the lower data state and decreases with the sensed WL voltage for the higher data state.

FIG. 13D depicts a graph of read voltage versus detected word line voltage, where two sets of read voltages are used in the exemplary embodiment of FIG. 13C. In a simplified embodiment, the sensed WL voltage is classified into one of two ranges: below the reference voltage (Vref) or above Vref. If the sensed WL voltage is higher than Vref, the read voltages VrAH, VrBH, VrCH, VrDH, VrEL, VrFL and VrGL are selected. If the sensed WL voltage is below Vref, then the read voltages VRAL, VRBL, VRCL, VrDL, VrEH, VrFH and VrGH are selected. In one approach, Vref may be selected based on the maximum up-coupled word line voltage. For example, if the maximum up-coupled word line voltage is about 4V, Vref may be about half of it, or 2V.

FIG. 13E depicts another exemplary process according to block 10 in FIG. 1C. As an alternative to fig. 13A, this process involves periodic polling (polling) of the blocks to determine their word line voltages. This process is useful because it can store a data entry for the word line voltage prior to receiving a read command. When a read command is received, the appropriate read voltage can be immediately determined without performing another word line voltage detection. It can be checked whether the detected word line voltage is recent enough so that it is reliable at the selected read voltage.

Step 1310 includes sensing a word line voltage according to a timer. This may be done periodically, for example, every few minutes or hours. Step 1311 includes storing a data entry for the word line voltage. If no read command is received before the time of the next sensing, steps 1310 and 1311 are repeated. If a read command for a block is received at step 1312, decision step 1313 determines whether the data entry is recent, e.g., not older than a specified amount of time. If decision step 1313 is true, step 1314 selects a read voltage set based on the data entry, and step 1315 performs a read operation using the read voltage set at the block. The process then continues at step 1310. If decision step 1313 is false, step 1316 repeats the sensing of the wordline voltage, step 1317 stores a new data entry for the wordline voltage, and step 1318 resets the timer. Then steps 1314 and 1315 are reached.

Optionally, decision step 1313 is omitted so that the most recent entry is always used to select the read voltage. The period of wordline detection may be set short enough so that the latest entry is valid.

FIG. 14A depicts an exemplary process according to block 11 in FIG. 1C. This feature includes applying a pre-read voltage pulse just prior to the read operation. Step 1400 includes receiving a read command for a selected memory cell (e.g., connected to a selected word line) in a selected block. Decision step 1401 determines whether a condition for applying a pre-read voltage pulse to a selected word line is satisfied. This decision step may take into account various data inputs. For example, block 1401a indicates whether the elapsed time since the last sensing of the block exceeds a threshold. The threshold may be long enough so that if the elapsed time exceeds the threshold, the cell will be in a first read condition. If an input is received at block 1401a, the condition may be satisfied. Block 1401b indicates whether a previous read of the block resulted in one or more uncorrectable errors. This previous read may be associated with a read command other than the previous read command involved in step 1400. In response to one or more uncorrectable errors in a previous read, a read recovery process may have been used to read the data. If an input is received for block 1401b, the condition may be satisfied.

The control circuitry may be configured such that the voltage detector is caused to perform the evaluation in response to determining that a previous read of the memory cells in the block resulted in one or more uncorrectable errors.

Block 1401c indicates whether the word line voltage in the block is below a threshold. The threshold may be low enough so that if the word line voltage is below the threshold, the cell will be in a first read condition. The word line voltage may be sensed using the techniques discussed with respect to fig. 13A and 24B. If an input is received at block 1401c, the condition may be satisfied.

If decision step 1401 is true, step 1402 comprises applying a pre-read voltage pulse to the selected word line, and step 1403 comprises reading the selected memory cell. See fig. 15A and 15B. In one embodiment, the pre-read voltage pulse is applied to a selected word line in a selected block but not to the remaining, unselected word lines. In another implementation, the pre-read voltage pulse is also applied to some or all of the unselected word lines simultaneously. The pre-read voltage pulses provide weak or soft programming of the cells, especially those in the lower programmed state. The pulse creates an electric field across the cell that causes some charge trapping and therefore some increase in Vth, which is proportional to the duration and amplitude of the pulse. Depending on the pulse amplitude and duration, the pulse may not raise Vth for cells in the higher state.

In one option, step 1402a includes setting a duration of the pre-read voltage pulse to a fixed duration. The amplitude of the pre-read voltage pulse may also be set to a fixed amplitude. In another option, step 1402b includes setting a duration of the pre-read voltage pulse based on the elapsed time. The amplitude of the pre-read voltage pulse may also be set based on the elapsed time. See fig. 15C. Step 1402c includes setting a duration of the pre-read voltage pulse based on the detected word line voltage. The amplitude of the pre-read voltage pulse may also be set based on the detected word line voltage. See fig. 15D. Step 1402d includes setting a duration of the pre-read voltage pulse based on the temperature. The amplitude of the pre-read voltage pulse may also be set based on the sensed temperature. See fig. 15E.

If the read voltage is optimized for the second read condition, the pre-read voltage pulse helps to raise the Vth of the cell back to the second read condition before the cell is read.

FIG. 14B depicts another exemplary process according to block 11 in FIG. 1C. In this case, the pre-read voltage pulse is not applied unless there are one or more uncorrectable errors for the initial read. Step 1410 includes receiving a read command for the selected memory cell. Step 1411 includes reading the selected memory cell. In one approach, a default read level optimized for the second read condition is used. A decision 1412 determines whether there are one or more uncorrectable errors, e.g., whether the ECC process cannot correct all read errors. If decision step 1412 is false, then the read process proceeds at step 1417. If decision step 1412 is true, step 1413 includes applying a pre-read voltage pulse to the selected word line. Step 1414 then reads the selected memory cells again and decision step 1415 determines whether one or more uncorrectable errors still exist. If decision step 1415 is false, then a read process is performed at step 1417. If decision step 1415 is true, step 1416 includes performing a read recovery process. This may involve repeated read attempts, where the read voltage is shifted higher and/or lower.

Alternatively, if decision step 1415 is true, a second pre-read voltage pulse may be applied. The amplitude and/or duration of the second pre-read voltage pulse may be greater than the amplitude and/or duration of the first application of the pre-read voltage pulse.

If the word line voltage floats long enough, the initial read resulting in an uncorrectable error will have some effect on the up-coupled word line voltage. However, this would unduly lengthen the read operation time. Soft programming of the pre-read voltage pulse acts more rapidly than word line up coupling at the increase of Vth of the cell. In addition, the pre-read voltage pulse may act on the selected word line, rather than on all word lines in the block.

FIG. 15A depicts a graph of exemplary waveforms in a read operation similar to that of FIG. 10C, wherein a pre-read voltage pulse is applied prior to the read operation. The waveforms 1115-1117 and 1120-1122 of FIG. 10C are repeated. The pre-read voltage pulse is applied just prior to the read waveform (curve 1500). As an example, the pre-read voltage pulse may have a magnitude of Vpass. Overall, at the Vth rise of the cell, the pulse will have a greater effect when it has a higher amplitude and/or longer duration. The pre-read voltage pulse starts to ramp up at t0a and starts to ramp down at t0b, for example, in response to a read command, such that the duration is t0b-t0 a. After it ramps down to 0V, for example, the read operation starts at t 0. The delay between the pre-read voltage pulse and the read operation can be minimized to minimize the overall read time. The pre-read voltage pulse helps raise the Vth of the cell before reading the cell to reduce read errors. The upward coupling of the word line after the read operation may also be performed, as indicated by curve 1032.

Curve 1500a shows an option for pre-reading voltage pulses, which may reduce power consumption. In this example, the ramp rate of the pre-read voltage pulse may be less than the ramp rate of the subsequent pass voltage during the read operation.

Fig. 15B shows a graph corresponding to the channel voltage (Vch) of fig. 15A. Curve 1035a corresponds to curve 1035 of fig. 10C.

FIG. 15C depicts a plot of pre-read voltage pulse duration and/or amplitude versus time since the last sense operation, in accordance with step 1402b of the process of FIG. 14A. This may be the time since the last read operation or programming operation including a verify test. The duration and/or amplitude increases with time because the pre-read voltage pulse helps the Vth of the memory cell to increase, where Vth decreases with time due to the discharge of the word line voltage. The effect of the pre-read voltage pulse is stronger when the duration is longer and/or the amplitude is stronger. By way of example, the duration may be about 0.1-200 milliseconds.

FIG. 15D depicts a plot of pre-read voltage pulse duration and/or amplitude versus detected word line voltage in accordance with step 1402c of the process of FIG. 14A. The duration and/or amplitude increases as the detected WL voltage decreases because a lower WL voltage indicates that the word line voltage has discharged and the cell is in (or close to) the first read condition. Thus indicating a stronger (longer or larger amplitude) pre-read voltage to help raise the Vth of the memory cell back to the second read condition.

FIG. 15E depicts a plot of pre-read voltage pulse duration and/or amplitude versus temperature according to step 1402d of the process of FIG. 14A. I.e. the pulse duration and/or amplitude is inversely proportional to the temperature. The temperature sensor 115 of fig. 1A may be used to determine temperature. In general, at lower temperatures, we require longer pulse durations and/or amplitudes. In the case of a pre-read (which occurs just prior to the read operation), we expect to use a pre-read pulse to capture electrons so that the memory cell enters a second read state. The time required to capture electrons and to transition the memory cell from the first read state to the second read state increases at lower temperatures. One mechanism is believed to involve hopping between capture sites, which is slower at lower temperatures. Thus, longer pulse durations and/or amplitudes are preferred at lower temperatures.

FIG. 15F depicts a graph of error counts versus programming pulse width on a log-log scale according to the process of FIG. 14A. The graph is obtained by reading the cell in the first reading condition. It can be seen that if the pulse duration is short (such as a few nanoseconds), it does not significantly reduce the error count, and the error count is expected to be as when the cell is in the first read condition. However, as the pulse duration increases (such as to a few milliseconds), the error count is significantly reduced to the same level as when the cell is in the second read condition. In this example, the read voltage is optimized for the second read condition.

FIG. 16A depicts an exemplary process according to block 12 in FIG. 1C. This feature includes periodically applying voltage pulses to all word lines in a block. This process may use a voltage pulse similar to the pre-read voltage pulse. In one approach, this process may apply voltage pulses to all word lines in one or more blocks, rather than only to the selected word line. The process may be performed independently of a read command. A command may be defined in the controller that causes the pulses to be issued periodically. In one approach, when executing a command, the voltage drivers and associated pass gates (fig. 24A and 24B) are configured to apply voltage pulses to all word lines in one or more blocks simultaneously. Another approach is to apply voltage pulses to one or more word lines in one or more blocks simultaneously.

It is also possible to stagger the voltage pulses within one die so that they are applied to different sets of blocks at different times. This reduces peak current consumption. For example, if the tiles are arranged in multiple planes (e.g., different p-well regions of the substrate), pulses may be applied to the tiles in one plane at a time. Alternatively, pulses may be applied to portions of a block in one plane at a time, depending on the memory device architecture. The pulses may be applied to one set of tiles at a time, where each set includes one or more tiles.

In another option to reduce peak current consumption, as shown in fig. 25, the voltage pulses may be staggered across multiple dies in a multi-die memory device.

Further, by setting Vbl to Vsource when the SGS and SGD transistors are in a conductive state, current consumption can be reduced. This will tend to prevent current from flowing in the string because both ends of the string are at the same potential. Another approach is to turn off the SGD or SGS transistors (but not both) so there is no current through them. One of the SGS or SGD transistors should be conductive so that the channel voltage is not floated.

The pulses may be emitted periodically, such as about once every few minutes or once every hour. The term "periodic" is meant to encompass fixed intervals as well as varying intervals. In the case where the word line has begun to discharge, the pulse returns the block to the second read condition. The pulse may be implemented without keeping the tracking block in the first read condition or the second read condition. In some cases, due to the recent sense operation, the block may already be in the second read condition when the pulse is applied. In this case, the pulse may have little or no effect. In other cases, the block may be at or near the first read condition. In this case, the pulse may have a significant effect on returning the block to the second read condition. In one approach, the periodic issuance of pulses may begin in response to a power-up event in the memory device. This event forces all word lines to 0V and a first read condition is entered.

Step 1600 starts a timer. At step 1601, the timer continues to count. A decision step 1602 determines whether the timer has counted to a specified period. Block 1602a indicates that the period may be adjusted based on the temperature, e.g., such that the period is shorter when the temperature is higher. See fig. 16D. If decision step 1602 is false, step 1601 is repeated and the timer continues to count. If decision step 1602 is true, step 1603 resets a timer and step 1604 includes refreshing memory cells in one or more blocks using voltage pulses. Refreshing involves raising the Vth of at least the lower state cell back to the second read condition. Block 1604a indicates that the duration and/or amplitude of the voltage pulse may be adjusted. For example, adjustments may be made based on time since last sensing, WL voltage, and temperature, as discussed with respect to fig. 15C-15E, respectively.

FIG. 16B depicts a graph of periodic voltage pulses according to the process of FIG. 16A. The vertical axis plots voltage and the horizontal axis plots time. The exemplary pulses 1610, 1620, and 1630 have a duration represented by arrow 1625 and a period represented by arrow 1626. Between pulses, the word line voltage may couple upward and begin to decay, as illustrated by curves 1611, 1621, and 1631. Other operations involving the application of voltages to the word lines, such as read and program operations, may occur between periodic voltage pulses. In the example provided, each voltage pulse has a common duration. In another approach, the duration may vary. Further, in the example provided, the voltage pulses are provided using a common period (e.g., time between pulses). In another approach, the period may vary.

FIG. 16C depicts a graph of channel voltage according to FIG. 16B. The channel voltage may be coupled lower and then raised, resulting in upward coupling of the word line, as discussed. For example, pulse 1610 ramps up at t0 and ramps down at t1, resulting in a downward spike in Vch as shown by curve 1616. The pulse 1620 ramps up at t3 and ramps down at t4, resulting in a downward spike in Vch as shown by curve 1627. The pulse 1630 ramps up at t6 and ramps down at t7, resulting in a downward spike in Vch as shown by curve 1636. The word line voltages begin to couple upward at t2, t5, and t 8.

Fig. 16D depicts a graph of pulse period versus temperature according to block 1602a of fig. 16A. As mentioned, the period may be shorter when the temperature is higher. The high temperature represents the worst case in which the discharge rate of the word line is the greatest. In one method, for example, the cycle is set to a few minutes (e.g., 1 to 10 minutes) for a temperature higher than room temperature, and 1 to 2 hours for a temperature of room temperature or lower.

FIG. 17A depicts an exemplary process according to block 13 in FIG. 1C. This feature includes performing a soft erase just after a read or program operation (block 13). As mentioned, after a sensing operation (e.g., a read or verify test), if the word line voltage is floated, the word line voltage is coupled up through the channel. Step 1700 includes receiving a read or program command for a selected memory cell (e.g., connected to a selected word line) in the block. Step 1701 includes performing a read or verify of the selected memory cell. The verify operation is performed with respect to the programming operation as discussed, for example, with respect to fig. 9. Step 1702 includes performing a soft erase of the block.

Prior to receiving a read command, the block is subjected to a normal erase operation such as that shown in fig. 17B and 17C, followed by a program operation such as that shown in fig. 9. Before receiving a program command, the block is subjected to a normal erase operation.

FIG. 17B depicts a graph of an exemplary erase voltage applied to a substrate during a normal erase operation. Verase is plotted on the vertical axis and erase loop number is plotted on the horizontal axis. Verase has an initial amplitude of Vinit and steps up in amplitude in each successive erase loop. In this example, a total of three loops are used to complete the erase operation. Erase voltages 1711, 1712, and 1713 are applied in erase loops 1, 2, and 3, respectively. As an example, Verase is a voltage applied to the substrate (p-well) via local interconnects. As an example, Verase may have an amplitude of up to 20-25V.

FIG. 17C depicts a graph of verify voltages applied to word lines in a block according to FIG. 17B. The vertical axis depicts Vwl (word line voltage) and the horizontal axis depicts erase loop number. An exemplary erase verify voltage 1714 is depicted. For example, this voltage (VvEr) may have an amplitude of approximately 0V. Typically, an erase verify voltage is applied after each erase voltage as part of an erase verify test of the block.

Fig. 18A depicts the configuration of the example memory string 1200 of fig. 12A when holes are introduced from the substrate to the channel and the channel begins to neutralize in a soft erase operation, in accordance with step 1702 of fig. 17. Following the configuration of fig. 12A, the p-well voltage is raised to 5V, for example, causing holes ("h +") from the substrate to enter the channel to begin neutralizing the channel voltage. See also fig. 19A-19D. The control gate of the SGS transistor may be set, for example, to 0V so that the transistor is in a conductive state for holes.

The electrons begin to combine with the holes as indicated by the reduced number of electrons compared to fig. 12A. During this time, the word lines may be driven at 0V so that they are not coupled up. The control gate of the SGD transistor may also be driven at 0V. This process is referred to as soft erase because it is similar to what happens in normal erase operations, but to a lesser extent. For example, in a normal erase operation, such as shown in FIGS. 17B and 17C, the p-well may be raised to a much higher voltage of 20-25V, as an example. The normal erase operation provides a sufficiently high channel-to-gate voltage that drives electrons out of the charge trapping layer of the cell and lowers the Vth of the programmed cell to the Vth level of the erased state. Typically, in a normal erase operation, a cell is erased in multiple iterations. Each iteration involves applying a p-well voltage, followed by performing a verify test using verify level VvEr (fig. 8A). Soft erase differs in that the channel-to-gate voltage is not high enough to erase the cell. Furthermore, there is typically no check test or use of multiple iterations. Furthermore, the duration of the erase voltage on the p-well may be less during soft erase than during normal erase. Soft erase provides a channel-to-gate voltage that is sufficient to neutralize the channel without erasing the memory cell.

In one approach, the magnitude of the soft erased p-well voltage is less than 25-50% of the magnitude of the normal erase, and/or the duration of the soft erased p-well voltage is less than 25-50% of the duration of the normal erase.

Fig. 18B depicts the configuration of an exemplary memory string when the channel is fully neutralized in the soft erase operation according to step 1702 of fig. 17 and 18A. The channel is fully neutralized so that Vch is 0V. The word line voltage is floated, but remains at about 0V because there is no upward coupling from the channel.

FIGS. 19A-19D illustrate exemplary waveforms in a read operation followed by a soft erase, consistent with FIG. 17.

FIG. 19A depicts a graph of exemplary waveforms in a read operation, which is followed by a soft erase. FIG. 19B shows the channel voltage during soft erase. FIG. 19C shows the SGS transistor voltage during soft erase. FIG. 19D depicts the p-well voltage during soft erase. The waveforms 1115-1117 and 1120-1122 of FIG. 10C are repeated. As the p-well voltage Vp-well increases, soft erase occurs from t14-t16 (curve 1930). For example, the word line is driven at 0V (a lower level than the pass voltage) during soft erase (curve 1033) so that the word line voltage does not float higher as Vch goes up. Subsequently, after t17, the word line voltage may float (curve 1034). Although the word line voltage is floating at this time, it does not float to a higher level because the channel voltage has reached an equilibrium condition (Vch ═ 0V). Curve 1910 represents the channel voltage, which begins to couple down at t13 and gradually returns to 0V at t 15. Time margins of t16-t15 are provided to ensure that the channel voltage has completed its transition before Vp-well ramps back to 0V from t16-t 17. At the same time that sensing occurs, Vsgs (curve 1920) rises and when Vwl also ramps down, it ramps down to 0V at t 12.

The time required to ramp up Vp-well may be significant due to the relatively large capacitance of the p-well on the substrate. Typically, the p-well extends below the block in the plane. Another type of soft erase, described next, uses Gate Induced Drain Leakage (GIDL) from SGS and/or SGD transistors to introduce holes into the channel. This may charge the channel faster to reduce the overall consumption of the soft erase process.

FIG. 20A depicts the configuration of an exemplary memory string just after discharging the word lines at the end of the sense operation, where coupling in a soft erase operation according to step 1702 of FIG. 17 is used to lower the SGD and SGS transistor voltages. In fig. 20A-20C, soft erase uses GIDL to shorten the soft erase time. GIDL soft erase involves biasing the SGS and/or SGD transistors of the string with negative gate-to-drain/source voltages. The amount of GIDL hole current is greater when the magnitude of the negative gate-to-drain/source voltage is greater.

When negative voltages are not available in the memory device to directly drive the SGS and/or SGD control gates with negative voltages, the SGS and/or SGD control gate voltages may be coupled down to a negative level using an adjacent word line. In this case, the adjacent word line may be a non-data or dummy word line. For example, control gate 1211 may represent a dummy word line such as WLD4, and control gate 1215 may represent a dummy word line such as WLD2 (see fig. 4 and 7A).

21A-21D, the word line voltage may be ramped down from its peak level of Vpass to an intermediate level of VpassL before ramping down to a final level of 0V. When the word line voltage is ramped down from Vpass to VpassL, the SGS and/or SGD control gate voltages are ramped down from their peak levels to 0V. Subsequently, the SGS and/or SGD control gate voltages are floated (e.g., disconnected from the voltage drivers) so that they are coupled down to a negative level when the word line voltage VpassL ramps down to 0V. For example, VpassL can be 4.5V, such that the SGS and/or SGD control gate voltages are coupled down to about-4V. See fig. 20B. Transitions from VpassL to 0V provide a sufficient amount of coupling down, while transitions from VpassL to 0V may provide excessive coupling down to SGS and/or SGD control gates. VpassL can be made relatively high to provide relatively more GIDL hole current.

FIG. 20A shows how the SGS and/or SGD control gate voltages float lower from 0V while the dummy word line transitions from VpassL to 0V. The data word line is driven at 0V to prevent changes due to coupling from the channel. The channel voltage is negative at this time.

FIG. 20B depicts the configuration of an exemplary memory string just after the word lines are discharged at the end of the sense operation, where the SGD and SGS transistor voltages are reduced using the driven negative voltages in a soft erase operation according to step 1702 of FIG. 17. When negative voltages are available in the memory device, the SGS and/or SGD control gates may be driven directly with negative voltages, such as-4V, instead of using the coupling-down process of fig. 20A.

22A-22D, the word line voltage may be ramped down from its peak level of Vpass to a final level of 0V. The SGS and/or SGD control gate voltages are ramped down from their peak levels to negative levels. The channel voltage is negative at this time.

Fig. 20C depicts an exemplary memory string configuration when GIDL is used to introduce holes from the SGD and SGS transistors into the channel and the channel begins to neutralize in step 1702 according to fig. 17 and a soft erase operation according to fig. 20A or 20B. This configuration shows how holes are generated in the channel from SGS and/or SGD transistors due to the negative voltage coupled or driven down with the proper biasing of these transistors. The channel voltage begins to neutralize and then fully neutralize, such as shown in fig. 18B.

21A-21D depict waveforms in soft erase where the SGS and/or SGD transistors are coupled down to a negative voltage to generate holes by GIDL, consistent with FIGS. 20A and 20C.

FIG. 21A depicts a graph of exemplary waveforms in a read operation followed by a soft erase in which the pass voltage is ramped down to VpassL before ramping down to 0V, consistent with FIGS. 20A and 20C. Waveforms 1115 and 1116 and 1120-1122 of FIG. 10C are repeated. Waveform 1117a corresponds to waveform 1117 except that the word line voltage is ramped down from t12-t14 to Vpass (the intermediate level), between the peak level of Vpass and 0V. The word line voltage is held at VpassL from t14-t15 to ensure that the desired level curve 2110 is reached before t15 ramps down from VpassL to V, indicating that the channel voltage is coupled down and then rises, as previously discussed.

When the word line voltage is ramped down 0V from VpassL at t15, this results in the coupling down of the SGS and/or SGD control gate voltages as shown. The SGS and/or SGD transistors are biased at this time to generate holes in the channel due to GIDL, so that the channel is charged up, and soft erase of the memory cells in the block occurs from t15-t 17. For example, the wordline voltage is driven at 0V during soft erase (curve 2111). Subsequently, after t18, the word line voltage may be floated (curve 2112).

FIG. 21B depicts channel voltages during one example of soft erase. Graph 2110 represents the channel voltage, which begins to couple down at t13, and gradually returns to 0V at t 16. Time margins of t17-t16 are provided to ensure that the channel voltage has completed its transition before Vsgd/Vsgs no longer floats, but rather t17 returns to being driven at 0V.

FIG. 21C depicts SGS and/or SGD transistor voltages during one example of soft erase. The SGS and/or SGD control gate voltages (shown 2120) are ramped down from t13-t14a to 0V, and then float from t14a-t17 (as indicated by the dashed lines).

FIG. 21D plots p-well voltage during one example of soft erase. Vp-well (curve 2130) can remain at a level such as 1V before t18 ramps down to 0V during soft erase.

Fig. 22A-22D depict waveforms in soft erase in which SGS and/or SGD transistors are driven with a negative voltage to bias the transistors to generate holes through GIDL, consistent with fig. 20B and 20C.

FIG. 22A depicts a graph of exemplary waveforms in a read operation, which is followed by a soft erase. This soft erase process can be shortened in time compared to the soft erase of FIGS. 21A-21D because the pass voltage is not held at VpassL. The waveforms 1115-1117 and 1120-1122 of FIG. 10C are repeated. Waveform 2110 represents the channel voltage that is coupled down at t13 and then boosted, as previously discussed.

From t13-t14, the SGS and/or SGD control gate voltage is ramped down to a negative voltage, causing the SGS and/or SGD transistors to generate holes in the channel due to GIDL. The channel is charged up and soft erase of the memory cells in the block occurs from t14-t 16. For example, during soft erase (curve 2211), the word line voltage is driven at 0V. Subsequently, after t17, the word line voltage may be floated (curve 2212).

FIG. 22B depicts channel voltage during one example of soft erase. Curve 2210 represents the channel voltage starting to couple down at t13 and gradually returning to 0V at t 15. Time margins of t16-t15 are provided to ensure that the channel voltage has completed its transition before Vsgd/Vsgs ramps back to 0V at t 16.

FIG. 22C depicts SGS and/or SGD transistor voltages during one example of soft erase. The SGS and/or SGD control gate voltages (shown as 2220) ramp down to negative values from t13-t14 and then ramp up to 0V at t 16.

FIG. 22D depicts the p-well voltage during one example of soft erase. Vp-well (curve 2230) can remain at a level such as 1V before t17 ramps down to 0V during soft erase.

FIG. 23 shows an exemplary block diagram of the sense block 51 in the column control circuit of FIG. 1A. The column control circuit may include a plurality of sense blocks, where each sense block performs a sensing (e.g., reading) operation of a plurality of memory cells via a respective bit line.

In one approach, the sense block includes a plurality of sense circuits, also referred to as sense amplifiers. Each sensing circuit is associated with data latching and caching. For example, exemplary sensing circuits 2350a, 2351a, 2352a and 2353a are associated with caches 2350c, 2351c, 2352c and 2353c, respectively. In one approach, different subsets of bit lines may be sensed using different respective sense blocks. This allows the processing load associated with the sensing circuit to be divided and processed by the respective processors in each sensing block. For example, the sense circuit controller 2360 may be in communication with the sense circuits and the latched set (e.g., sixteen). The sensing circuit controller may include precharge circuits 2361 that provide a voltage to each sensing circuit to set the precharge voltage. The sensing circuit controller may also include a memory 2362 and a processor 2363.

FIG. 24A depicts an exemplary circuit for providing voltages to a block of memory cells. In this example, row decoder 2401 provides voltages to the word lines and select gates of each block in block set 2410. The set may be in a plane and contain tiles BLK0 through BLK 7. The row decoder provides control signals to pass gates 2422, which connect the blocks to the row decoder through gates 2422. Typically, operations (e.g., programming, reading, or erasing) are performed on one selected block at a time. The row decoder may connect the global control lines 2402 to local control lines 2403 (word lines or select gate lines). The control lines represent conductive paths. A voltage is provided on the global control line from a voltage source 2420. The voltage source may provide a voltage to switch 2421, with switch 2421 connected to the global control line. A pass gate 2424 (also referred to as a pass transistor or pass transistor) is controlled to pass a voltage from a voltage source 2420 to a switch 2421. As an example, voltage source 2420 may provide voltages on the Word Line (WL), SGS control gate, and SGD control gate.

Various components comprising the row decoder may receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

In normal erase or soft erase, a source line voltage source 2430 provides an erase voltage to a source line/diffusion region (p-well) in the substrate via a control line 2432. In one approach, the source diffusion region 2433 is common to the blocks. The set of bit lines 2442 is also shared by the blocks. A bit line voltage source 2440 provides a voltage to the bit line. In one possible implementation, the voltage source 2420 is close to the bit line voltage source.

The word line voltage detector 2460 is connected to one of the word lines in each block. The voltage detector may include an operational amplifier comparator, such as shown in fig. 24B, for example.

FIG. 24B depicts an exemplary circuit according to FIG. 24B for detecting word line voltage according to the process of FIG. 13A. The circuit comprises a subset of the circuit of fig. 24A as it relates to word line voltage detection in the exemplary block. The word lines and select gate lines (control lines) of BLK0 are illustrated. A pass gate is connected to each control line. For example, pass gate 2470 is connected to the SGD0 control line. The control gate of the pass gate is connected to a common path 2471. When the voltage on the path is high enough, the control lines are connected to the voltage driver via the row decoder 2401. When the voltage on the path is low enough, the control line is disconnected from the voltage driver and floats.

In this example, when the control signal on line 2472 is high enough to cause the pass gate 2412 to conduct, the word line voltage is obtained from WLL4 via a conductive path 2473 connected to word line voltage detector 2460. The word line voltage detector may include a comparator. The comparators each include a non-inverting input that receives the word line voltage Vwl, an inverting input that receives the reference voltage Vref, positive and negative power supplies + Vs and-Vs, and an output that provides Vout. If Vwl > Vref, Vout is + Vs, and if Vwl < Vref, Vout is-Vs. The analog output value may be provided to a controller that converts the analog output value to 0 or 1 bits to represent Vwl > Vref or Vwl < Vref, respectively. If the bit is 0, the controller may select one read voltage set. If bit 1, the controller may select another read voltage set. Furthermore, Vwl can be compared to different values of Vref to classify Vwl into more than two ranges. The corresponding set of read voltages may be selected based on the range into which Vwl is classified. See fig. 13C and 13D.

In one method, a first comparison is made between Vwl and a reference voltage having a first level. Then, a second comparison is made between Vwl and a reference voltage having a second level, the second level being based on the first comparison. For example, assume that Vref can be set to any one of 1, 2, or 3V. The first comparison may use Vref-2V. If Vwl <2V, the second comparison may use Vref ═ 1V. In this way, the detector can quickly classify Vwl into one of several ranges (e.g., 0-1V or 1-2V) to allow the corresponding set of read voltages to be selected.

As an example, the voltage compared to Vref may be the full word line voltage Vwl or some fraction of the word line voltage. The voltage detector may be in the peripheral region such that there is a considerable distance between the word line and the detector, resulting in an RC delay. Other problems are that the word line in the floating state may have a smaller capacitance than the conductive path 2473. These problems can be taken into account during the detection process. For example, a voltage at the detector of less than 2V may correspond to a voltage of 2V at the word line. The output of the detector may be acquired at a specified time after the word line is connected to the detector via the pass gate 2412.

In general, it is sufficient to measure the voltage of one word line in a block. It helps avoid the use of edge word lines (e.g., WLL0 or WLL10) because their voltages may be affected by edge effects. In some cases, a block may be partially programmed such that some word lines at the bottom of the block (starting with WLL 0) are programmed, while other higher word lines are not programmed. The programmed state of the cell should not significantly affect the word line voltage read.

Fig. 25 depicts a memory device 2500 in which voltage pulses are performed for multiple die, one die at a time, according to the process of fig. 16A. Three memory die 2510, 2520, and 2530 are provided as an example. Off-die control circuitry 2502 determines that a voltage pulse is to be applied (such as part of a pre-read operation), and in response, initiates application of the voltage pulse at one of the die, such as die 2530, by providing a command to interface 2530 d. In response to the command, an on-die control circuit 2530c instructs the voltage driver 2531 to provide voltage pulses to the row decoder 2530b and instructs the row decoder to switch the voltage pulses from the voltage driver to the word lines in the array 2530 a. As an example, the on-die control circuit may be the control circuit 110 of fig. 1A. When the operation is completed for memory die 2530, it reports back to the off-die control circuitry.

The off-die control circuitry may implement a short latency, such as 10 microseconds, before causing the voltage pulse to be applied at the die 2520. The off-die control circuit provides commands to interface 2520 d. In response to the command, the on-die control circuit 2520c instructs the voltage driver 2521 to provide voltage pulses to the row decoder 2520b, and instructs the row decoder to switch the voltage pulses from the voltage driver to the word lines in the array 2520 a. When the operation is completed for memory die 2520, it reports back to the off-die control circuitry.

Finally, the off-die control circuitry provides commands to interface 2510d of die 2510. In response to the commands, the on-die control circuit 2510c instructs the voltage driver 2511 to provide voltage pulses to the row decoder 2510b and instructs the row decoder to switch voltage pulses from the voltage driver to word lines in the array 2510 a. When the operation is complete for memory die 2510, it reports back to the off-die control circuit.

As mentioned, the peak power consumption of the voltage driver is reduced because voltage pulses are applied at one die at a time.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (9)

1. An apparatus, comprising:

a block of memory cells (BLK0-BLK 3); and

control circuitry (110, 122) configured to perform an operation involving sensing of selected memory cells of the block in response to a command to perform the operation, and to perform a soft erase of the block of memory cells after the operation, wherein:

the selected memory cells are arranged in sets (700n-703n, 710n-713n, 720n-723n, 730n-733n) of series-connected memory cells including unselected memory cells;

each set of series-connected memory cells includes a channel (665);

to perform the sensing of the selected memory cell, the control circuitry is configured to apply a sense voltage (VvA-VvG; VrA-VrG) to the selected memory cell while a pass voltage is applied to unselected memory cells of the block;

after the sensing of the selected memory cell, the control circuit is configured to drive the voltage of the unselected memory cells at a level lower than the pass voltage, resulting in a coupling down of the channel; and is

The control circuit is configured to perform the soft erase when the channel is coupled down.

2. The apparatus of claim 1, wherein:

the memory cells are connected to a set of word lines (WLL0-WLL10) and arranged in sets of series-connected memory cells (700n-703n, 710n-713n, 720n-723n, 730n-733 n);

each set of series-connected memory cells includes a channel (665), a source terminal (613), and a select gate transistor at the source terminal;

the source terminal is in contact with a p-well (611b) of a substrate (611); and is

To perform the soft erase, the control circuit is configured to bias the p-well and the select gate transistor at the source end of the set of series-connected memory cells to pass holes from the p-well into the channel.

3. The apparatus of claim 1 or 2, wherein:

the memory cells are connected to a set of word lines (WLL0-WLL10) and arranged in sets of series-connected memory cells (700n-703n, 710n-713n, 720n-723n, 730n-733 n);

each set of series-connected memory cells includes a channel (665), a source terminal (613), and a select gate transistor at the source terminal;

the source terminal is in contact with a p-well (611b) of a substrate (611); and is

To perform the soft erase, the control circuit is configured to bias the select gate transistor with a negative gate-to-drain voltage.

4. The apparatus of claim 3, wherein:

the control circuitry is configured to perform a normal erase of the block of memory cells in response to an erase command of the block;

to perform the normal erase, the control circuit is configured to bias the substrate and the select gate transistor at the source end of the set of series-connected memory cells for a first duration; and is

To perform the soft erase, the control circuit is configured to bias the substrate and the select gate transistor at the source terminal of the set of series-connected memory cells for a second duration that is less than 25-50% of the first duration, and/or for a magnitude of bias on the substrate during the soft erase that is less than 25-50% of a magnitude of bias on the substrate during the normal erase.

5. The apparatus of claim 1 or 2, wherein:

the memory cells are connected to a set of word lines and arranged in a set of serially connected memory cells (700n-703n, 710n-713n, 720n-723n, 730n-733 n);

each set of series-connected memory cells includes a channel (665), a source terminal (613), and a select gate transistor; and is

To perform the soft erase, the control circuit is configured to bias the control gates (1010, 1016) of the select gate transistors of the set of series-connected memory cells with a negative voltage to generate holes in the channels by gate-induced drain leakage.

6. The apparatus of claim 1 or 2, wherein:

the operation includes a read operation in which the sensing includes reading a data state of the selected memory cell or a program operation in which the sensing includes a verify test of the selected memory cell.

7. The apparatus of claim 1 or 2, wherein:

the control circuitry is configured to perform a normal erase of the block of memory cells in response to an erase command of the block;

performing the soft erase in a single iteration; and is

The normal erase is performed in a plurality of iterations.

8. A method, comprising:

applying a sense voltage to a selected memory cell in a connected set of memory cells (700n-703n, 710n-713n, 720n-723n, 730n-733n) while applying a pass voltage to an unselected memory cell of the connected set of memory cells;

sensing the selected memory cell while applying the sense voltage;

after the sensing, driving the control gate voltage of the unselected memory cell from the pass voltage to a lower level, resulting in a downward coupling of the voltage of the channel of the connected set of memory cells;

generating a hole current in the channel to neutralize a voltage of the channel while driving the control gate voltage at the lower level; and

floating the control gate voltage of the unselected memory cell after generating the hole current.

9. The method of claim 8, wherein:

generating the hole current includes biasing a select gate transistor of the connected set of memory cells to cause gate induced drain leakage.

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