CN108512783A - A kind of status information acquiring method and equipment - Google Patents

A kind of status information acquiring method and equipment Download PDF

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Publication number
CN108512783A
CN108512783A CN201810239739.6A CN201810239739A CN108512783A CN 108512783 A CN108512783 A CN 108512783A CN 201810239739 A CN201810239739 A CN 201810239739A CN 108512783 A CN108512783 A CN 108512783A
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event
register
bit
port
identification
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徐在水
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New H3C Technologies Co Ltd
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New H3C Technologies Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
    • G06F11/3093—Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer And Data Communications (AREA)

Abstract

A kind of status information acquiring method of the application offer and equipment, this method include：Processor reads the identification information of each event bit from the event registers of logical device；It is that the port register configures an event bit, and establishes the first correspondence of the port register and the event bit in event registers for each port register of logical device；For each event bit of reading, if the identification information of the event bit is first identifier, processor is according to the status information of the first correspondence read port from the corresponding port register of the event bit；The identification information of the event bit is first identifier or second identifier, first identifier is for indicating that the status information of at least one port of port register has changed, and second identifier is for indicating that the status information of all of the port of port register does not change.By the technical solution of the application, the read access time of status information can be reduced, improves reading efficiency.

Description

State information acquisition method and device
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for acquiring status information.
Background
Network equipment (such as routers and switches) support line cards with high port density, such as line cards with 80 ports, and the line cards include CPLDs (Complex Programmable Logic devices) in which an 8-bit port register is corresponding to each port, the port register is used to record status information of the port, such as port 0 corresponding to port register 0, port register 0 is used to record status information of port 0, and so on. Further, a CPU (central processing Unit) can access a port register in the CPLD through the local bus, and read status information from the port register.
In order to analyze whether the state information of the port changes, the CPU reads the state information of the port from each port register in turn, for example, reads the state information of the port 0 from the port register 0, and so on, reads the state information of the port 79 from the port register 79. Thus, the CPU needs to read the state information 80 times, and since the read-write efficiency of the local bus is low, the time consumed for reading the state information every time is about 400 nanoseconds, therefore, the time consumed for reading the state information 80 times is 32 microseconds, the read efficiency is very low, and the read time is very long.
Disclosure of Invention
The application provides a state information acquisition method, which is applied to network equipment, wherein the network equipment comprises a processor and a logic device, and the method comprises the following steps:
the processor reads the identification information of each event bit from an event register of the logic device; the method comprises the steps that for each port register of a logic device, an event bit is configured for the port register in an event register, and a first corresponding relation between the port register and the event bit is established;
for each read event bit, if the identification information of the event bit is a first identification, the processor reads the state information of the port from the port register corresponding to the event bit according to the first corresponding relation; the identification information of the event bit is a first identification or a second identification, the first identification is used for indicating that the state information of at least one port of the port register has changed, and the second identification is used for indicating that the state information of all ports of the port register has not changed.
The application provides a network device comprising a processor and a logic device, wherein:
the processor is used for reading the identification information of each event bit from the event register of the logic device; the method comprises the steps that for each port register of a logic device, an event bit is configured for the port register in an event register, and a first corresponding relation between the port register and the event bit is established;
the processor is further configured to, for each read event bit, if identification information of the event bit is a first identification, read state information of a port from a port register corresponding to the event bit according to the first correspondence; the identification information of the event bit is a first identification or a second identification, the first identification is used for indicating that the state information of at least one port of the port register has changed, and the second identification is used for indicating that the state information of all ports of the port register has not changed.
Based on the above technical solution, in this embodiment of the application, the identification information of each event bit may be read from the event register, if the identification information of an event bit is the first identifier, it is indicated that the state information of the port has changed, the state information of the port is read from the port register corresponding to the event bit, and if the identification information of an event bit is the second identifier, it is indicated that the state information of the port has not changed, and the reading of the state information of the port from the port register corresponding to the event bit is prohibited. In summary, the processor can read the state information of the ports from a part of the port registers without reading the state information of the ports from all the port registers, thereby reducing the number of times of reading the state information, reducing the time of reading the state information, and improving the reading efficiency. Furthermore, when the processor reads the state information of the port through the local bus, the occupied time of the local bus can be reduced, and the real-time performance of rapidly responding to the state change of the port is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments of the present application or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings of the embodiments of the present application.
FIG. 1 is a schematic diagram of an application scenario in an embodiment of the present application;
FIG. 2 is a flow chart of a method for obtaining status information in one embodiment of the present application;
fig. 3 is a flowchart of a status information acquisition method according to another embodiment of the present application;
fig. 4 is a hardware configuration diagram of a network device according to an embodiment of the present application.
Detailed Description
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein is meant to encompass any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Depending on the context, moreover, the word "if" as used may be interpreted as "at … …" or "when … …" or "in response to a determination".
An embodiment of the present application provides a method for acquiring status information, where the method may be applied to a network device (e.g., a router, a switch, etc.), and as shown in fig. 1, as an application scenario schematic diagram of the embodiment of the present application, the network device may include a processor (e.g., a CPU, etc.) and a line card (also referred to as a board card, e.g., an interface board, a service board, etc.), the line card may be a line card with high port density, and may include a logic device (e.g., a CPLD, etc.) and a plurality of ports, which is described by taking 80 ports as an example in fig. 1, and in actual application, the line card may also be other number of ports, which is not limited thereto. The type of the port may include, but is not limited to, an optical module, an RJ45 port, and the like, and the type of the port is not limited, and for convenience of description, the optical module is taken as an example in the following. Further, the optical module may include, but is not limited to, an SFP (small form Factor, soldered small form Factor) optical module, and the like.
Referring to fig. 1, for each port, there may be multiple status signals (e.g., MOD _ DEF, TX _ FAULT, LOS, etc.) and multiple control signals (e.g., DISABLE, LED _ RED, LED _ yes, etc.) and these status signals and these control signals may be connected to the logic device.
MOD _ DEF is an optical module presence indication signal, the signal direction is from the optical module to the logic device, when MOD _ DEF is 0, the optical module is not in place, and when MOD _ DEF is 1, the optical module is in place. TX _ FAULT is a FAULT signal of the laser of the optical module, the signal direction is from the optical module to the logic device, when the TX _ FAULT is 0, the FAULT of the laser is indicated, and when the TX _ FAULT is 1, the normal of the laser is indicated. LOS is that the optical module receives an optical power low signal, the signal direction is from the optical module to the logic device, when the LOS is 0, the received optical power is lower than the receiver sensitivity; when the LOS is 1, it indicates normal.
The DISABLE is an optical module enable/DISABLE signal, the signal direction can be from the logic device to the optical module, and when the DISABLE is 0, the transmitting laser is normal; when DISABLE is 1, it indicates that the transmit laser is disabled. LED _ RED is a RED light signal of a double-color indicator light, the signal direction can be from a logic device to an optical module, and when the LED _ RED is 0, the RED light is on; when LED _ RED is 1, it indicates that the RED light is off. The LED _ YELLOW is a YELLOW light signal of a bicolor indicator light, the signal direction can be from a logic device to a light module, and when the LED _ YELLOW is 0, the signal direction indicates that the YELLOW light is on; when LED _ YELLOW is 1, it indicates that the YELLOW light is off.
In another example, LED _ RED and LED _ YELLOW may be replaced with control signals such as LEDA, LEDB, and LEDC, which are two-color indicator signals, indicating normally off when LEDA, LEDB, and LEDC is 000, indicating on green when LEDA, LEDB, and LEDC is 001, indicating on RED when LEDA, LEDB, and LEDC is 010, indicating on green when LEDA, LEDB, and LEDC is 011, and indicating on RED when LEDA, LEDB, and LEDC is 100.
In one example, the logic device stores an 8-bit port register for each port, and the port register is used to record status information (e.g., MOD _ DEF, TX _ FAULT, LOS, etc.) and control information (e.g., LEDA, LEDB, LEDC, DISABLE, etc., or LED _ RED, LED _ YELLOW, DISABLE, etc., which are described as examples in the following processes) of the port. For example, the logic device may store a port register 0 for port 0, where the port register 0 is used to record state information and control information of port 0, and the processing for ports 1 to 79 is similar to that of port 0 and is not repeated.
Referring to table 1, which is a structural example of a port register in a logic device, a port register 0 occupies 8 bits, and an offset address is 0x0400, and similarly, port registers 1 to 79 also occupy 8 bits respectively, and the offset addresses thereof are shown in table 1 and are not repeated herein.
TABLE 1
Offset address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x0400 DISABLE0 LEDC0 LEDB0 LEDA0 reserved LOS0 TX_FAULT0 MOD_DEF0
0x0401 DISABLE1 LEDC1 LEDB1 LEDA1 reserved LOS1 TX_FAULT1 MOD_DEF1
0x0402 DISABLE2 LEDC2 LEDB2 LEDA2 reserved LOS2 TX_FAULT2 MOD_DEF2
… … … … … … … … …
0x044E DISABLE78 LEDC78 LEDB78 LEDA78 reserved LOS78 TX_FAULT78 MOD_DEF78
0x044F DISABLE79 LEDC79 LEDB79 LEDA79 reserved LOS79 TX_FAULT79 MOD_DEF79
Referring to table 1, each port register occupies 8 BITs, such as BIT0-BIT7, BIT0-BIT2 are used for recording status information of a port, BIT3 is reserved, BIT4-BIT7 is used for recording control information of a port, the content of BIT3-BIT7 is not limited, and the status information of BIT0-BIT2 is described later.
Here, BIT0 is MOD _ DEF information indicating a port, that is, BIT indication information, and when BIT0 is 0, it indicates that the BIT indication information is not BIT, and when BIT0 is 1, it indicates that the BIT indication information is BIT. The BIT1 is used to indicate TX _ FAULT information of a port, i.e., laser FAULT information, and when the BIT1 is 0, it indicates that the laser FAULT information is a laser FAULT, and when the BIT1 is 1, it indicates that the laser FAULT information is a laser normal. The BIT2 is used to indicate LOS information of the port, that is, received optical power information, and when the BIT2 is 0, it indicates that the received optical power information is that the received optical power is lower than the receiver sensitivity, and when the BIT2 is 1, it indicates that the received optical power information is that the received optical power is normal (that is, the received optical power is not lower than the receiver sensitivity).
In one example, the logic device may further provide an event register based on the port register, where the event register may include a plurality of bits, such as 8 bits, 16 bits, and the like, and 8 bits are taken as an example in the following. For ease of distinction, each bit in the event register may also be referred to as an event bit. Based on this, for each port register, an event bit may also be configured for the port register in the event register of the logic device, and a corresponding relationship between the port register and the event bit is established.
The logic device may store a corresponding relationship between the port register and the event bit, the processor may also store a corresponding relationship between the port register and the event bit, and the subsequent process introduces a process in which the logic device performs processing using the corresponding relationship and a process in which the processor performs processing using the corresponding relationship.
In one example, the number of event registers may also be related to the number of port registers, e.g., when the number of port registers is 80, then 80 event bits are required. Since each event register may include 8 bits, the 80 event bits total to occupy 10 event registers.
Referring to table 2, as a structural example of an event register in a logic device, the event register 0 occupies 8 bits, and an offset address of the event register 0 may be 0x0480, and similarly, the event registers 1 to 9 also occupy 8 bits, and the offset address refers to table 2, and is not repeated here.
TABLE 2
As can be seen from table 2, EVENT0 (i.e. BIT0 of EVENT register 0) is an EVENT BIT for port register 0, and the corresponding relationship between port register 0 and EVENT0 is established; in addition, the implementation process of the EVENT1-EVENT79 is similar to the implementation of the EVENT0, and repeated description is omitted here.
In one example, the identification information of each EVENT bit (e.g., EVENT0-EVENT79, etc.) may be a first identification (e.g., 1) for indicating that the status information of the port has changed or a second identification (e.g., 0) for indicating that the status information of the port has not changed. For example, when EVENT0 is 1, it indicates that the status information of port 0 corresponding to port register 0 has changed, i.e., one or more of the bit indication information, the laser failure information, and the received optical power information of port 0 have changed. When the EVENT0 is 0, it indicates that the state information of the port 0 corresponding to the port register 0 has not changed, that is, the on-bit indication information, the laser failure information, and the received optical power information of the port 0 have not changed.
In practical application, the optical module may update the state information of the port to a port register of the logic device, for example, the optical module of the port 0 updates the state information of the port 0 to the port register 0, and the optical module of the port 1 updates the state information of the port 1 to the port register 1, which is not limited to the update process of the state information. It is assumed that at a certain time, the status information of all port registers can be as shown in table 3, and the time is taken as an initial time, and at the initial time, the identification information of all event bits can be 0.
TABLE 3
Offset address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x0400 DISABLE0 LEDC0 LEDB0 LEDA0 reserved 1 1 0
0x0401 DISABLE1 LEDC1 LEDB1 LEDA1 reserved 0 0 1
0x0402 DISABLE2 LEDC2 LEDB2 LEDA2 reserved 0 0 0
… … … … … … … … …
0x044E DISABLE78 LEDC78 LEDB78 LEDA78 reserved 1 1 1
0x044F DISABLE79 LEDC79 LEDB79 LEDA79 reserved 1 0 0
0x0480 0 0 0 0 0 0 0 0
0x0481 0 0 0 0 0 0 0 0
… … … … … … … … …
0x0489 0 0 0 0 0 0 0 0
In the subsequent process, if the state information of the port changes, the optical module of the port updates the changed state information to the port register of the logic device. If the in-place indication information of port 0 is changed from "not in place" to "in place", the optical module of port 0 may change BIT0 of port register 0 from 0 (i.e., the in-place indication information is not in place) to 1 (i.e., the in-place indication information is in place), as shown in table 4.
TABLE 4
Offset address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x0400 DISABLE0 LEDC0 LEDB0 LEDA0 reserved 1 1 1
0x0401 DISABLE1 LEDC1 LEDB1 LEDA1 reserved 0 0 1
0x0402 DISABLE2 LEDC2 LEDB2 LEDA2 reserved 0 0 0
… … … … … … … … …
0x044E DISABLE78 LEDC78 LEDB78 LEDA78 reserved 1 1 1
0x044F DISABLE79 LEDC79 LEDB79 LEDA79 reserved 1 0 0
0x0480 0 0 0 0 0 0 0 0
0x0481 0 0 0 0 0 0 0 0
… … … … … … … … …
0x0489 0 0 0 0 0 0 0 0
In one example, the logic device may also periodically read port status information from the port register; if the state information read this time is different from the state information read from the port register last time, the logic device may determine an event bit corresponding to the port register according to a corresponding relationship between the port register and the event bit, and modify identification information corresponding to the event bit into a first identification; if the state information read this time is the same as the state information read from the port register last time, the logic device may not modify the identification information corresponding to the event bit corresponding to the port register, that is, the identification information is still the second identification.
For example, when the logic device reads the state information for the first time, the state information is shown in table 3, the state information of the port register 0 is 110, the state information of the port register 1 is 001, and the state information of the other port registers is not described again. Then, the logic device may record the state information, and the recording manner is not limited. When the logic device reads the state information for the second time, the state information is shown in table 4, the state information of the port register 0 is 111, the state information of the port register 1 is 001, and the state information of the other port registers is not described again. By comparing table 3 and table 4, since the state information of the port register 0 is changed (from 110 to 111), the EVENT bit "EVENT 0" corresponding to the port register 0 is determined according to the correspondence between the port register and the EVENT bit, and the identification information corresponding to "EVENT 0" is modified to the first identification 1, as shown in table 5, and the state information of the port register 0 recorded locally is modified to 111.
Since the status information of the port register 1 is not changed, the identification information of the EVENT bit "EVENT 1" corresponding to the port register 1 may not be modified, and the status information of the port register 1 recorded locally may not be modified. The processing procedure for other port registers is similar to that of port register 1, and is not described herein again.
TABLE 5
Offset address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x0400 DISABLE0 LEDC0 LEDB0 LEDA0 reserved 1 1 1
0x0401 DISABLE1 LEDC1 LEDB1 LEDA1 reserved 0 0 1
0x0402 DISABLE2 LEDC2 LEDB2 LEDA2 reserved 0 0 0
… … … … … … … … …
0x044E DISABLE78 LEDC78 LEDB78 LEDA78 reserved 1 1 1
0x044F DISABLE79 LEDC79 LEDB79 LEDA79 reserved 1 0 0
0x0480 0 0 0 0 0 0 0 1
0x0481 0 0 0 0 0 0 0 0
… … … … … … … … …
0x0489 0 0 0 0 0 0 0 0
When the logic device reads the state information for the third time, the processing procedure of the logic device is similar to that of the second reading, and details are not repeated here. In a word, the logic device may periodically read the state information, determine whether the state information read this time is the same as the state information read last time each time the state information is read, modify the identification information of the corresponding event bit to the first identification if not, and not modify the identification information of the event bit if yes.
In the application scenario, referring to fig. 2, a flowchart of the state information obtaining method is shown.
Step 201, a processor reads identification information of each event bit from an event register of a logic device; the method comprises the steps that for each port register of a logic device, an event bit is configured for the port register in the event register, and the corresponding relation between the port register and the event bit is established.
Step 202, for each read event bit, if the identification information of the event bit is the first identification, the processor reads the state information of the port from the port register corresponding to the event bit according to the corresponding relationship between the port register and the event bit. The identification information of the event bit may be a first identification used for indicating that the state information of at least one port of the port register has changed or a second identification used for indicating that the state information of all ports of the port register has not changed.
In addition, if the identification information of the event bit is the second identification, the processor may not read the state information of the port from the port register corresponding to the event bit, but may read the state information of the port from the port register corresponding to the event bit after the identification information of the event bit is the first identification.
Wherein, the processor can read the identification information of each event bit in the event register through a Local Bus (Local Bus). For example, reading the EVENT register 0 through the local bus to obtain the identification information of each EVENT bit in the EVENT register 0, as shown in table 5, the identification information of EVENT0 of the EVENT register 0 is 1, and the identification information of EVENT1-EVENT7 is 0; the processing procedure of the event register 1-the event register 10 is similar to that of the event register 0, and is not described herein again. Finally, the identification information of the EVENT0 is 1, and the identification information of the EVENT1-EVENT79 is 0, so that the status information of the port 0 can be read from the port register 0 corresponding to the EVENT0, and the status information of the ports 1-79 does not need to be read from the port registers 1-79 corresponding to the EVENT1-EVENT 79.
Among other things, the processor may determine the offset address 0x0480 of the EVENT register 0 and read 8-bit values starting from the offset address 0x0480, the 8 values (00000001) being the identification information of EVENT0-EVENT 7. Similarly, an offset address 0x0481 of the EVENT register 1 may be determined, and a value of 8 bits, i.e., identification information of EVENT8-EVENT15, is read from the offset address 0x 0481.
Here, since the correspondence relationship between the port register 0 and the EVENT0 has been established, after determining that the identification information of the EVENT0 is 1, it may be determined that the port register corresponding to the EVENT0 is the port register 0. Then, offset address 0x0400 of port register 0 may be determined and 8-BIT values may be read starting from offset address 0x0400, the 8 values being the contents of port register 0, which may include the status information of port 0, e.g., BIT0-BIT2 of port register 0 being the status information of port 0.
In one example, after the processor reads the state information of the port from the port register corresponding to the event bit, the processor may further modify the identification information corresponding to the event bit to the second identification.
For example, after the processor reads the state information of port 0 from port register 0 corresponding to the EVENT0, the processor may also modify the identification information corresponding to the EVENT0 to the second identification 0.
In the above embodiment, the reading of the identification information of each event bit from the event register by the processor may include, but is not limited to: in the first mode, the processor periodically reads the identification information of each event bit from the event register. Reading the identification information of each event bit from the event register when the processor receives an interrupt signal sent by the logic device; when the logic device learns that the state information of the port changes, the logic device can send an interrupt signal to the processor, so that the processor receives the interrupt signal.
As for the second method, when knowing that the state information of the ports changes, the logic device may generate an interrupt signal (as long as the state information of any one or more ports changes, the logic device may generate the interrupt signal), and send the interrupt signal to the processor, and when receiving the interrupt signal, the processor may read the identification information of each event bit from the event register.
In one example, when the line card is started, the processor may read the status information in all the port registers, and in the following process, only the changed status information and the unchanged status information are read from the port registers in steps 201 to 202, and the processor may not read from the port registers any more.
Based on the above technical solution, in the embodiment of the present application, in order to analyze whether the state information of the port changes, the processor may read the state information of the port from a part of the port registers, instead of reading the state information of the port from all the port registers, so as to reduce the number of reading the state information, reduce the reading time of the state information, and improve the reading efficiency. When the processor reads the state information of the port through the local bus, the occupied time of the local bus can be reduced, and the real-time performance of quickly responding to the state change of the port is improved. When the state information of the port changes, the processor can be triggered to read the state information in real time in an interrupt mode.
For example, in the conventional method, if there are 80 port registers, the processor needs to read each port register of the 80 port registers in turn, that is, read the port registers 80 times in total, and even if the status information of only one port changes, the processor needs to read 80 times. In the embodiment of the present application, if there are 80 port registers and 10 event registers, the processor needs to read each event register of the 10 event registers in turn, that is, read the event registers 10 times in total. In the 10 EVENT registers, a total of 80 EVENT bits are included, and assuming that only the identification information of 1 EVENT bit EVENT0 is the first identification, and the identification information of the other 79 EVENT bits is the second identification, the processor only needs to read the port register 0 corresponding to the EVENT0, that is, only 1 port register is read. Obviously, if only one port's state information changes, the processor only needs to read 11 times, significantly less than 80 times.
In one example, the logic device may further provide an integrated register based on the port register and the event register, where the integrated register may include a plurality of bits, such as 8 bits, 16 bits, and the like, and 8 bits are taken as an example in the following. For ease of distinction, each bit in the synthesis register may also be referred to as a synthesis bit. Based on this, for each event register, a synthesis bit may be configured for the event register in the synthesis register of the logic device, and a corresponding relationship between the event register and the synthesis bit is established. The logic device may store a corresponding relationship between the event register and the synthesis bit, and the processor may also store a corresponding relationship between the event register and the synthesis bit, and the subsequent process introduces a process in which the logic device performs processing using the corresponding relationship and a process in which the processor performs processing using the corresponding relationship.
The number of synthesis registers may also be related to the number of event registers, e.g. when the number of event registers is 10, then 10 synthesis bits are required. Since each synthesis register may comprise 8 bits, the 10 synthesis bits need to occupy a total of 2 synthesis registers (16 bits may be provided, of which 10 bits are allocated to the synthesis bits and the remaining 6 bits are free).
Referring to table 6, for a structural example of the synthesis register in the logic device, synthesis register 0 occupies 8 bits, the offset address is 0x0500, synthesis register 1 occupies 8 bits, and the offset address is 0x 0501. As can be seen from table 6, the EVREG0 (i.e., BIT0 of synthesis register 0) is a synthesis BIT for the event register 0, and establishes a correspondence between the event register 0 and the EVREG 0; in addition, the implementation process of the EVREG1-EVREG9 is similar to that of the EVENT0, and the detailed description is not repeated here.
TABLE 6
The identification information of each integrated bit (e.g., EVREG0-EVREG 9) may be a third identification (e.g., 1) for indicating that the event register has changed or a fourth identification (e.g., 0) for indicating that the event register has not changed. For example, when the EVREG0 is 0, it indicates that the event register 0 has not changed, i.e., the status information of the ports corresponding to the port register 0-the port register 7 has not changed. When the EVREG0 is 1, it indicates that the event register 0 has changed, that is, the status information of the ports corresponding to the port register 0 to the port register 7, there is status information that has changed.
When the logic device periodically reads the state information of the port from the port register, if the read state information is different from the state information read from the port register last time, determining an event bit corresponding to the port register according to the corresponding relation between the port register and the event bit, and modifying the identification information corresponding to the event bit into a first identification. Then, the logic device determines an event register to which the event bit belongs, determines a synthetic bit corresponding to the event register according to a corresponding relationship between the event register and the synthetic bit, and modifies identification information corresponding to the synthetic bit into a third identification. If the state information read this time is the same as the state information read from the port register last time, the identification information corresponding to the event bit corresponding to the port register is not modified, and the identification information corresponding to the comprehensive bit is not modified.
For example, when the logic device reads the state information for the first time, the state information is shown in table 3, and when the logic device reads the state information for the second time, the state information is shown in table 4, and the synthesis registers are not shown in tables 3 and 4, in practical application, tables 3 and 4 may include synthesis registers, which is not described herein again. Since the state information of the port register 0 is changed (from 110 to 111), the EVENT bit "EVENT 0" corresponding to the port register 0 is determined according to the correspondence between the port register and the EVENT bit, and the identification information corresponding to "EVENT 0" is modified to the first identification 1. Then, the EVENT register 0 to which the "EVENT 0" belongs is determined, the integrated bit "EVREG 0" corresponding to the EVENT register 0 is determined according to the correspondence between the EVENT register and the integrated bit, and the identification information corresponding to the "EVREG 0" is modified to the third identification 1, as shown in table 7.
TABLE 7
Offset address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x0400 DISABLE0 LEDC0 LEDB0 LEDA0 reserved 1 1 1
0x0401 DISABLE1 LEDC1 LEDB1 LEDA1 reserved 0 0 1
0x0402 DISABLE2 LEDC2 LEDB2 LEDA2 reserved 0 0 0
… … … … … … … … …
0x044E DISABLE78 LEDC78 LEDB78 LEDA78 reserved 1 1 1
0x044F DISABLE79 LEDC79 LEDB79 LEDA79 reserved 1 0 0
0x0480 0 0 0 0 0 0 0 1
0x0481 0 0 0 0 0 0 0 0
… … … … … … … … …
0x0489 0 0 0 0 0 0 0 0
0x0500 0 0 0 0 0 0 0 1
0x0501 0 0
In the application scenario, referring to fig. 3, a flowchart of the status information obtaining method is shown.
In step 301, the processor reads the identification information of each synthesis bit from the synthesis register of the logic device. The method comprises the steps that for each event register of a logic device, a comprehensive bit is configured for the event register in the comprehensive register, and the corresponding relation between the event register and the comprehensive bit is established.
Step 302, for each read integrated bit, if the identification information of the integrated bit is a third identification, the processor reads the identification information of each event bit from the event register corresponding to the integrated bit according to the corresponding relationship between the event register and the integrated bit. If the identification information of the integrated bit is the fourth identification, the identification information of each event bit is not read from the event register corresponding to the integrated bit, but the identification information of each event bit is read from the event register corresponding to the integrated bit after the identification information of the integrated bit is the third identification. The identification information of the comprehensive bit is a third identification or a fourth identification, the third identification is used for indicating that the event register is changed, and the fourth identification is used for indicating that the event register is not changed.
Step 303, for each read event bit, if the identification information of the event bit is the first identification, the processor reads the state information of the port from the port register corresponding to the event bit according to the corresponding relationship between the port register and the event bit. Step 303 is similar to step 202, and is not described herein again.
In one example, the processor may read the identification information of each synthesis bit in the synthesis register via the local bus. For example, the synthesis register 0 is read through the local bus to obtain the identification information of each synthesis bit in the synthesis register 0, as shown in table 7, the identification information of the EVREG0 is 1, and the identification information of the EVREG1-EVREG7 is 0; further, it can be obtained that the identification information of EVREG8-EVREG9 in synthesis register 1 is 0. Since the identification information of the EVREG0 is 1 and the identification information of the EVREGs 1-9 is 0, the identification information of each event bit is read from the event register 0 corresponding to the EVREG0, and the identification information of the event bit does not need to be read from the event registers 1-9. Further, reading the EVENT register 0 through the local bus to obtain that the identification information of the EVENT0 is 1, and the identification information of the EVENT1-EVENT7 is 0; since the identification information of the EVENT0 is 1 and the identification information of the EVENT1-EVENT7 is 0, the status information of the port 0 is read from the port register 0 corresponding to the EVENT0, but the status information of the ports 1-7 does not need to be read from the port registers 1-7.
Among other things, the processor may determine an offset address 0x0500 of the synthesis register 0 and read an 8-bit value starting from the offset address 0x0500, the 8 values (00000001) being identification information of the EVREG0-EVREG 7. Similarly, the offset address 0x0501 of the synthesis register 1 is determined, and the 8-bit value is read from the offset address 0x0501, thereby obtaining the identification information of the EVREG8-EVREG 9.
Here, since the correspondence relationship between the event register 0 and the EVREG0 has been established, after determining that the identification information of the EVREG0 is 1, it may be determined that the event register corresponding to the EVREG0 is the event register 0. Then, an offset address 0x0480 of the EVENT register 0 is determined, and 8-bit values, i.e., identification information of the EVENT0-EVENT7, are read starting from the offset address 0x 0480.
Here, since the correspondence relationship between the port register 0 and the EVENT0 has been established, after determining that the identification information of the EVENT0 is 1, it may be determined that the port register corresponding to the EVENT0 is the port register 0. Then, offset address 0x0400 of port register 0 may be determined and 8-BIT values may be read starting from offset address 0x0400, the 8 values being the contents of port register 0, which may include the status information of port 0, e.g., BIT0-BIT2 of port register 0 being the status information of port 0.
In one example, after the processor reads the state information of the port from the port register corresponding to the event bit, the processor may further modify the identification information corresponding to the event bit to the second identification. Further, the processor may also determine an event register to which the event bit belongs, and if all event bits of the event register are the second identifier, may determine a synthetic bit corresponding to the event register according to a corresponding relationship between the event register and the synthetic bit, and modify identification information of the synthetic bit into a fourth identifier; if the event register has the event bit with the first identifier, the identifier information of the comprehensive bit corresponding to the event register is modified into a fourth identifier after all the event bits are the second identifier.
In the above embodiment, the processor reads the identification information of each synthesis bit from the synthesis register, which may include but is not limited to: in the first mode, the processor periodically reads the identification information of each synthesis bit from the synthesis register. Reading the identification information of each comprehensive bit from the comprehensive register when the processor receives an interrupt signal sent by the logic device; when the logic device learns that the state information of the port changes, the logic device can send an interrupt signal to the processor, so that the processor receives the interrupt signal.
In the conventional method, if there are 80 port registers, the processor needs to read each port register of the 80 port registers in turn, that is, read the port registers 80 times in total, and even if the status information of only one port changes, the processor needs to read 80 times. In the embodiment of the present application, if there are 80 port registers, 10 event registers, and 2 synthesis registers, the processor needs to sequentially read each synthesis register in the 2 synthesis registers, that is, read the synthesis registers for 2 times in total. In the 2 synthesis registers, 10 synthesis bits are included, and assuming that only the identification information of 1 synthesis bit EVREG0 is the third identification, and the identification information of the other 9 synthesis bits is the fourth identification, the processor only needs to read the event register 0 corresponding to the EVREG0, that is, read the event register 1 time in total. The EVENT register 0 includes 8 EVENT bits, and assuming that only 1 EVENT bit EVENT0 has the identification information of the first identifier and the other 7 EVENT bits have the identification information of the second identifier, the processor only needs to read the port register 0 corresponding to the EVENT0, that is, only 1 port register is read. Obviously, if only one port's state information changes, the processor only needs to read 4 times, significantly less than 80 times.
Based on the same concept as that in the above application, the embodiment of the present application further provides a network device, which is shown in fig. 4 and is a structural diagram of the network device, where the network device includes a processor 41 and a logic device 42;
the processor 41 is configured to read the identification information of each event bit from the event register of the logic device; the method comprises the steps that for each port register of a logic device, an event bit is configured for the port register in an event register, and a first corresponding relation between the port register and the event bit is established;
the processor 41 is further configured to, for each read event bit, if the identification information of the event bit is a first identification, read the state information of the port from the port register corresponding to the event bit according to the first corresponding relationship; the identification information of the event bit is a first identification or a second identification, the first identification is used for indicating that the state information of at least one port of the port register has changed, and the second identification is used for indicating that the state information of all ports of the port register has not changed.
When the processor 41 reads the identification information of each event bit from the event register of the logic device, the processor is specifically configured to: reading identification information of each synthesis bit from a synthesis register of the logic device; aiming at each event register of a logic device, configuring a comprehensive bit for the event register in a comprehensive register, and establishing a second corresponding relation between the event register and the comprehensive bit;
for each read comprehensive bit, if the identification information of the comprehensive bit is a third identification, reading the identification information of each event bit from the event register corresponding to the comprehensive bit according to a second corresponding relation; the identification information of the integrated bit is a third identification or a fourth identification, the third identification is used for indicating that the event register has changed, and the fourth identification is used for indicating that the event register has not changed.
The logic device 42 is used for periodically reading the state information of the port from the port register; if the read state information is different from the state information read from the port register last time, determining an event bit corresponding to the port register according to the first corresponding relation, and modifying the identification information corresponding to the event bit into a first identification; further, an event register to which the event bit belongs may be determined, a comprehensive bit corresponding to the event register may be determined according to the second correspondence, and identification information corresponding to the comprehensive bit may be modified into a third identification.
After the processor 41 reads the port status information from the port register corresponding to the event bit according to the first corresponding relationship, the processor is further configured to: modifying the identification information corresponding to the event bit into a second identification; and then, determining an event register to which the event bit belongs, if all event bits of the event register are the second identifier, determining a comprehensive bit corresponding to the event register according to the second correspondence, and modifying the identifier information of the comprehensive bit into a fourth identifier.
When the processor 41 reads the identification information of each event bit from the event register of the logic device, the processor is specifically configured to: periodically reading the identification information of each event bit from the event register; or reading the identification information of each event bit from the event register when receiving an interrupt signal sent by the logic device; the interrupt signal is sent by the logic device when the state information of the port is changed.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Furthermore, these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (10)

1. A status information acquisition method applied to a network device, the network device comprising a processor and a logic device, the method comprising:
the processor reads the identification information of each event bit from an event register of the logic device; the method comprises the steps that for each port register of a logic device, an event bit is configured for the port register in an event register, and a first corresponding relation between the port register and the event bit is established;
for each read event bit, if the identification information of the event bit is a first identification, the processor reads the state information of the port from the port register corresponding to the event bit according to the first corresponding relation; the identification information of the event bit is a first identification or a second identification, the first identification is used for indicating that the state information of at least one port of the port register has changed, and the second identification is used for indicating that the state information of all ports of the port register has not changed.
2. The method of claim 1, wherein the processor reading the identification information of each event bit from an event register of the logic device comprises:
the processor reads the identification information of each synthesis bit from the synthesis register of the logic device; aiming at each event register of a logic device, configuring a comprehensive bit for the event register in a comprehensive register, and establishing a second corresponding relation between the event register and the comprehensive bit;
for each read comprehensive bit, if the identification information of the comprehensive bit is a third identification, the processor reads the identification information of each event bit from the event register corresponding to the comprehensive bit according to the second corresponding relation; the identification information of the integrated bit is a third identification or a fourth identification, the third identification is used for indicating that the event register has changed, and the fourth identification is used for indicating that the event register has not changed.
3. The method of claim 2, further comprising:
the logic device periodically reads the state information of the port from the port register;
if the read state information is different from the state information read from the port register last time, the logic device determines an event bit corresponding to the port register according to the first corresponding relation, and modifies identification information corresponding to the event bit into a first identification;
and the logic device determines an event register to which the event bit belongs, determines a comprehensive bit corresponding to the event register according to the second corresponding relation, and modifies identification information corresponding to the comprehensive bit into a third identification.
4. The method of claim 2, wherein after the processor reads the port status information from the port register corresponding to the event bit according to the first mapping relationship, the method further comprises:
the processor modifies the identification information corresponding to the event bit into a second identification;
and the processor determines an event register to which the event bit belongs, if all event bits of the event register are the second identifier, determines a comprehensive bit corresponding to the event register according to the second corresponding relation, and modifies the identification information of the comprehensive bit into a fourth identifier.
5. The method of claim 1, wherein the processor reading the identification information of each event bit from an event register of the logic device comprises:
the processor periodically reads the identification information of each event bit from the event register; or,
reading the identification information of each event bit from an event register by the processor when receiving an interrupt signal sent by the logic device; wherein, the interrupt signal is sent by the logic device when the state information of the port is changed.
6. A network device comprising a processor and logic, wherein:
the processor is used for reading the identification information of each event bit from the event register of the logic device; the method comprises the steps that for each port register of a logic device, an event bit is configured for the port register in an event register, and a first corresponding relation between the port register and the event bit is established;
the processor is further configured to, for each read event bit, if identification information of the event bit is a first identification, read state information of a port from a port register corresponding to the event bit according to the first correspondence; the identification information of the event bit is a first identification or a second identification, the first identification is used for indicating that the state information of at least one port of the port register has changed, and the second identification is used for indicating that the state information of all ports of the port register has not changed.
7. The network device of claim 6,
when the processor reads the identification information of each event bit from the event register of the logic device, the processor is specifically configured to: reading identification information of each synthesis bit from a synthesis register of the logic device; aiming at each event register of a logic device, configuring a comprehensive bit for the event register in a comprehensive register, and establishing a second corresponding relation between the event register and the comprehensive bit;
for each read comprehensive bit, if the identification information of the comprehensive bit is a third identification, reading the identification information of each event bit from the event register corresponding to the comprehensive bit according to a second corresponding relation; the identification information of the integrated bit is a third identification or a fourth identification, the third identification is used for indicating that the event register has changed, and the fourth identification is used for indicating that the event register has not changed.
8. The network device of claim 7, wherein the logic device is configured to periodically read port status information from a port register; if the read state information is different from the state information read from the port register last time, determining an event bit corresponding to the port register according to the first corresponding relation, and modifying the identification information corresponding to the event bit into a first identification; and determining an event register to which the event bit belongs, determining a comprehensive bit corresponding to the event register according to the second corresponding relation, and modifying the identification information corresponding to the comprehensive bit into a third identification.
9. The network device of claim 7,
after the processor reads the state information of the port from the port register corresponding to the event bit according to the first corresponding relationship, the processor is further configured to: modifying the identification information corresponding to the event bit into a second identification; and determining an event register to which the event bit belongs, if all event bits of the event register are the second identifier, determining a comprehensive bit corresponding to the event register according to the second corresponding relation, and modifying the identification information of the comprehensive bit into a fourth identifier.
10. The network device of claim 6, wherein the processor, when reading the identification information of each event bit from the event register of the logic device, is specifically configured to: periodically reading the identification information of each event bit from the event register; or reading the identification information of each event bit from an event register when receiving an interrupt signal sent by the logic device; wherein, the interrupt signal is sent by the logic device when the state information of the port is changed.
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