Embodiment
In the prior art, in the master control borad logic, all distribute the register of a special use to be used to preserve the port status of business plate report in order to realize the RRPP function for each business board, thereby make the business board number of system and each business board the port number more for a long time, for the logical resource of realizing the master control borad that the RRPP function takies many more.At this problem, main thought of the present invention is: be provided with one and share register in master control borad, allow all business board dynamic sharings take this shared register.So just, need not in master control borad, all to distribute the register of a special use, thereby significantly reduced taking the master control borad logical resource for each business board.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing specific embodiment that develops simultaneously, the present invention is described in more detail.
Fig. 1 is the flow chart of a kind of port status report method of the embodiment of the invention.As shown in Figure 1, this method may further comprise the steps:
Step 101, each business board report the port status information of self to master control borad when self port status changes.
Step 102, described each business board of master control logic inquiry of described master control borad, for each current business plate that inquires, judge whether ports having state information report of this business board, be then to receive the described port status information that reports, and deposit the identification information of current business plate and the port status information that received in the master control borad shared register, report interruption to the CPU of master control borad.
In this step, because business board is connected by backboard with master control borad, promptly master control borad is inserted on the master control groove position on the backboard, and on each the professional groove position on each business board inserted backplane, so the identification information of business board can be the slot number of business board.
By port status report method shown in Figure 1, can when realizing the RRPP function, need not to take in a large number again the logical resource of master control borad.
Fig. 2 is the pictorial diagram of a kind of port status report method shown in Figure 1.Referring to Fig. 2, each business board reports master control borad with self port status in the mode of serial code stream by the RXD signal path in above-mentioned steps 101.The CPU of master control borad knows that in above-mentioned steps 102 the ports having state variation produces, this CPU reads business board identification information and port status information from sharing register then, and by master control logic to the service identification information corresponding service plate feedback response message that is read.Master control logic transmits by the TXD signal path to the response message of business board feedback.The with dashed lines arrow is represented the RXD signal path in Fig. 2, represents the TXD signal path with dash-dot arrows.
According to the technical scheme shown in Fig. 1 and Fig. 2, each business board dynamically takies the shared register in the master control borad.Therefore, next analyze in the embodiment of the invention and to realize that each business board dynamically takies some related when sharing register key technology:
1, require the business board of each groove position to take in embodiments of the present invention and share having equal opportunities of register, therefore, whether the business board that the master control logic of master control borad is inquired about each groove position with the mode of poll the ports having state information report.For example master control logic can be foundation with the slot number, the business board of each groove position of poll successively, thus guarantee that can not omit any one produced the interrupted service plate.
2, each business board is that timesharing dynamically takies shared register, when a business board generation interruption and when master control borad sends the port status signal of serial, may exist shared register also being taken by other business board, and master control logic also is not polled to the situation of this business board, at this moment, the serial port status signal of this business board transmission can not received by master control logic.Therefore, in embodiments of the present invention, in a single day business board interrupts, and just needs ceaselessly report to master control borad the port status of self, till master control borad returns response message.
3, master control borad returns response message by the TXD passage to this business board after correctly getting access to the port status information of a business plate report, to notify it to stop to send the port status information of this interruption.In an embodiment of the present invention, the TXD passage is set remains " high " state usually, master control borad is when the business board feedback response message, and the TXD passage is set to " low " state.Promptly, show the response message that receives master control borad when " TXD=0 " for business board.
4, business board is sent and stops several considerations of transmit port state information:
(1) under the situation that business plate port only took place once to interrupt, after interrupting generation, this business board transmit port state information is repeatedly given master control borad; Master control logic is polled to this business board, parses the port status information in the serial code stream, and with the slot number at this business board place be stored in share register after, report an interruption to master cpu; CPU responds interruption, reads and shares in the register after the content, by writing a special register in the master control logic, makes low pulse of TXD passage output of this business board; Stop the transmit port state information after the low pulse on this business board reception TXD passage.Here, in order to guarantee that business board can receive TXD and go up low pulse signal, the low pulse signal on the TXD need keep a period of time, and this point describes in detail in the back.
(2) because TXD is the low maintenance regular hour width that needs, and business board produces the situation of interruption once more during therefore needing to consider TXD=0, otherwise the interrupt status that business board produces during TXD=0 will be omitted.In the embodiments of the invention, a flag bit TxOverIntFlag1 is set writes down during the TXD=0 business board and whether produce once more and interrupt; If business board produced interruption during set flag bit TxoverIntFlag1 represented TXD=0, then business board also needs to send current port status information to master control borad after receiving the response message that master control borad returns.
(3) in a rack-mount unit, have only the port of the business board of a groove position to change and produce interruption, and produce under the situation of interrupting more than once, because having only the business board of a groove position to produce interrupts, CPU under normal circumstances can make response immediately after business board distributes a serial code stream, when master control borad during to business board feedback TXD=0, business board should send secondary serial code stream again.And receive at business board before the TXD=0 of master control borad feedback, the port of this business board may also can change once more and produce interruption, as shown in Figure 3 and Figure 4.
Fig. 3 is that embodiment of the invention business board receives the serial code stream schematic diagram that TXD=0 produces a kind of situation of interrupting before once more.As shown in Figure 3, be that example describes with the business of 48 ports, in the each 50 Bits Serial code streams that send of business board, 48 except that " 1 " of " 0 " of frame head and postamble is the port status significance bit.In Fig. 3, when business board sends 50 serial code stream for the first time and sends to 21 (among Fig. 3 with three cornet mark marks), the state that had sent the 5th bit port (in Fig. 3 with four directions sign mark) of state information changes once more; Business board begins to send 50 Bits Serial code streams of second frame immediately after sending 50 Bits Serial code streams of first frame, and when sending the 19th, receive the TXD=0 of master control borad feedback and stop transmission, the latest state information that then must lose above-mentioned the 5th port immediately.At problem shown in Figure 3, in embodiments of the present invention, during the transmission of the every end one frame serial port state information of business board, port status information that all will just send and current port status compare, if different, then after receiving TXD=0, also need to initiate once more once new port status process of transmitting.
Fig. 4 is that embodiment of the invention business board receives the serial code stream schematic diagram that TXD=0 produces another situation of interrupting before once more.As shown in Figure 4, business board begins to send second frame after sending the serial code stream of first frame, and when sending to the 19th of second frame (among Fig. 4 with three cornet mark marks), the state that had sent the 2nd port (in Fig. 4 with four directions sign mark) of state information changes once more; Business board receives the TXD=0 of master control borad feedback and stops immediately sending the latest state information that then must lose above-mentioned the 2nd port when sending to the 20th of second frame.At problem shown in Figure 4, in embodiments of the present invention, business board stops to send consecutive frame immediately behind the TXD=0 that receives the master control borad feedback, and the content of the former frame of a current frame that does not send and current port status compared, if it is identical then do not process, otherwise initiate port state information report process once more, up-to-date port status information is reported master control borad.
5, master control borad is begun to receive and stop to receive several considerations of the port status information of business plate report:
(1) produce to interrupt and report the situation of serial port state information for the business board that has only a groove position, be 0 then begin to receive serial information on this RXD of storage from its next bit in case master control logic detects the RXD corresponding with certain business board.This is because RXD remains height by default always, in case this moment RXD=0, then show the frame head of a frame serial code stream that is business plate report.
(2) business board for a plurality of grooves position all might produce the situation of interrupting and reporting the serial port state information, when master control logic is polled to a certain business board and detects its corresponding RXD=0, can not determine that just be the frame head of a frame information of this business plate report this moment.This is because master control logic is when receiving and handling the port status information of other business plate report, this business board just may produce interruption and begin to send serial code stream, and therefore detected RXD=0 might be the effective status information bit of certain port status of expression in the serial code stream when master control logic is polled to this business board.At this problem, in an embodiment of the present invention,, when being used on the RXD of this business board slot position, having consecutive frame to send the figure place of consecutive frame is counted for consecutive frame counter of RXD distribution of each professional board slot position.The default conditions of this consecutive frame counter are 0, and when on finding RXD the frame head of consecutive frame being arranged, since 1 counting, message count value of the last every transmission of RXD adds 1.When master control logic is polled to a groove position, on the one hand, can judge whether the business board of this groove position produced interruption (counting of consecutive frame counter is not 0, and then expression has interruption to produce) like this according to the consecutive frame counter of this groove position; On the other hand, can judge the whether frame head that sends on the current RXD according to the consecutive frame counter, if not frame head then keeps the authority of this groove position, on the RXD that finds this groove position, send be frame head the time, begin again to receive and the storage serial information.
(3) stop to receive for master control borad, master control logic interrupts to the CPU report after receiving a frame port status information of current business plate and being saved in shared register in embodiments of the present invention, then the business board of the next groove of poll position; And CPU has no progeny in having responded, and puts the TXD=0 of current groove position business board, and then the current business plate stops to send immediately, and whether a frame that no matter was sending at that time sends and finish.
6, to some analyses of the operation logic of master control borad CPU
Because what master control logic adopted the inquiry of each business board is polling mechanism, therefore share the business plate port state information of preserving in the register along with the business board that master control logic is polled to its next groove position can be refreshed.The time of sharing the port status information that keeps a business board in the register is sent the frequency decision of serial code stream by business board.With business board 48 ports are arranged, and its frequency that sends serial code stream is that 24KHz is an example, the time that a frame serial code stream of business board transmission is received in the master control borad sampling is: 48 * (1/24KHz) ≈ 2ms, the minimum of promptly sharing the port status information of a business board of register reservation may be 2ms the time.That is to say, interruption that the CPU of master control borad response master control logic reports and the response message of feedback TXD=0 must finish in 2ms-83.4us that (83.4us is the retention time of TXD=0 here, because TXD=0 is greater than a clock cycle of business board received signal at least, therefore get two 24k clock cycle, be approximately 83.4us).The speed of CPU access logic on the order of magnitude of several MHz, is example with 4MHz usually here, and CPU finishes 9 read-write operations approximately needs (1/4MHz) * 9=2.25us.9 above-mentioned read-write operations comprise: (sharing register is made up of 7 registers for the reading an of status poll (master control logic reports the mode bit of interruption to CPU), 7 registers, wherein the register of 6 8bit is used to deposit the state information of 48 ports, and the register of 1 4bit is used for the storage tank item) and the writing of 1 register (register to TXD puts 0).Therefore, require the CPU of master control borad in 2ms-83.4us, to finish interruption that the response master control logic reports and the response message of feedback TXD=0 is fully feasible.
7, about the analysis of the time width of TXD=0
The minimum time width of TXD=0 also is to be decided by the clock frequency that business board sent and received serial signal.Here the clock frequency that still sends and receive serial signal with business board is that 24kHz is an example, the time width of TXD=0 must guarantee to have at least a clock cycle 1/24KHz ≈ 41.7us of business board received signal, and the clock that just can guarantee the business board received signal can be adopted the value of TXD=0 and can not missed.Therefore the minimum time width of TXD=0 need be greater than the one-period of business board received signal clock.
In addition, because producing, RRPP interrupts reporting CPU by master control logic, its specific implementation is: master control logic need report when interrupting the interruption uploaded state position (interrupt register) with a special use to be written as preset value to CPU, here be 1 to be example with preset value, CPU just knows have interruption to report when inquiring when this interruption uploaded state position is 1, remove to read shared register then.Therefore the structure of reading is clearly made in interruption that must subtend CPU reports in master control logic, promptly will interrupt after the uploaded state position is written as 1 at master control logic, and also need be known at CPU and will interrupt uploaded state position 0 after this interruption reports.Remove to interrupt, the condition that is about to interrupt uploaded state position 0 is TXD=0, and removes and interrupt and will finish before master control logic next time the business plate port state of sample also will report new interruption.This has two kinds of situation: a, and 0 condition that the TXD of a groove position is put takes place when other groove position of sampling; B, 0 condition that the TXD of a groove position put takes place when adopting the sample slot position, and for example, the response in time of CPU of having no progeny in this groove position reports, and other groove position did not produce interruption just might this thing happens.Therefore can fall the new interruption masking that produces in a back groove position during for fear of the interruption that reports in clear previous groove position, just need to TXD put 0 maximum time width do a restriction.
Fig. 5 analyzes the schematic diagram that TXD puts maximum time of 0 width, and referring to Fig. 5, the business plate port state of a groove position of master control logic sampling needs 2ms, and the business board of groove position 1 and groove position 2 all needs to report interruption; Master control logic reports interruption (representing with solid arrow upwards) in business plate port state sampling the finishing back to groove position 1 to CPU in Fig. 5, then the business plate port state of groove position 2 is sampled; Under best situation, CPU master control logic report groove position 1 in have no progeny and can handle this interruption at once, and at the response message TXD=0 (among Fig. 5 with upwards dotted arrow represent) of feedback behind the 2.25us to groove position 1; And master control logic needs to report the interruption (representing with dash-dot arrows upwards) of groove position 2 equally behind the business plate port state with the intact groove position 2 of the time sampling of 2ms in Fig. 5.Analysis chart 5: master control logic need be removed between the interruption that reports groove position 2 to the interruption of the groove position 1 that CPU reports, and the condition of removing the interruption of groove position 1 is the response message TXD=0 to groove position 1, therefore the TXD of groove position 10 the time of putting the longlyest can equal 2ms-2.25us=1997.75us, the TXD of groove position 1 puts time of 0 greater than 2ms-2.25us=1997.75us else if, then may be before the interruption of CPU response groove position in meeting, the interrupt clear that groove position 2 is reported.The TXD that can draw each groove position from above-mentioned analysis puts 0 maximum time width: master control logic sampled a required time of business plate port state information deduct CPU response master control logic report interrupt to the required time of feedback response message.But, in the middle of reality, TXD put the smaller the better that 0 time width is provided with in its span for preventing that CPU from can not in time respond interruption.
According to above-mentioned next some Analysis of Key is provided specific implementation in the embodiment of the invention, and be divided into the realization of business board side and realization two parts of master control borad side are described.
One, the realization of business board side
In the present embodiment, each business board all has 48 ports and uses the 24kHz clock to send the serial protocol frame, and the form of serial protocol frame is: (port status significance bit)+1 (postamble), 0 (frame head)+48.In the present embodiment, it is to be provided with according to the port numbers that current every business board is supported at most that the port number of business board is made as 48, certainly the port number of business board can be expanded arbitrarily, as long as the figure place that master control borad receives is also adjusted thereupon, 48 ports of present embodiment just illustrate.
Mainly need finish following seven processes in each business board logic:
Process one: the clock that utilizes the work clock of CPLD to tell 24kHz is used as the tranmitting data register of serial protocol frame.For example, can adopt the clock of 33MHz as the CPLD clock.Clock division is accomplished to one skilled in the art easily, but it should be noted that business board divides the mode of 24kHz clock to be better than the mode unanimity that master control borad divides 196kHz most, to guarantee that the tranmitting data register on the business board is the integral multiple of receive clock on the master control borad.
Process two: distribute a register 1 to be used for all of the port state of record traffic plate.Here business board has 48 ports, and register 1 also needs 48.What register 1 was preserved is the current state of business plate port.
Process three: distribute a register 2 with register 1 identical figure place, 1 value of register is composed to register 2.What therefore register 2 was preserved is the Last status of the current state of business plate port.
Process four: judge according to the register 2 in register in the process two 1 and the process three whether the port status of business board has taken place to change and whether needs report port status to master control borad.Fig. 6 is the flow chart of the process four of embodiment of the invention business board side, as shown in Figure 6, may further comprise the steps:
Step 601 judges whether to be in reset mode, is execution in step 602 then, otherwise execution in step 603.
Step 602 is put port status change flag TxoverIntFlag1 initialize during 0 with interrupt status sign Int_los_l and TXD, and promptly Int_los_l puts 1, TxoverIntFlag1 puts 0, process ends.
In the present embodiment, Int_los_l puts 1 expression business plate port state no change, does not promptly have and interrupts producing, and opposite Int_los_l puts 0 expression has interruption to produce; TxoverIntFlag1 puts the port status no change that 0 expression TXD puts business board during 0, does not promptly have interruption and produces, and opposite TxoverIntFlag1 puts 1 and represents during TXD puts 0 the generation of interruption is arranged.
Step 603 judges that whether the content in register 1 and the register 2 equates, is execution in step 605 then, otherwise execution in step 604.
Step 604 has been judged new interruption and has been produced, and Int_los_l is put 0, and TxoverIntFlag1 is changed to TXD negate, process ends.
In this step, with TxoverIntFlag1 be changed to the TXD negate be because: if the content of register 1 is not equal to the content (produce interrupt) of register 2 occur in TXD=0 during, then TxoverIntFlag1 should be changed to 1, is the value negate of TXD; Occur in during the TXD=1 if the content of fruit register 1 is not equal to the content (produce and interrupt) of register 2, then TxoverIntFlag1 should be changed to 0, is still the value negate of TXD.
Step 605 judges whether TXD=0 and TxoverIntFlag=0, is execution in step 606 then, otherwise execution in step 607.
TxoverIntFlag in this step is the flag bit that whether needs to initiate once more new port status information process of transmitting after business board receives the response message of TXD=0 of master control borad feedback.TxoverIntFlag=TxoverIntFlag1 TxoverIntFlag2, symbol presentation logic " or ".Wherein, FxoverIntFlag2 be business board after master control borad transmit port state information, and the sign that whether port status changes before the response message of the TXD=0 that receives master control borad feedback.Before business board is receiving TXD=0, do not interrupt once more, TxoverIntFlag2=0 then, otherwise TxoverIntFlag2=1, for example as shown in Figure 3 and Figure 4 just TxoverIntFlag2 need be put 1 in both cases.The concrete condition of the value of TxoverIntFlag2 will explanation in follow-up process seven.
Step 606, the clear interruption, with Int_los_l put 1, TxoverIntFlag1 puts 0, process ends.
Because TXD=0 and TxoverIntFlag=0 show business board receives the response message of TXD=0 and do not interrupt once more, therefore need not to keep interruption in this step in this process.
Step 607 judges whether TXD=0 and TxoverIntFlag=1, is execution in step 608 then, otherwise execution in step 609.
Step 608 keeps interrupting, and Int_los_l puts 0, process ends.
In this step because TXD=0 and TxoverIntFlag=1 show that business board receives the response message of TXD=0, but business board during the TXD=0 produced new interruption and/or business board in the process of transmit port state information the port of send state information produced new variation again, therefore need to keep interrupting.
Step 609, Int_los_l keeps previous state constant, removes the TxoverIntFlag1 flag bit, and promptly TxoverIntFlag1 puts 0.
Because when TXD=0 and TxoverIntFlag=1, interruption is held, and the interruption that business board produces when having guaranteed TXD=0 is normally reported, therefore TXD=1 in this step, TxoverIntFlag1 must be by clear 0, so that note the interruption that business board produces during TXD=0.
Arrive this, the flow process of process four finishes.
Whether above-mentioned process two, three and four is used to jointly judge whether the port status of business board variation has taken place, and need to carry the serial protocol frame of port status information to the business board transmission.In the present embodiment, process two, three and four is used the clock of the clock of 33MHz as process.
Process five: distribute one 48 register RlosSerialReg, all of the port that is used for the record traffic plate is at the state that produces (during Int_los_l=0) when interrupting.Fig. 7 is the flow chart of the process five of embodiment of the invention business board side, as shown in Figure 7, may further comprise the steps:
Step 701 judges whether to be in reset mode, is execution in step 702 then, otherwise execution in step 703.
Step 702, register RlosSerialReg composes the initial condition of port, and promptly port all is in Link UP state, and RlosSerialReg composes 48 1 in the present embodiment, process ends.
Step 703 judges whether Int_los_l equals 0, is execution in step 704 then, otherwise execution in step 705.
Step 704, RlosSerialReg composes the current state of port.
Show that the generation of interruption is arranged because Int_los_l equals 0 in this step, therefore the current state of port is composed the register to RlosSerialReg, serial sends and uses fully.
Step 705, RlosSerialReg keeps preceding state constant.
RlosSerialReg not being returned 1 purpose in this step is when doing contrast with preceding state in process seven, not the situation that can occur judging by accident.
Process six: be a counter Cout_port, this counter Cout_port does bat with the 24KHz clock, discharges the back and equals 0 beginning at Int_los_l resetting, and remembers 49 from 0, and is endless.Control whether send the serial protocol frame that carries port status information with counter Cout_port in the present embodiment, Cout_port remains 0 and does not send out, and Cout_port begins counting then can send the serial protocol frame.Fig. 8 is the flow chart of the process six of embodiment of the invention business board side, as shown in Figure 8, may further comprise the steps:
Step 801 judges whether to be in reset mode, is execution in step 802 then, otherwise execution in step 803.
Step 802, counter Cout_port returns 0, so that correctly begin counting.
Step 803 judges whether that the rising edge of Int_los_l=0 and 24KHz clock arrives, and is execution in step 804 then, otherwise is left intact.
Step 804 judges whether the count value of counter Cout_port is 49, is execution in step 805 then, otherwise execution in step 806.
Step 805, counter Cout_port returns 0.
Step 806, the counting of counter Cout_port adds 1.
Process seven: this process mainly sends the serial protocol frame that carries port status information.Fig. 9 is the flow chart of the process seven of embodiment of the invention business board side, as shown in Figure 9, may further comprise the steps:
Step 901 judges whether to be in reset mode, is execution in step 902 then, otherwise execution in step 903.
Step 902, each parameter of initialization comprises: business board reports the signalling channel RXD of port status to put 1 to master control borad; TxoverFlag2 puts 0; The register RxdSerialEndReg1 that is used to write down the former frame content of current transmit frame composes 48 1; The register RxdSerialReg of a true content frame that sends composes 48 1 when being used to write down transmission serial protocol frame; Being used to write down TXD is fed the counter RxdTransEnd how many positions 0 o'clock present frame sent and composes 48.The counting maximum of counter RxdTransEnd is 49, when counting down to when adding 1 again after 49, since 0 counting.
Step 903 is bat with counter Cont_port, and each claps the content that sends among the RlosSerialReg on RXD, and in information of the every transmission of RXD, just content corresponding is recorded in the corresponding positions of RxdSerialReg, and RxdTransEnd adds 1.
Step 904 judges whether TXD equals 0, is execution in step 905 then, otherwise execution in step 910.
Step 905 judges whether to send the 49th, is execution in step 909 then, otherwise execution in step 906.
In the present embodiment, owing to can send the frame head of a bit before business board first bit in transmitter register RlosSerialReg, therefore, judging whether in this step sends the 49th, is the 48th that judges whether to send register RlosSerialReg.In addition, when the transmit port state information, have the time space of 1 bit between the frame head of the 49th of a frame and next frame, the value in this 1 bit time space on the RXD is " 1 ", " 1 " of this 1 bit is considered as the postamble of a frame.
In this step, judge whether not send the 49th according to the value of RxdTransEnd.
Step 906 judges whether RxdSerialEndReg1 equates with RlosSerialReg, is execution in step 907 then, otherwise execution in step 908.
Step 907 puts 0 with TxoverFlag2, process ends.
Step 908 puts 1 with TxoverFlag2, and expression is interrupted and should be continued to keep, and sends port status information at least again one time, process ends.
Step 909 is judged whether RxdSerialReg waits with RlosSerialReg to equate, is execution in step 907 then, otherwise execution in step 908.
Step 910 judges whether to send the 49th, is execution in step 911 then, otherwise execution in step 903.
Judging whether in this step sends the 49th, also for judging whether to send last position of register RlosSerialReg, promptly the 48th.
Step 911 composes the value of RxdSerialReg to RxdSerialEndReg1, execution in step 909.
The effect of this step is the former frame content of the current transmit frame of record.
Finished the flow process of process seven to this.
More than be to need seven processes finishing in the business board logic, wherein, process one, two, three, four and five is a benchmark with the 33MHz clock all, and process six and seven is a benchmark with the 24kHz clock.All processes are all clapped in each of self reference clock and are carried out once.
Two, the realization of master control borad side
In the present embodiment, master control borad uses the clock of 196kHz to receive the serial protocol frame that the business board side sends.
Mainly need finish following two kinds of processes in the master control borad logic:
Process one: take at the 196kHz clock, with one nine digit counter from 0 to 399, per 8 clap the beat of data that the corresponding 24kHz clock of adopting business board sends over, and the corresponding figure place of 50 the serial protocol frame that sends over one six digit counter record traffic plate, the 1st to 48 of each frame of essential record.In the present embodiment, the 0th of 50 Bits Serial protocol frames accounts for 12 of 196kHz clock and claps, and the 49th only accounts for 4 and clap, and all the other 1 to 48 all accounts for 8 and claps and the 4th sample when clapping at it.
In master control borad, do sampling clock with nine above-mentioned digit counters, judge the framing bit that sampled at that time with six above-mentioned digit counters and whether consistent send framing bit and then judge that when begin need be with under the data preservation that uses.
In the master control borad logic, a process one need all be set for the groove position of each business board, no matter whether processed with the content that the business board that guarantees each groove position sends over, whether all have register to monitor this groove position all the time has terminal to produce, and when interruption taking place and have the serial protocol frame to send, the real time record current data is which position of 50 Bits Serial protocol frames.
Figure 10 is the flow chart of the process one of embodiment of the invention master control borad side.As shown in figure 10, may further comprise the steps:
Step 1001 judges whether to be in reset mode, is execution in step 1002 then, otherwise execution in step 1003.
Step 1002, nine digit counters and six digit counters return 0, process ends.
Step 1003 judges whether nine digit counters are 0, is execution in step 1004 then, otherwise execution in step 1007.
Step 1004 judges whether the present bit on the RXD equals 0, is execution in step 1005 then, otherwise execution in step 1006.
Step 1005, the count value of nine digit counters adds 1, process ends.
Step 1006, nine digit counters return 0, process ends.
Step 1007 judges whether nine digit counters are 3, is execution in step 1004 then, otherwise execution in step 1008.
Judge in this step that whether nine digit counters are 3 is to be real frame head in order to ensure current RXD=0, rather than other interference.
Step 1008 judges whether the count value of nine digit counters equals 399, is execution in step 1009 then, otherwise execution in step 1010.
Step 1009, nine digit counters and six digit counters all return 0, process ends.
Step 1010 judges whether the present bit on the TXD equals 1, is execution in step 1011 then, otherwise execution in step 1009.
Step 1011, the count value of nine digit counters adds 1.
Step 1012 judges whether to arrive the sampling instant of nine digit counters record, is then execution in step 1014 otherwise execution in step 1013.
Step 1013, six digit counters remain unchanged, process ends.
Step 1014, the count value of six digit counters adds 1, process ends.
Arrive this, finished a flow process of process one.
Process two: in this process, according to slot number poll is done in each groove position, and in this process, finish the correct storage of the consecutive frame that the generation interrupted service plate that samples is reported, and after having stored a frame, report and interrupt giving CPU, and to finish the task of interrupting clearly in due course.
The register of mainly using in process two has five classes: the 48 bit register Samp_lpu_reg that receive the effective port state information in 50 the consecutive frame; Slot number register currentslotNum; Preceding two register values are composed the register to Samp_lpu_rego, and I haven't seen you for ages keeps 2ms for this register, can read its content so that have no progeny in the CPU response; Interrupt register Int_rpr_l; The framing bit register SerialSyncNum that is receiving, this register all need be distributed in each groove position.
Figure 11 is first's flow chart of the process two of embodiment of the invention master control borad side.As shown in figure 11, may further comprise the steps:
Step 1101 judges whether to be in reset mode, is execution in step 1102 then, otherwise execution in step 1103.
Step 1102, register Samp_lpu_reg, Samp_lpu_rego, Int_rpr_l compose 1, and other register composes 0, process ends.
Step 1103 judges whether to arrive the trailing edge of 196kHz clock, is execution in step 1105 then, otherwise execution in step 1104.
Step 1104 is left intact, process ends.
Step 1105 judges which groove position the numerical value among the slot number register currentslotNum indicates, and then this groove position is handled, and specifically sees second portion flow process shown in Figure 12.
Enter behind each groove position handling process as shown in figure 12.
Figure 12 is the second portion flow chart of the process two of embodiment of the invention master control borad side.As shown in figure 12, may further comprise the steps:
Step 1201, judge nine for counter whether on sampled point, and whether the value of SerialNum more than or equal to 1 and smaller or equal to 49, is execution in step 1202 then, otherwise execution in step 1209.
In this step, because in the present embodiment, nine digit counters are to clap from 0 to 399 in 196kHz, and clap the 0th that adopts 50 Bits Serial frames preceding 12, the 49th of sampling 50 Bits Serial frames clapped in back 4, and the 1st to 48 of sampling 50 Bits Serial frames clapped in 384 middle bats per 8, and all claps the 4th of per 8 rows and sample, therefore low three at nine digit counters all are 1 o'clock, can determine that promptly nine digit counters are on sampled point.
In this step, the value of parameter S erialNum is the count value of six digit counters.
Step 1202 judges whether the condition of interruption clearly, is then to interrupt clearly, otherwise keeps interrupting.
Step 1203, with the one digit number on the RXD according to being saved in the highest order of Samp_lpu_reg.
Step 1204 judges whether SerialSyncNum equals 49, be that then SerialSyncNum composes 1, otherwise the counting of SerialSyncNum adds 1.
In this step, in the time of in the middle of 50 Bits Serial protocol frames in current groove position send to, just this process two is polled under the situation of finding to interrupt producing in this groove position,, wait the SerialSyncNum that is provided with by the time the frame head of these groove position 50 Bits Serial protocol frames occurs in order to maintain current slot number.
Step 1205, judge whether the transmission framing bit is consistent with the reception framing bit, judge promptly in the present embodiment whether SerialSyncNum equals SerialNum-1, it is execution in step 1206 then, otherwise be left intact, the 196kHz clock of waiting for next time arrives sampled point, and the next bit data that receive again on the storage RXD get final product.
Step 1206 is with one of all data shift right of Samp_lpu_reg.
Step 1207 judges whether to receive the 48th of 50 Bits Serial frames, is execution in step 1208 then, otherwise is left intact that the 196kHz clock of waiting for next time arrives sampled point, and the next bit data that receive again on the storage RXD get final product.
In this step, when SerialSynNum=48, then determine to receive 50 Bits Serial frames the 48th.
Step 1208 composes the value of register Samp_lpu_reg and currentslotNum to register Samp_lpu_rego; Samp_lpu_reg returns 1 entirely; SerialSyncNum returns 0; Slot number increases progressively, and promptly currentslotNum adds 1, if the currency of currentslotNum is last slot number, then currentslotNum compose first groove position number; Report interruption to CPU, be about to interrupt register and be written as effective value.Process ends.
Step 1209 judges whether SerialNum equals 0 or 49, is execution in step 1211 then, otherwise execution in step 1210.
Step 1210 maintains slot number and is left intact, process ends.
Step 1211 judges whether current groove position has the serial protocol frame to send here, is execution in step 1212 then, otherwise execution in step 1213.
In this step, whether there is counting to judge whether that the serial protocol frame sends here according to nine digit counters.
Step 1212, SerialSyncNum composes 49, so that the follow-up slot number that retains on this basis.
Step 1213 judges whether SerialSyncNum equals 49, is execution in step 1214 then, otherwise execution in step 1215.
Step 1214 judges whether the TXD of current groove position equals 0, is execution in step 215 then, otherwise execution in step 217.
Step 1215, slot number adds 1, and promptly currentslotNum equals currency and adds 1, and SerialSynNum returns 0.
Step 1216 is judged the interruption that other groove position that whether CPU responds reports, and judges promptly whether the TXD of other groove position equals 0, is then to interrupt clearly, otherwise keeps interrupting, and counts this flow process.
Step 1217 maintains current slot number, process ends.
Arrive this, introduce the specific implementation of business board side and master control borad side in the embodiment of the invention that is over.
Based on the foregoing description, next introduce the structured flowchart of a kind of network equipment of the embodiment of the invention.
Figure 13 is the structured flowchart of a kind of network equipment of the embodiment of the invention.As shown in figure 13, this network equipment comprises: master control borad 1301 and plural business board 1302, described master control borad 1301 comprises: master control logic module 1303, share register 1304 and CPU 1305.
In Figure 13, each business board 1302 is used for when self port status changes reporting to master control borad 1301 self port status information.
Master control logic module 1303, be used for each business board of poll successively, for each current business plate that is polled to, judge whether ports having state information report of this business board, be then to receive the described port status information that reports, and the identification information of current business plate and the port status information that received deposited in share register 1304, report interruption to CPU 1305.
In the present embodiment, the identification information of business board is the slot number of business board.
CPU 1305, be used for having no progeny knowing that master control logic module 1303 reports, read business board slot number and port status information from sharing register 1304, by master control logic module 1303 to the business board slot number corresponding service plate feedback response message that is read.
In Figure 13, each business board 1302 is used for when self port status changes, and the port status information that repeats to report self to master control borad is till the described response message that receives master control borad CPU 1305 feedbacks.
In Figure 13, each business board 1302, be further used for judge behind the described response message that receives CPU 1305 feedback self port status receiving described response message before and/or whether in the described response message valid period (during being TXD=0) variation has taken place once more, be that the port status information of then initiating a new round reports process.
In Figure 13, each business board 1302, whenever, send a frame port status information to master control borad 1301 serials, one frame port status information of described firm transmission and current port status are compared, if equated first flag bit be set to invalid, if unequal then first flag bit is set to effectively; And when when also not having serial to send a complete frame port status information, just stopping to send owing to the described response message that receives CPU 1305 feedbacks, sending complete frame port status information and current port status with last one compares, if equated first flag bit be set to invalid, if unequal then first flag bit is set to effectively; Behind the described response message that receives CPU 1305 feedback, judge according to described first flag bit whether self port status changed once more before receiving described response message.
In Figure 13, master control borad 1301 can further include and each business board consecutive frame counter one to one, does not draw in Figure 13.At this moment: each business board 1302 is used for reporting to master control borad with the form of serial protocol frame self port status information.Each consecutive frame counter is used for having on the consecutive frame at pairing business board and gives the correct time, and the framing bit of each consecutive frame of being reported is all counted successively.Master control logic module 1303 is used for judging whether ports having state information report of current business plate according to the count status of the pairing consecutive frame counter of current business plate; And begin to receive the consecutive frame that the current business plate reports during to the frame head of consecutive frame in the consecutive frame rolling counters forward of current business plate, until receiving a complete consecutive frame.
In Figure 13, master control logic module 1303 is further used at CPU 1305 removing the described interruption that reports to CPU after the business board feedback response message.
In sum, each business board of this master control borad of the present invention reports the port status information of self to master control borad when self port status changes; The master control logic of master control borad is described each business board of poll successively, when the current business board ports having state information report that is polled to, deposit the identification information of current business plate and the port status information that received in the master control borad shared register, report the technical scheme of interruption to the CPU of master control borad, owing to make each business board timesharing dynamically take a shared register in the master control borad, and need in master control borad, not distribute the register of a special use for each business board, therefore saved the logical resource of master control borad greatly.
The above is specific embodiments of the invention only, is not to be used to limit protection scope of the present invention, all any modifications of being made within the spirit and principles in the present invention, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.