CN108512518A - A kind of low ESR small chips production method and system - Google Patents
A kind of low ESR small chips production method and system Download PDFInfo
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- CN108512518A CN108512518A CN201810262133.4A CN201810262133A CN108512518A CN 108512518 A CN108512518 A CN 108512518A CN 201810262133 A CN201810262133 A CN 201810262133A CN 108512518 A CN108512518 A CN 108512518A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000001681 protective effect Effects 0.000 claims abstract description 70
- 239000011159 matrix material Substances 0.000 claims abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000010453 quartz Substances 0.000 claims abstract description 26
- 238000005260 corrosion Methods 0.000 claims abstract description 19
- 230000007797 corrosion Effects 0.000 claims abstract description 19
- 239000007788 liquid Substances 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 16
- 230000003628 erosive effect Effects 0.000 claims description 13
- 238000000608 laser ablation Methods 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000009471 action Effects 0.000 claims description 2
- 229910001092 metal group alloy Inorganic materials 0.000 claims 1
- 238000011031 large-scale manufacturing process Methods 0.000 abstract description 5
- 238000010079 rubber tapping Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004576 sand Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010511 deprotection reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
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Abstract
The present invention provides a kind of low ESR small chips production methods; first one layer of metal protective film is respectively formed on the two sides of entire large-sized quartz wafer; then got on film trepanning in two surface protective films according to preset matrix layout with laser; the small wafer layout for forming the one-dimensional or two-dimensional matrix arrangement of definite shape and area, then carries out shallow corrosion with corrosive liquid from these tappings.Then laser striping, deep etch are carried out successively, generate several both ends or four sides are thinning and central part small chip outstanding, finally the residual metallic protective film on each small chip is removed, ultimately forms a large amount of ESR small chips.The production method is simple, is suitable for large-scale production, and can obtain the small chips of a large amount of more good low cost ESR.
Description
Technical field
The invention belongs to quartz wafer manufacture technology fields more particularly to a kind of low ESR small chips to make
Method and system.
Background technology
Quartz-crystal resonator due to its frequency accuracy and stability the characteristics of, using wide in hyundai electronics industry
It is general, such as communication, computer, amusement equipment.In general, the output frequency of quartz-crystal resonator and quartz used
The effective thickness of crystal wafer is inversely proportional, and frequency is higher, then the thickness of chip is thinner, and thickness and frequency have following relationship：T=
1.65/F, wherein t is thickness, and unit mm, F are frequency, unit MHz.
Due to the miniaturization of the product of each application field, to the volume requirement of quartz-crystal resonator and oscillator
It is smaller and smaller, and the quartz-crystal resonator and oscillator after minimizing also require the size of its quartz crystal chip used to get over
It is next smaller, and smaller and smaller equivalent series resistance (the Equivalent Series for making chip of the size of quartz wafer
Resistance, ESR) it is higher and higher, and the equivalent series resistance (ESR) that chip is higher and higher can reduce Quartz crystal resonant
The effective efficiency of device and oscillator.So how to reduce the equivalent series resistance (ESR) and large-scale low-cost of small chips
Ground manufactures the increasing trend that this kind of small chips are quartz-crystal resonator and oscillator industry.
In Quartz crystal resonant theory, a kind of implementation that related energy well theory is provided is to make small wafer center portion
Effective resonance face of position keeps the ineffective resonance face position on relatively thick and periphery to keep relatively thin, thus can will be in chip
The energy in effective resonance face of central part is maintained at central part and reduces energy and brought to the diffusion of peripheral part as possible
Energy loss meet customer demand to reduce the equivalent series resistance (ESR) of small chip.
Currently, common energy well theory implementation is to use roll processes.The technology is according to a certain percentage will
Small chips and sand mixing are put into an intermediate empty metal roller, make small chips and sand together by rolling metal cylinder
It rubs on the inner wall of metal roller.This method can largely realize the change of small chips peripheral shape in statistical significance
It is especially thinning, achieve the effect that " can fall into ".But during roll processes each small chip very difficult to control specific fortune
Dynamic state, thus the also shape of each small chip difficult to control.So the small chip produced using this kind of technical process, in reality
The control aspect for applying the design requirement of chip energy well theory is extremely difficult, causes the equivalent series resistance of this kind of small chip very high,
It is unable to fully meet the needs of customer in the application.
It can be seen from the above, the equivalent series electricity for the small chip that existing equivalent series resistance small chips production method makes
Resistance is high and cost is high, is unfavorable for mass producing.
Invention content
The technical problems to be solved by the invention are to provide low ESR small chips production method, it is intended to be solved
The equivalent series resistance height and cost height of the small chip that existing equivalent series resistance small chips production method makes,
The problem of being unfavorable for large-scale production.
In order to solve the above technical problems, the present invention provides a kind of low ESR small chips production method, it should
Method includes：
Layer protecting film is respectively sputtered on the two sides of a large-sized wafer, according to preset matrix layout, utilizes laser ablation
The protective film of corresponding matrix dot on the large-sized wafer；
Matrix dot (i.e. the not part of protective film) to having removed protective film on the large-sized wafer corrodes, with
It is set to be corroded thin；
Using on large-sized wafer described in laser ablation with removed protective film matrix dot it is (described there is no protective film position
Adjacent protective film) adjacent regions a part of protective film；
Matrix dot (i.e. first time laser striping position) to having removed protective film on the large-sized wafer corrodes,
It is set to be corroded through to form trepanning, so that the large-sized wafer to be resolved into several thin edges of matrix arrangement and central part also
There are the small chips of protective film；
Remove the remaining protective film in the small chips unless each using metal erosion technology, formed both ends or four sides it is thin and
The low ESR small chips of central thick.
In order to solve the above technical problems, the present invention provides a kind of low ESR small chips manufacturing system, it should
System includes：
Sputtering protection film device, for respectively sputtering layer protecting film on the two sides of a large-sized wafer；
Laser removes film device, for according to preset matrix layout, being corresponded to using on large-sized wafer described in laser ablation
Matrix dot protective film；
Quartz crystal corrosion device, for corroding to the matrix dot for having removed protective film on the large-sized wafer,
So that its be corroded it is thin；
Laser removes film device, is additionally operable to utilize on large-sized wafer described in laser ablation and removed the matrix dot of protective film
A part of protective film of adjacent regions；
Quartz crystal corrosion device is additionally operable to carry out the matrix dot for having removed protective film on the large-sized wafer rotten
Erosion, makes it be corroded through to form trepanning, the large-sized wafer to resolve into several thin edges of matrix arrangement and central portion
There is the small chips of protective film position；
Metal erosion device, for removing the remaining protective film in the small chips unless each using metal erosion technology,
It forms both ends or four sides is thin and the low ESR small chips of central thick.
Compared with prior art, the present invention advantageous effect is：
The present invention provides a kind of low ESR small chips production methods, first in entire large-sized quartz
The two sides of chip respectively forms one layer of metal protective film, is then got on film in two surface protective films according to preset matrix layout with laser
Trepanning forms the small wafer layout of the one-dimensional or two-dimensional matrix arrangement of definite shape and area, is then opened from these with corrosive liquid
Shallow corrosion is carried out at hole.Then laser striping, deep etch are carried out successively, generate several both ends or four sides are thinning and central part
Small chip outstanding finally removes the residual metallic protective film on each small chip, ultimately forms a large amount of ESR small chips.
The production method is simple, is suitable for large-scale production, and can obtain the small chips of a large amount of more good low cost ESR.
Description of the drawings
Fig. 1 is a kind of low ESR small chips production method flow that first embodiment of the invention provides
Figure；
Fig. 2 is that low ESR small chips provided in an embodiment of the present invention make schematic diagram；
Fig. 3 is a kind of low ESR small chips manufacturing system signal that second embodiment of the invention provides
Figure.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
As one embodiment of the present invention, as shown in Figure 1, a kind of low ESR provided by the invention is small-sized
Wafer fabrication method, this method include：
Step S101 (sputtering protective film)：One layer of metal protective film is respectively sputtered (such as Fig. 2 institutes on the two sides of a large-sized wafer
Show, 10 indicate the large-sized wafer, and 20 indicate protective film).Wherein, metal protective film can be by vacuum sputtering technique come real
It is existing, it is also possible to which that other technologies are realized.The material of the protective film is any metal or metal that can resist quartz crystal corrosive liquid
Alloy.The thickness of protective film can be set according to the concentration, temperature of corrosive liquid in below step and the length of etching time
It is fixed.After final sputtering is completed, the size of protective film is as the appearance and size of large-sized wafer.The shape ruler of large-sized wafer
Depending on the very little specifications design requirement by finally wanting small chip obtained.For example, the specification of small chip is rectangle 5mm*10mm, and this
One large-sized wafer is fabricated to 30 small chips by invention plan, then the specification of the large-sized wafer should be greater than (5mm* at this time
30) * (10mm*30), levels off to 150mm*300mm.
It should be noted that during following step S102-S106, it is either removed protective film (including laser
Deprotection film and metal erosion technology deprotect film) operation still corroded (including it is shallow corrode so that corrode thin and deep etch
So that corrosion forms trepanning) operation, it is both needed to all carry out the two sides of the large-sized wafer, and often in step both for two sides
Symmetrical position is operated.
Step S102 (first time laser striping)：It is brilliant using large scale described in laser ablation according to preset matrix layout
(matrix dot is position of opening to be formed to the corresponding matrix dot of on piece, and the shape of trepanning or area are by design requirement and small
The specification of chip determines, can be a point, can also be designed to any one shape, such as circle, polygon etc.) guarantor
Cuticula, to form the small chip of one-dimensional or two-dimensional matrix layout.The preset matrix layout is with specific shape or area
One-dimensional or two-dimensional matrix, wherein the specific shape or area (size) are set according to the specification of small chips.Into
When row matrix layout designs, position of opening is typically to design on four sides of each small chips, and the both ends of small chip or four sides
Depending on thinning degree is by design requirement.
Step S102 concrete operations are：With laser according to regular (i.e. preset matrix layout) the one of large-sized wafer 10
Metal protective film is removed on the designated position (i.e. matrix dot/position of opening, as indicated at 30 in figure 2) of face metal protective film 20, is revealed
Go out the quartz wafer material 30 (as shown in Fig. 2, position of opening 30 is shown as dotted in the present embodiment) of definite shape and area, shape
The small chips being laid out at one-dimensional or two-dimensional matrix.Large-sized wafer is afterwards turned over, phase is carried out in the corresponding position of other one side
With operation, what the arrangement of one-dimensional or two-dimensional matrix was all exposed on large-sized wafer two sides at this time has the numerous of certain area and shape
Position of opening, so as to follow-up position of opening be corroded wear after form trepanning.
Step S103 (shallow corrosion for the first time)：Using quartz crystal corrosion technology, to having been removed on the large-sized wafer
The matrix dot (i.e. the not part of protective film) of protective film is corroded so that its be corroded it is thin (be protected film protection portion
Position is unaffected, and the chip of the osseotomy site of unprotected film protection is thinning under the action of corrosion), to form matrix
The thin portion of chip (as shown in 30A in Fig. 2) of arrangement, so that central part has protrusion.
Step S104 (second of laser striping)：Large-sized wafer Jing Guo shallow corrosion is cleaned up, is gone using laser
Except adjacent with the matrix dot (the adjacent protective film without protective film position) that has removed protective film on the large-sized wafer
A part of protective film (as shown in 40 in Fig. 2) at position.The position 40 of second of laser striping is typically and first time striping
Position 30 is adjacent.Large-sized wafer is afterwards turned over, protective film is removed in the symmetric position of other one side.
Step S105 (second of deep etch)：Using quartz crystal corrosion technology, to having been removed on the large-sized wafer
The matrix dot (i.e. first time laser striping position) of protective film is corroded, it is made to be corroded through to form trepanning, so as to will be described big
Wafer size resolves into several thin edges of matrix arrangement and central part also has the small chips of protective film.As shown in Fig. 2, straight
It is corroded through completely to trepanning 30, forms the small chips individual 50 of numerous separation, at this time the both ends of each small chips or four
Side is thin and central part has protrusion.
Step S106：The remaining protective film in the small chips unless each, shape after cleaning are gone using metal erosion technology
Thin and central thick the low ESR quartz crystal small chips 60 at both ends or four sides.
Above-mentioned steps make entire large-sized wafer be broken down by the process of segmentation laser striping and stopping-out chip
Many small chips, and each small chip is that central part is thick and both ends or four sides are thin, reached the shape required by energy well theory,
Energy " trap " is formed on small chip, is prevented the energy at wafer center position to the diffusion of wafer perimeter, is reduced energy
Loss, to reduce the equivalent series resistance (ESR) of chip.Small chip is corroded thin degree by design requirement and small-sized
The specification of chip determines that the factor usually considered also has the concentration, temperature and etching time of corrosive liquid.
In conclusion the production method that first embodiment of the invention is provided is simple, it is suitable for large-scale production, and can
To obtain the small chips of a large amount of more good low cost ESR.
As second embodiment of the present invention, as shown in figure 3, providing a kind of low ESR small chips system
Make system, which includes：
Sputtering protection film device 101, for respectively sputtering layer protecting film on the two sides of a large-sized wafer.
Laser removes film device 102, for according to preset matrix layout, using right on large-sized wafer described in laser ablation
The protective film for the matrix dot answered.
Quartz crystal corrosion device 103, it is rotten for being carried out to the matrix dot for having removed protective film on the large-sized wafer
Erosion so that its be corroded it is thin.There is the large scale for exposing certain area and the numerous trepannings of shape quartz crystal materials brilliant on two sides
Piece is put into quartz crystal etching tank internal corrosion, the thin portion of chip of matrix arrangement is formed, so as to the central part of each small chips
There is protrusion.
Laser removes film device 102, is additionally operable to utilize on large-sized wafer described in laser ablation and removed the square of protective film
A part of protective film of lattice point adjacent regions.
Quartz crystal corrosion device 103 is additionally operable to carry out the matrix dot for having removed protective film on the large-sized wafer
Corrosion, makes it be corroded through to form trepanning, central so that the large-sized wafer to be resolved into several thin edges of matrix arrangement
There is the small chips of protective film at position.Two sides is had and exposes the big of certain area and the numerous trepannings of shape quartz crystal materials
Wafer size is put into quartz crystal etching tank internal corrosion, until the osseotomy site of first time is corroded through completely, second of trepanning
Position be corroded it is thin, formed numerous separation small chips individual.
Metal erosion device 104, for going the remaining protection in the small chips unless each using metal erosion technology
Film, forms both ends or four sides are thin and the low ESR small chips of central thick.The small-sized of metal protective film will be there remains
Chip is put into metal erosion liquid, all erodes remaining metal protective film, it is thin to form available both ends or four sides after cleaning
And low ESR (ESR) small chips of central thick.
In conclusion the system that second embodiment of the invention is provided, the method provided using one embodiment,
Manufacturing system is simple, is suitable for large-scale production, and can obtain the small chips of a large amount of more good low cost ESR.
The foregoing is merely illustrative of the preferred embodiments of the present invention, all in spirit of the invention not to limit invention
With within principle made by all any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of low ESR small chips production method, which is characterized in that the method includes：
Layer protecting film is respectively sputtered on the two sides of a large-sized wafer, according to preset matrix layout, described in laser ablation
The protective film of corresponding matrix dot on large-sized wafer；
Matrix dot to having removed protective film on the large-sized wafer corrodes so that its be corroded it is thin；
Utilize a part of protective film with the matrix dot adjacent regions for having removed protective film on large-sized wafer described in laser ablation；
Matrix dot to having removed protective film on the large-sized wafer corrodes, it is made to be corroded through to form trepanning, to incite somebody to action
The large-sized wafer resolves into several thin edges of matrix arrangement and central part also has the small chips of protective film；
The remaining protective film in the small chips unless each is removed using metal erosion technology, both ends is formed or four sides is thin and central
Thick low ESR small chips.
2. the method as described in claim 1, which is characterized in that the preset matrix layout is with specific shape or area
One-dimensional or two-dimensional matrix；Wherein, the specific shape or area are set according to the specification of small chips.
3. the method as described in claim 1, which is characterized in that described in the respectively one layer of protection of sputtering of the two sides of a large-sized wafer
Film includes：Using vacuum metal sputtering technology, layer protecting film is respectively sputtered on the two sides of a large-sized wafer.
4. the method as described in claim 1, which is characterized in that the material of the protective film is that can resist quartz crystal corrosive liquid
Any metal or metal alloy.
5. the method as described in claim 1, which is characterized in that the square to having removed protective film on the large-sized wafer
Lattice point is corroded so that its be corroded it is thin, by using quartz crystal corrosion technology realize.
6. the method as described in claim 1, which is characterized in that the square to having removed protective film on the large-sized wafer
Lattice point is corroded, it is made to be corroded through to form trepanning, is realized by using quartz crystal corrosion technology.
7. the method as described in claim 1, which is characterized in that the two sides of the large-sized wafer is both needed to be removed protective film
And etching operation, and the positional symmetry of two sides removal protective film and etching operation.
8. a kind of low ESR small chips manufacturing system, which is characterized in that the system comprises：
Sputtering protection film device, for respectively sputtering layer protecting film on the two sides of a large-sized wafer；
Laser removes film device, for according to preset matrix layout, utilizing corresponding square on large-sized wafer described in laser ablation
The protective film of lattice point；
Quartz crystal corrosion device, for corroding to the matrix dot for having removed protective film on the large-sized wafer, so that
It is corroded thin；
Laser removes film device, is additionally operable to using adjacent with the matrix dot for having removed protective film on large-sized wafer described in laser ablation
A part of protective film at position；
Quartz crystal corrosion device is additionally operable to corrode the matrix dot for having removed protective film on the large-sized wafer, make
It is corroded through to form trepanning, the large-sized wafer to be resolved into several thin edges of matrix arrangement and central part also has
The small chips of protective film；
Metal erosion device is formed for being removed the remaining protective film in the small chips unless each using metal erosion technology
Both ends or four sides are thin and the low ESR small chips of central thick.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113690129A (en) * | 2021-09-14 | 2021-11-23 | 江苏天企奥科技有限公司 | Preparation method of quartz wafer for high-precision piezoelectric sensor |
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Effective date of registration: 20200928 Address after: 518000 south side of innovation Avenue and east side of Bianxi River, EBU Town, Shenzhen Special Cooperation Zone, Shenzhen City, Guangdong Province Applicant after: Shenzhen Shenshan special cooperation zone Yingdali Electronic Technology Co.,Ltd. Address before: 518103, building 3-4, building C, 4 / F, Tai Po Industrial Park, Fenghuang second industrial zone, Fenghuang Industrial Zone, Baoan District, Shenzhen, Guangdong, Fuyong, China Applicant before: INTERQUIP ELECTRONICS (SHENZHEN) Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180907 |