CN108509480A

CN108509480A - It is configured to execute the data storage device of non-obstructive root canal update operation

Info

Publication number: CN108509480A
Application number: CN201711402794.4A
Authority: CN
Inventors: K.因巴尔; M.伊欧宁; E.泽乌伦; E.列夫
Original assignee: Western Digital Technologies Inc
Current assignee: Western Digital Technologies Inc
Priority date: 2017-02-23
Filing date: 2017-12-22
Publication date: 2018-09-07
Anticipated expiration: 2037-12-22
Also published as: KR102042904B1; DE102017128952A1; CN108509480B; DE102017128952B4; US20180239547A1; US10359955B2; KR20180097441A

Abstract

A kind of device includes nonvolatile memory and is coupled to the controller of nonvolatile memory.Controller includes volatile memory, is configured as storing the first authentic copy of control table associated with nonvolatile memory.The controller is configured as：The first update of the part of the first authentic copy of control table is executed in response to the first request, and the second update of the triplicate for initiating control table at nonvolatile memory is updated based on first and is concurrently run with the second update and is asked access nonvolatile memory second.The controller is configured as asynchronously executing non-obstructive root canal simultaneously operating and non-obstruction union operation, wherein non-obstruction union operation is atomic operation, which includes the address translation table for update step concurrently being evacuated and being compressed to the cache in volatile memory.

Description

It is configured to execute the data storage device of non-obstructive root canal update operation

Cross reference to related applications

This application claims 2 months 2017 U.S. Patent Application No.s submitted for 23rd be 15/440,505 equity and be it Continuation-in-part application, entire contents are incorporated herein by reference.

Technical field

The present disclosure relates generally to electronic equipments, and relate more specifically to data storage device.

Background technology

Data storage device allows users to store and retrieve data.The example of data storage device includes volatile storage Equipment and non-volatile memory device.Non-volatile memory device retention data after power cut-off incident, and volatile storage is set It is standby that data are lost after power cut-off incident.

Data storage device can store control information associated with data.For example, data storage device can be safeguarded Management table of the instruction logical address to the mapping of physical address.In some embodiments, management table is maintained at data storage In the volatile memory of the controller of equipment.Data storage device can at volatile memory more new management table, and Can management table be periodically sent to the nonvolatile memory of data storage device (for example, in nonvolatile memory Place comes " backup " using control update operation and manages table).

Data storage device can control update operation during the write operation of " obstruction " to nonvolatile memory, with Create the consistency between control table and host data.For example, data storage device can be waited for until completing one or more A write operation (for example, during system idle time) is with more newly control information.During more newly control information, data storage Equipment " can block " the subsequent request of (for example, delay) to the write-access of nonvolatile memory, until completing to control The update of information.The write operation of " obstruction " one or more may cause the stand-by period at data storage device.

Invention content

According to an aspect of the present invention, a kind of device includes：Nonvolatile memory；And controller, it is coupled to this Nonvolatile memory, controller include volatile memory, and wherein controller is configured as executing the non-obstructive root canal of separation Simultaneously operating and non-obstruction union operation.

According to another aspect of the present invention, a kind of device includes：Nonvolatile memory；And controller, it is coupled to this Nonvolatile memory, controller include：Interface is configured as receiving to accessing the nonvolatile memory from access equipment First request；And volatile memory, it is configured as the first of storage control structure associated with the nonvolatile memory Copy, wherein controller are additionally configured to：First of the part to the first authentic copy of control structure is executed in response to the first request Update, initiated at the nonvolatile memory based on the first update the second update to the triplicate of control structure and with Second update concurrently runs the second request to accessing the nonvolatile memory.

According to another aspect of the present invention, a kind of method includes：By the first equipment from the second equipment receive first request with Execute the first write operation to the nonvolatile memory of the first equipment；In response to executing the first write operation, execute to depositing Store up the first update of the part of the first authentic copy of the control table at the volatile memory of the first equipment；In non-volatile memories The second update to the triplicate of control table is executed at device so that triplicate will be traveled to the modification of the first authentic copy；With holding The second reproducting periods of row executes the second write operation to nonvolatile memory.

According to another aspect of the present invention, a kind of device includes：Device for storing data；For being connect from access equipment Receive the device of the first request to accessing device for storing data；It is associated with device for storing data for storing Control table the first authentic copy part device；With for executing the portion to the first authentic copy of control table in response to the first request Point the first update, for the to the triplicate of control table to be initiated at device for storing data based on the first update Two update and for being performed in parallel the second device asked to accessing device for storing data with the second update.

According to another aspect of the present invention, a kind of device includes：Nonvolatile memory；And controller, it is coupled to The nonvolatile memory, controller include volatile memory, and wherein controller is configured as executing non-obstructive root canal synchronization Operation, and wherein controller is additionally configured to asynchronously execute non-obstruction merging behaviour relative to non-obstructive root canal simultaneously operating Make.

Description of the drawings

Fig. 1 be include the first explanation for being configured as executing the system of the data storage device of non-obstructive root canal simultaneously operating The exemplary figure of property；

Fig. 2 depicts the illustrated examples for the programming process that can be executed at the data storage device of Fig. 1；

Fig. 3 depicts another illustrated examples for the programming process that can be executed at the data storage device of Fig. 1；

Fig. 4 be include the second explanation for being configured as executing the system of the data storage device of non-obstructive root canal simultaneously operating The exemplary figure of property；

Fig. 5 depicts the one group of operation that can be executed by the data storage device of Fig. 4；

Fig. 6 is the figure of exemplary certain illustrative aspects of the data storage device of depiction 4；

Fig. 7 is the figure for the equipment that can be included in the data storage device of Fig. 4；

Fig. 8 is the figure of the illustrative aspect of the equipment of Fig. 7；

Fig. 9 is the figure in terms of the exemplary additional information of the data storage device of depiction 4；

Figure 10 is the figure for the certain operations for showing to be executed by the data storage device of Fig. 4；

Figure 11 is the exemplary flow chart of certain illustrative of the method for the operation of the data storage device of Fig. 1；

Figure 12 is the exemplary flow chart of certain illustrative of the method for the operation of the data storage device of Fig. 4；

Figure 13 is the illustrated examples for the system for including the data storage device for being configured as executing non-obstruction union operation Figure；

Figure 14 is the certain exemplary block diagrams for the operation for showing to execute at the data storage device of Figure 13；

Figure 15 is the certain exemplary ladder diagrams for the operation for showing to execute at the data storage device of Figure 13；

Figure 16 is the certain exemplary figures for the operation for showing to execute at the data storage device of Figure 13.13；

Figure 17 is the exemplary flow chart of certain illustrative of the method for the operation of the data storage device of Figure 13.

Specific implementation mode

It is configured as executing non-obstruction union operation according to the data storage device of some aspects of the disclosure, the non-obstruction Union operation propagates the change of the first authentic copy to being stored in the control information in volatile memory (for example, fusion or conjunction And) to the triplicate for the control information being stored at nonvolatile memory.For example, instead of the merging in more newly control information " obstruction " operation during operation, data storage device can be performed in parallel operation, such as by being performed in parallel write-in behaviour Work and union operation.

In some cases, after executing write operation and via control simultaneously operating more newly control information it Before, it may occur however that abnormal shutdown (ungraceful shutdown, UGSD) event.For example, power failure may cause UGSD events.In this case, data storage device can execute memory scans to identify the result (example of write operation Such as, due to the triplicate of control information be not updated to reflect also write operation as a result, and controlling the first secondary of information This may lose during UGSD events from volatile memory).For example, data storage device can use be stored in it is non-easily The metadata (for example, header information (header information)) of data at the property lost memory identifies write operation As a result, such as by identifying the address changed since previous control simultaneously operating.Data storage device can be based on result Carry out more newly control information.Therefore, union operation can be executed with non-blocking fashion, without causing data due to UGSD events The risk of loss.

In the description, common or similar feature can be specified by common reference label.As used herein , " exemplary " can indicate example, embodiment and/or aspect, and should not be construed as limited to or indicate preference Or preferred embodiment.

With reference to figure 1, depicts the certain illustrative example of system and be generally designated as 100.System 100 includes Data storage device 102 and equipment 180 (for example, host equipment or access device).Data storage device 102 includes non-volatile Memory 104 and controller 130.Controller 130 is coupled to nonvolatile memory 104.

Nonvolatile memory 104 includes being included in one or more memory naked core (such as first memory naked cores 106 and second memory naked core 108) in non-volatile storage element array.In order to further illustrate showing as illustrative Example, nonvolatile memory 104 may include that flash memory (for example, NAND quick-flash memory) or resistance-type memory are (all Such as resistive random access memory (resistive random access memory, ReRAM)).Nonvolatile memory 104 can have three-dimensional (three-dimensional, 3D) memory to configure.As it is used herein, 3D memory devices can With multiple physical layer levels including memory element (rather than with the single one physical such as the memory element in flat memory equipment Level).As an example, nonvolatile memory 104 can have 3D vertical bit lines (vertical bit line, VBL) to match It sets.In certain embodiments, nonvolatile memory 104 has 3D memory array configurations, is monolithically formed and is storing In one or more physical layer levels of device cell array, which has the active area being arranged on silicon substrate Domain.Alternatively, nonvolatile memory 104 can have another configuration, such as two-dimentional (two-dimensional, 2D) to deposit Reservoir configures or non-monolithic 3D memories configuration (for example, stacking the configuration of naked core 3D memories).

Nonvolatile memory 104 includes one or more regions of memory element.The example of storage region is block (block), the nand flash memory erasing group of such as memory element or one group of storage member based on resistance in ReRAM embodiments Part.Another example of storage region is the wordline of memory element (for example, the wordline of NAND Flash memory element or based on resistance The wordline of memory element).As illustrated examples, storage region can have single stage unit (single-level-cell, SLC) configuration, multi-level unit (multi-level-cell, MLC) configuration or three-level unit (tri-level-cell, TLC) are matched It sets.Each memory element of nonvolatile memory 104 can be programmed to indicate the state of one or more values (for example, dodging Deposit the threshold voltage in configuration or the resistance states in resistance-type memory configuration).As an example, in illustrative TLC schemes In, memory element can be programmed to the state of three values of instruction.As additional example, in illustrative MLC schemes, storage member Part can be programmed to the state of two values of instruction.

Controller 130 includes the memory interface 132 to nonvolatile memory 104, and further includes to equipment 180 Equipment interface 172 (for example, host interface).Controller 130 can also include flash translation layer (FTL) (flash translation Layer, FTL) 138, control circuit 140, data queue 142, volatile memory 144 and upper photodetector 146.As saying Bright property example, volatile memory 144 may include random access memory (random access memory, RAM).

During operation, controller 130 can receive data 174 from equipment 180, such as in conjunction with to nonvolatile memory The request of 104 write-access.Controller 130 can execute one or more operations to generate the first data based on data 174 120, such as the first data 120 are generated by being encoded to data 174.In some embodiments (for example, flash memory is real Apply mode), the FTL138 of controller 130 is configured as executing logic to physical address translations with will be associated with data 174 Logical address is converted into physical address associated with the first data 120.Controller 130 can be configured as in data queue (for example, buffering area or " queue ") data 174 are stored at 142.

Memory interface 132 is configured as the first data 120 being sent to nonvolatile memory 104.For example, controller 130 can retrieve the first data 120 from data queue 142 and can the first data 120 be supplied to memory interface 132 Data 120 are sent to nonvolatile memory 104.Nonvolatile memory 104 can store the first data 120 to non- The specific region of volatile memory 104 by the first data 120 (for example, by being written to first memory naked core 106, write-in To second memory naked core 108, be written to one or more of the other memory naked core, or combinations thereof).

Volatile memory 144 is configured as storage control information 184.In order to illustrate control information 184 may include reflecting Firing table 186, and controller 130 can carry out more new mappings in response to storing the first data 120 to nonvolatile memory 104 Table 186 such as indicates that nonvolatile memory 104 stores the first data 120 by updating mapping table 186.For example, control electricity Road 140 be configured as based on by the first data 120 storage to nonvolatile memory 104 come more newly control information 184 with generate Newer control information 124 (for example, newer mapping table corresponding with the newer version of mapping table 186).

Control circuit 140 can be configured as generation instruction 126 and be configured as to indicate that 126 include in newer control In information 124 processed.Instruction 126 can specify it is being stored by nonvolatile memory 104, " safely " be written to it is non-easily The data of the property lost memory 104.For example, instruction 126 can specify the first data 120 (and to be written before the first data 120 Other data of nonvolatile memory 104) correspond to " safe " (or reliable) data.Instruction 126 can use and the One data, 120 associated logical address, physical address associated with the first data 120, other information or combinations thereof refer to Fixed first data 120.Alternatively or additionally, instruction 126 can specify " point of safes " of such as timestamp (timestamp) (or " synchronous point "), wherein the data that nonvolatile memory 104 is written before point of safes correspond to secure data, and its In after point of safes be written nonvolatile memory 104 data correspond to easily damaged data.

Newer control information 124 can be sent to nonvolatile memory 104 (for example, " backup " is more by controller 130 The copy of new control information 124), enable to retrieve newer control information 124 (for example, so that can be in data Restore newer control information 124 after the power cycle of storage device 102).(control is synchronized in conjunction with non-obstructive root canal Sync, CS) operation (also referred herein as control update operation or control procedure operation), newer control information 124 can To be sent to nonvolatile memory 104.

According to all aspects of this disclosure, controller 130 is configured as newer control information 124 and other data parallels Ground is sent to nonvolatile memory 104 so that newer control information 124 and other data are stored in nonvolatile memory (" obstruction " other access to nonvolatile memory 104 and is executed by nonvolatile memory 104 for example, not at 104 Processing).In illustrated examples, memory interface 132 is configured as concurrently sending the second data 122 and newer control letter Second data 122 and newer control information 124 to be stored at nonvolatile memory 104 by breath 124.Data queue 142 The second data 122 of storage be can be configured as so that the second data 122 are written to nonvolatile memory 104.In particular example In, controller 130 can be configured as and access the second data 122 from data queue 142, and be visited from volatile memory 144 It asks newer control information 124, and concurrently provides the second data 122 and newer control information to memory interface 132 124.In illustrated examples, memory interface 132 is configured as the second data 122 are concurrently sent to first memory naked One in core 106 and second memory naked core 108 and newer control information 124 is sent to first memory naked core 106 and second memory naked core 108 in another.

It can refer to using extremely as it is used herein, " concurrently " sends the second data 122 and newer control information 124 A few common clock period, at least one public packet or another common technology send the second data 122 and newer Control information 124.In order to illustrate if sending the second data 122 during the common clock period or using public packet At least part of at least part and newer control information 124, then can concurrently send the second data 122 and newer Control information 124.In some cases, memory interface 132 may include the multichannel for being coupled to nonvolatile memory 104 Bus, and the second data 122 and newer control information 124 can be sent to using multichannel bus parallel it is non-volatile Property memory 104.

Nonvolatile memory 104 is configured as storing the second data 122 and newer control information with non-blocking fashion 124.For example, nonvolatile memory 104 can execute non-obstruction CS operations, which operates newer control information 124 are written to write-in of the nonvolatile memory 104 without " obstruction " to the second data 122.

The data that nonvolatile memory 104 is written to after newer control information 124 is written can correspond to Easily damaged data.In order to illustrate memory interface 132 can be configured as will after sending newer control information 124 Third data 123 are sent to nonvolatile memory 104.Instruction 126 can specify third data 123 to correspond to easily damaged number According to.For example, if during or after newer control information 124 is written to nonvolatile memory 104 and based on To power cut-off incident occurs before the write-ins of third data 123 again more newly control information 184, then controller 130 may not be able to be true Determine whether third data 123 have been successfully programmed (for example, causing " to lose " data).Therefore, third data 123 can correspond to " easily damaged " data.

Depending on specific embodiment, non-volatile deposit concurrently is written to newer control information 124 is written The data of reservoir 104 can correspond to " safe " data or " easily damaged " data.In illustrated examples, control circuit 140 are configured as the second data 122 in accessing data queue 142 during generating newer control information 124.In this example In, control circuit 140, which can be configured as, makes instruction 126 that the second data 122 be specified to correspond to secure data (because of the second data 122 will concurrently be programmed with newer control information 124).In other embodiments, the second data 122 can correspond to Easily damaged data.

Detection is can be configured as by the second data 122 and newer control in order to further illustrate, upper photodetector 146 Information 124 processed be written to occur after nonvolatile memory 104 power on event at data storage device 102.Control Device 130 can be configured as to be executed in response to powering on event using newer control information 124 (for example, using instruction 126) Scan operation is to identify third data 123.

In the particular example of implicit technology, it is easily damaged that instruction 126, which can implicitly specify third data 123,.Example Such as, instruction 126 can indicate that non-volatile memories are arrived in the storage of first data 120 before generating newer control information 124 Device 104, and the data stored after the first data 120 are easily damaged.Controller 130 can be from nonvolatile memory 104 read the first data 120 to determine that specific time associated with the first data 120 stabs, and can scan non-volatile Memory 104 finds the data of timestamp of the instruction after specific time associated with the first data 120 stamp (for example, the Three data 123).

Depending on specific embodiment, data storage device 102 can be in response to the easy of detection such as the second data 122 Impaired data execute one or more operations.As illustrated examples, data storage device 102 can notify equipment 180 Second data 122 are easily damaged due to the power cut-off incident at data storage device 102.

Operation at data storage device 102 can continue one or more storage operations.For example, data storage device 102 can execute write operation so that the 4th data are written to nonvolatile memory 104.Data storage device 102 can be more Newly control information 184 generates the third version of control information 184, and data storage device with the 4th data based on programming 102 can concurrently send the third version of control information 184 and the 5th data will control the third version and the of information 184 Five data are stored in nonvolatile memory 104.The third version of control information 184 can specify the 4th data the (or the 4th Data and the 5th data) correspond to secure data.

The performance at data storage device 102 can be improved with reference to the one or more aspects that figure 1 describes.For example, data Storage device 102 can execute CS operations during non-obstruction CS is operated, non-volatile without " obstruction " other memory accesses Memory 104 and the processing executed by nonvolatile memory 104, such as by concurrently by the second data 122 and update Control information 124 be written in nonvolatile memory 104.As a result, with while storing newer control information The equipment of " obstruction " memory access operation is compared, and handling capacity can be improved.

With reference to figure 2, the certain illustrative example of programming process is depicted, and is generally designated as 200.Programming process 200 can be executed by the data storage device 102 of Fig. 1.It is, for example, possible to use the first memory naked core 106 of Fig. 1 and second is deposited Reservoir naked core 108 executes programming process 200.Fig. 2, which is also described, can use third memory naked core 202 and the 4th memory Naked core 204 executes programming process 200.Third memory naked core 202 and the 4th memory naked core 204 can be included in Fig. 1 Nonvolatile memory 104 in.

Fig. 2 depicts first group of data program operation at 210.For example, data may be programmed into memory naked core 106, one or more of 108,202 and 204.As an illustrative example, data may include the first data 120 of Fig. 1.

Programming process 200 further includes that control procedure operation 222 and one or more data programmings are performed in parallel at 220 Operation.For example, as an illustrative example, Fig. 2 is depicted can be in first memory naked core 106, second memory naked core 108 With execution data program operation at the 4th memory naked core 204.Data may include the second data 122 of Fig. 1.Fig. 2 also describes Third memory naked core 202 can execute control procedure operation 222.For example, execute control procedure operation 222 may include with The newer control information 124 of Fig. 1 is concurrently programmed into third memory naked core 202 by the second data 122 of write-in Fig. 1.

Fig. 2 is also shown can execute third group one or more data program operation at 230.In order to illustrate first Memory naked core 106, second memory naked core 108 and third memory naked core 202 can execute data program operation.Illustrating In property example, programmed data can correspond to secure data before controlling programming operation 222.For example, being compiled at 210 The data of journey can correspond to secure data, and the instruction 126 of Fig. 1 can specify the programmed data at 210 to correspond to Secure data.Concurrently or after controlling procedure operation 222 programmed data can correspond to control procedure operation 222 Easily damaged data.For example, programmed data can correspond to easily damaged data, and the instruction 126 of Fig. 1 at 230 The programmed data at 230 can be specified to correspond to easily damaged data.Depending on particular implementation, with control program behaviour Concurrently programmed data may include secure data or easily damaged data to work 222.For example, the programmed number at 220 According to can correspond to secure data or easily damaged data, and the instruction 126 of Fig. 1 can specify the programmed number at 220 According to corresponding to secure data or easily damaged data.

It can improve that (the data storage of such as Fig. 1 is set in data storage device with reference to the one or more aspects that figure 2 describes The performance at standby 102) place.For example, by being performed in parallel control procedure operation 222 and one or more data program operations, with The equipment of " obstruction " data write operation is compared while storing newer control information, improves handling capacity.

With reference to figure 3, another certain illustrative example of programming process is depicted, and is generally designated as 300.Programming Process 300 depicts operation associated with host data block 302 and control data block 304.For example, host data block 302 can With the region (for example, physical region, logic region or virtual region) corresponding to nonvolatile memory 104, and control number Another region of nonvolatile memory 104 is can correspond to (for example, physical region, logic region or virtual area according to block 304 Domain).

Programming process 300 may include that the first control update is executed at 310.First control update may include that will update Control information 124 store the nonvolatile memory 104 of Fig. 1.Control update can correspond to the control update operation of Fig. 2 222.Newer control information 124 may include instruction 126, and indicate that 126 can specify in execution the first control update Preceding programmed data include secure data 312.Instruction 126 can be further specified that is compiled after executing the first control update The data of journey may include easily damaged data 314.

Programming process 300 further includes that the second control update is executed at 320.Second control update may include by Fig. 1's The again newer version storage of information 184 is controlled to the nonvolatile memory 104 of Fig. 1.Pass through more newly control information again 184, newer control information may include being programmed into nonvolatile memory before more newly control information 184 again again 104 data correspond to the instruction of secure data.For example, easily damaged data 314 can be re-classified as secure data.This Outside, the data programmed later in the update of the second secondary control may be indicated as easily damaged.For example, updating it in the second secondary control Programmed data 324 can be indicated as easily damaged afterwards.

Fig. 3 shows that control update operation could be used to indicate that secure data, easily damaged data or both.Control update Operation, which " can reclassify ", had previously been indicated as easily damaged data.

With reference to figure 4, depicts the certain illustrative example of system and be generally designated as 400.System 400 includes Data storage device 402 and equipment 480 (for example, host equipment or access equipment).Data storage device 402 includes non-volatile Memory 404 and controller 430.Controller 430 is coupled to nonvolatile memory 404.

Nonvolatile memory 404 includes being included in one or more memory naked core (such as first memory naked cores 406 and second memory naked core 408) in non-volatile storage element array.In illustrated examples, first memory naked core 406 and second memory naked core 408 correspond to Fig. 1 first memory naked core 106 and second memory naked core 108.

Controller 430 includes the memory interface 432 to nonvolatile memory 404, and further includes to equipment 480 Equipment interface 472 (for example, host interface).Controller 430 can also include flash translation layer (FTL) (FTL) 438, control circuit 440, Command queue 442, volatile memory 444 and counter 446.As illustrated examples, volatile memory 444 may include Random access memory (RAM).

During operation, controller 430 can receive data 474 from equipment 480, such as in conjunction with to nonvolatile memory 404 write-access request.Controller 430 can execute one or more operations to generate the first data based on data 474 422, such as the first data 422 are generated by being encoded to data 474.In some embodiments (for example, flash memory is implemented Mode) in, the FTL438 of controller 430 is configured as executing logic to physical address translations with will be associated with data 474 Logical address is converted into physical address associated with the first data 422.

In order to initiate the first data 422 storage arriving nonvolatile memory 404, controller 430 is configured as ordering One or more memory commands are lined up at queue 442.It is arranged at command queue 442 for example, controller 430 can be configured as The first set 452 of team's memory command at nonvolatile memory 404 to initiate the storage to the first data 422.Depend on It can be naked with the one or more of nonvolatile memory memory 404 in the first set 452 of particular example, memory command Core (such as first memory naked core 406, second memory naked core 408, one or more of the other memory naked core, or combinations thereof) For target.

Volatile memory 444 is configured as storage control information 484.In order to illustrate control information 484 may include reflecting Firing table 486, and controller 430 can update mapping table 486 in response to storing data into nonvolatile memory 404 and Newer mapping table 428 is generated, such as indicates that nonvolatile memory 404 stores the first data by updating mapping table 486 422.Control circuit 440 can be configured as based on by the first data 422 storage to nonvolatile memory 404 come generate update Control information.

In order to keep the integrality of newer control information 424 (for example, the power cycle at data storage device 402 Later), newer control information 424 can be sent to nonvolatile memory 404 (for example, " backup " update by controller 430 Control information 424 copy).(CS) operation (also referred herein as control update behaviour is synchronized in conjunction with non-obstructive root canal Make), newer control information 424 can be sent to nonvolatile memory 404.

According to the aspect of the disclosure, controller 430 can be configured as the backward order team with first group of storage order 452 Row 442 provide barrier (barrier) and order 454.Barrier command 454 can enable the first set 452 of memory command exist Newer control information 424 is sent to be transported before newer control information 424 is stored in one or more memory naked cores Row.For example, if controller 430 all sends out barrier command 454 to memory naked core 406,408, controller 430 can deposited When reservoir naked core 406,408 runs barrier command 454 confirmation is finished receiving from memory naked core 406,408 (acknowledgement, ACK).In this case, completing ACK can indicate that memory naked core 406,408 has been running for The first set 452 of memory command.As a result, controller 430 can be ordered in response to determination (based on ACK is completed) memory The first set 452 of order has completed that (and newer control information 424 accurately indicates the shape of nonvolatile memory 404 State) store newer control information 424.In illustrated examples, memory naked core 406 and 408 is configured as shielding in operation It is little or no after barrier order 454 lingeringly to immediately continue with order of the processing from command queue 442.In this example, it controls Simultaneously operating processed is the operation of non-obstruction.

In order to further illustrate controller 430 can be non-volatile by the way that the first set 452 of memory command to be supplied to Property memory 404 initiates the operation to the first set 452 of memory command.Controller 430 can be by memory command First set 452 be supplied to after nonvolatile memory 404, barrier command 454 is supplied to nonvolatile memory 404.Memory command in the first set 452 of memory command can be provided to first memory naked core 406, be provided To second memory naked core 408 or be provided to nonvolatile memory 404 one or more of the other memory naked core, Or combinations thereof.

In one or more of the first set 452 of run memory order memory command, non-volatile memories The memory naked core of device 404 can run barrier command 454.In response to running barrier command 454, nonvolatile memory 404 Memory naked core message (for example, complete ACK) can be supplied to controller 430.In order to illustrate Fig. 4 depicts controller 430 can receive one or more message 426 from nonvolatile memory 404.One or more message 426 and barrier command 454 is associated, and may include the completion ACK from memory naked core 406, one or more of 408.For example, response Barrier command 454 is run in first memory naked core 406, first memory naked core 406 can will be in one or more message 426 First message be supplied to controller 430.As another example, barrier command is run in response to second memory naked core 408 454, the second message in one or more message 426 can be supplied to controller 430 by second memory naked core 408.

Controller 430 can be configured as in response to receive each in one or more message 426 adjust by The value 450 that counter 446 indicates.Depending on particular example, controller 430 concurrently or can be sequentially received one or more Message 426.As illustrated examples, controller 430 can be loaded and be written based on the different operating of memory naked core 406,408 Speed is sequentially received one or more message 426.

Controller 430 is configured to determine whether to meet condition associated with barrier command 454, such as one or more Whether the quantity of message 426 meets threshold value 448.In illustrated examples, threshold value 448 and to run barrier command 454 it is non-easily The quantity of the memory naked core of the property lost memory 104 is corresponding.In this example, threshold value 448 can with will be deposited from non-volatile " expected " that reservoir 404 receives completes the corresponding (nonvolatile memory 404 based on reception barrier command 454 of quantity of ACK Memory naked core quantity).Controller 430 can be with use value 450 (for example, by response to each completion ACK received And increment value 450) come monitor receive completion ACK quantity.

Controller 430 can be configured as is compared to determine whether the quantity meets (example by value 450 and threshold value 448 Such as, it is more than or is greater than or equal to) threshold value 448.As illustrated examples, control circuit 440 may include being coupled to counter 446 Comparator circuit.Comparator circuit can be configured as whether completely value 450 and threshold value 448 are compared to determine the quantity Sufficient threshold value 448.

If the quantity fails to meet threshold value 448, controller 430 can determine that the condition is not satisfied.As a result, Controller 430 can wait the other message of at least one of one or more message 426 to be received.As illustrated examples, such as Fruit barrier command 454 is provided to both memory naked cores 406,408, then threshold value 448 can correspond to two, and equal to zero or Quantity equal to one cannot meet threshold value 448.

Alternatively, if the quantity of one or more message 426 meets threshold value 448, controller 430 can determine with 454 associated condition of barrier command is satisfied.In order to illustrate, if barrier command 454 be provided to memory naked core 406, Both 408, then threshold value 448 can correspond to two, and the quantity equal to two meets threshold value 448.In this example, controller 430 can determine that each first set 452 of memory command has been run and newer control information 424 is accurately anti- Reflect the state of nonvolatile memory 404 (due to the first set 452 of run memory order).In this case, it responds Meet threshold value 448 in the quantity of one or more message 426, controller 430 be configured as sending newer control information 424 with Control information 424 is stored in nonvolatile memory 404.

Barrier command 454 can be referred to as " control sync mark ".Barrier command 454 follows the first of memory command to collect 452 are closed, and the completion of the operation of barrier command ensures that the first set 452 of memory command is that newer control letter is being written It is run before breath 424.The second set 456 of memory command can be provided in parallel to non-volatile with barrier command 454 Memory 404 (such as so that the execution of CS operations, which " is not blocked ", writes command to nonvolatile memory 404).

In conjunction with the example of Fig. 4, CS operations are executed by data storage device 402 in a manner of non-obstruction.For example, can be with general Newer control information 424 is sent to nonvolatile memory 404 and is performed in parallel one or more memory access operations.For Further show, in some embodiments, can with send newer control information 424 concurrently by memory command One or more of second set 456 memory command is sent to nonvolatile memory 404, such as by using can be by The multichannel bus being included in memory interface 432.

The one or more aspects with reference to described in figure 4 can improve the performance at data storage device 402.For example, Data storage device 402 is configured as executing CS operations during non-obstruction CS is operated without " obstruction " other memory access behaviour Make.As a result, compared with the equipment of " obstruction " memory access operation while storing newer control information, Ke Yiti High-throughput.

With reference to figure 5, the illustrative aspect of one group of operation is depicted, and is generally designated as 500.Show as illustrative Example, group operation 500 can execute at the data storage device 402 of Fig. 4.

Group operation 500 may include the detection trigger event at 502.Trigger event can correspond to instruction control information 484 conditions that will be updated and be stored at nonvolatile memory 404.For example, trigger condition can be with non-volatile memories The specific quantity of operation at device 404, from previously updated and store control information 484 threshold duration, one or more A other conditions, or combinations thereof it is corresponding.

Group operation 500 further includes the transmission barrier command at 504.For example, controller 430 can be by barrier command 454 It is sent to nonvolatile memory 404.

Group operation 500 further includes the write-in daily record at 506.For example, daily record may include newer control information 424, And daily record can be written in nonvolatile memory 404.In response to determining that the quantity of one or more message 426 meets Threshold value 448, daily record can be written to nonvolatile memory 404.

Group operation 500 further includes the detection trigger event at 508.For example, in response at nonvolatile memory 404 Execute it is certain amount of operation, from previously updated and store control information 484 threshold duration (for example, at 506), One or more of the other condition, or combinations thereof, trigger event can be detected.

Group operation 500 further includes the transmission barrier command at 510.For example, another screen corresponding with barrier command 454 Barrier order can be supplied to nonvolatile memory 404 by controller 430, such as with newer 484 phase knot of control information again It closes.

Group operation 500 further includes the write-in daily record at 512.For example, can be based on holding at nonvolatile memory 404 Capable one or more storage operations carry out again more newly control information 484, and newer control information can be carried again Supply nonvolatile memory 404.

Fig. 5, which is shown, to use barrier to order in conjunction with daily record to be written to the memory of such as nonvolatile memory 404 Enable the example of (for example, barrier command 454).Barrier command may insure that previous storage device order is transported before barrier command Row, and ensures that subsequent memory command is run after barrier command, maintain daily record relative to memory command one Cause property.

Fig. 6 depicts the illustrative aspect of the data storage device 402 of Fig. 4.In figure 6, with reference to the FTL 438 of figure 4, One processor 602 and second processor 604 describe to operate.Referring also to command queue 606, command queue 608, command queue 610 and command queue 612 describe to operate.

During operation, processor 602,604 can be in response to FTL 438.For example, FTL 438 can provide instruction To processor 602,604 to generate barrier command, such as barrier command 454.In the example of fig. 6, command queue 606,608, Each in 610 and 612 can be associated with the specific memory naked core of nonvolatile memory 404.Show as illustrative Example, command queue 606 can be associated with memory naked core n (for example, first memory naked core 406), and command queue 608 Can be associated with memory naked core n+1 (for example, second memory naked core 408), wherein n is positive integer.Command queue 610 can With associated with memory naked core 0, and command queue 612 can be associated with memory naked core 1.

During running order, barrier command 454 can be by each in command queue 606,608,610 and 612 To propagate (for example, " being moved up in the queue " by response to running previous instruction).Due to different naked core characteristics (different naked core workloads or different naked core writing speeds etc.), so the certain of nonvolatile memory 404 deposit Reservoir naked core can reach barrier command 454 before other memory naked cores of nonvolatile memory 404.For example, in Fig. 6 In, command queue 608 can indicate barrier command 454 before instruction barrier command 454 prepares the command queue 610 of operation Prepare operation.

Each memory naked core of operation barrier command 454 can provide the corresponding message of one or more message 426 To the controller 430 of Fig. 4.In order to illustrate Fig. 6 is depicted at 614, corresponds to the specific memory naked core of command queue 610 Particular message (such as naked core barrier response) can be sent.In particular example, transmission naked core barrier response makes one at 614 The quantity of a or multiple message 426 meets threshold value 448.In this example, controller 430 can in response to from memory naked core n, Each in n+1,0 and 1 receives naked core barrier response and initiates newer control information 424 being sent to non-volatile memories Device 404.In the illustrated examples, threshold value 448 can correspond to four.Quantity as one or more message 426 meets threshold Value 448 as a result, controller 430 can detect newer control information 424 it is to be sent arrive nonvolatile memory 404, Maintain consistency of the newer control information 424 relative to the storage operation executed at nonvolatile memory 404.

With reference to figure 7, depicts the illustrative aspect of equipment and be generally designated as 700.The equipment 700 of Fig. 7 One or more aspects can be integrated in the controller 430 of Fig. 4.For example, Fig. 7 depicts the of the FTL 438 and Fig. 6 of Fig. 4 One processor 602.

In the figure 7, multiple queues are coupling between FTL 438 and processor 602.For example, Fig. 7 depict queue 702, Queue 704, queue 706 and queue 708 can be coupling between FTL 438 and processor 602.

The example of Fig. 7 shows multiple barrier commands associated with the message of different number.In order to illustrate Fig. 7's shows Example depicts first barrier command associated with the first barrier mark (" barrierID ") for zero.First barrier command with The first quantity (" numReqs ") of one or more message is associated, which is equal to four (for example, because showing in Fig. 7 The first barrier command can be provided in example to four memory naked cores).As another example, Fig. 7 is further depicted and second for 2 Barrier ID is associated and the second barrier command associated with the second quantity of one or more message, second quantity are equal to 2 (for example, because the second barrier command can be provided to two memory naked cores in the example of Fig. 7).

Any one of barrier command in Fig. 7 can correspond to the barrier command 454 of Fig. 4, and be retouched with reference to figure 7 Any one of quantity of message stated can correspond to the threshold value 448 of Fig. 4.It is each in queue 702,704,706 and 708 It is a to be associated with the corresponding naked core of nonvolatile memory 404.

The example of Fig. 7, which is shown, can use multiple barrier message, wherein each in barrier message and corresponding mark (barrierID) and the corresponding number of message (numReq) is associated.As a result, the controller 430 of Fig. 4 can be adjusted concurrently Multiple operations of one or more CS operations are completed using barrier and included to degree.Depending on particular example, above-mentioned multiple operations May include one or more refresh operations, dependent on prior operation completion one or more controls operations relied on, one A or a number of other operations, or combinations thereof.

With reference to figure 8, depicts the illustrative aspect of the equipment 700 of Fig. 7 and be generally designated as 800.Fig. 8's deposits Storage equipment 800 can be included in the data storage device 402 of Fig. 4.

In the example of fig. 8, first processor 602 includes barrier module 806 and shielded counter (barrier Counter, BC) 808.In particular example, barrier module 806 corresponds to control circuit 440, and BC 808 is corresponding to Fig. 4's Counter 446.

In the example of fig. 8, first processor 602 further includes the first naked core manager 810, the second naked core manager 812 With third naked core manager 814.Each in naked core manager 810,812 and 814 can be with nonvolatile memory 404 Corresponding memory naked core is associated.As illustrated examples, the first naked core manager 810 can be managed in first memory naked core The storage operation being performed at 406, and the second naked core manager 812 can be with the second memory naked core 408 of control figure 4 at Storage operation.

In the example of fig. 8, naked core 810,812 and 814 can be configured as the memory from nonvolatile memory 404 Naked core receives message.In order to illustrate the first naked core manager 810 can be configured as from first memory naked core 406 and receive one First message in a or multiple message 426, and the second naked core manager 812 can be configured as from second memory naked core 408 receive the second message in one or more message 426.In naked core manager 810,812 and 814 each can by with It is set to incremental BC 808, and barrier module 806 can be configured as the value for detecting and being indicated by BC 808 (for example, counter 446 Value 450) when meet threshold value 448.

Fig. 9 depicts the illustrative aspect of the data storage device 402 of Fig. 4.In fig.9, with reference to 438 Hes of FTL of figure 4 The set (such as command queue 606,608,610 and 612) of queue describes to operate.Fig. 9 also shows this group of queue can be with Including queue 902, queue 904 and queue 906.

The set of the queue of Fig. 9 can have there are one be layered configuration.For example, queue 606,608,610 and 612 can be right Should be in " lower " grade of level, and queue 902,904 can correspond to " higher " grade of level.Each " higher " grade queue can To be connected to multiple " lower " grade queues.For example, queue 902 is connected to queue 606,608.As additional example, queue 904 are connected to queue 606,608, and queue 906 is connected to queue 610,612.

In the example of figure 9, barrier command can be sent to one or more of the set of queue team by FTL 438 Row.One or more " lower " queues can be transmitted to by being sent to the barrier command of " higher " queue.For example, Fig. 9 is shown Barrier command 454 can travel to queue 606,608 from queue 902.As another example, Fig. 9 depict barrier command 454 can To travel to queue 606,608 from queue 904.In response to the operation of each in barrier command 454, completing message can be by It is forwarded to FTL 438.

With reference to figure 10, the figure for the operation for showing data storage device is depicted, and by data storage device totality subscript It is denoted as 1000.In illustrated examples, operation 1000 can be executed by the data storage device 402 of Fig. 4.In the example of Figure 10 In, operation 1000 is described with reference to nonvolatile memory 404, FTL 438 and barrier module 806.

Operation 1000 may include that pre- barrier (pre-barrier) request is generated at 1010.For example, FTL 438 can be with Notify FTL 438 that will provide barrier command to barrier module 806 to barrier module 806.

Operation 1000 can also be included in generation barrier request at 1012.For example, barrier request can correspond to barrier life Enable 454.Barrier request can be supplied to barrier module 806 by FTL 438.In some embodiments, barrier module 806 can be with Barrier request is obtained from FTL 438.In some instances, barrier ID can be supplied to by barrier module 806 in conjunction with barrier request Barrier module 806.For example, barrier ID can correspond to any one of the barrier ID described with reference to figure 7.

Operation 1000 can also be included in initialization counter at 1028.For example, the value 450 of counter 446 can respond Sending out and be reset in barrier command 454.

Operation 1000 further includes the offer barrier service request at 1032.As illustrated examples, barrier service request can To be supplied to nonvolatile memory 404 by barrier module 806, first memory naked core can be included in by being such as supplied to 406 or second memory naked core 408 in naked core state machine.

Operation 1000 can also be included at 1052 is supplied to barrier module 806 by completion message.It can be passed at 1064 Down counter such as passes through the value 450 of down counter 446.Operation 1000, which can also be included at 1072, is sent completely message (for example, being sent to FTL mailboxes associated with the FTL of Fig. 4 438).For example, complete message can correspond to one of Fig. 4 or Particular message in multiple message 426.

With reference to figure 11, the illustrated examples of the method for the operation of data storage device are depicted, and by its overall subscript It is denoted as 1100.In illustrated examples, method 1100 is executed by the data storage device 102 of Fig. 1.

Method 1100 is included in 1102 the first data of transmission so that the first data are stored in the non-volatile of data storage device At property memory.For example, controller 130 can send the first data 120 so that the first data 120 are stored in data storage device At 102 nonvolatile memory 104.

Method 1100 further includes：It is non-volatile to be stored in the first data in response to sending the first data at 1104 Newer mapping table is generated at memory.For example, control circuit 140 can be configured as access in volatile memory 144 The control information 184 at place, and update mapping table 186 is configured as to generate newer control information 124.

Method 1100 further includes：At 1106, newer mapping table is concurrently sent after generating newer mapping table With the second data newer mapping table and the second data to be stored at nonvolatile memory.For example, controller 130 can be with It sends the second data 122 and newer control information 124 arrives nonvolatile memory 104.

Method 1100 further includes：At 1108, non-blocking operation (for example, wherein memory naked core be not suspended it is non- Obstruction CS operations) in newer mapping table and the second data stored by nonvolatile memory.In order to illustrate non-volatile memories Device 104 can be to continuing operation (for example, will more during newer control information 124 and the storing of the second data 122 Do not have " to suspend " operation during the CS operations of the new write-in nonvolatile memory of control information 124).

With reference to figure 12, the illustrated examples of the method for the operation of data storage device are depicted, and by its overall subscript It is denoted as 1200.In illustrated examples, method 1200 is executed by the data storage device 402 of Fig. 4.

Method 1200 is included in first set at 1202 by memory command and barrier command is supplied to data storage to set Standby command queue.For example, the first set 452 and barrier command 454 of memory command can be provided to the order team of Fig. 4 Row 442.

Method 1200 further includes：At 1204, in response to the operation of the first set of memory command, set from data storage Standby one or more memory naked cores receive one or more message.For example, memory naked core 406,408 can be in response to fortune Row barrier command 454 (and after first set of run memory order 452) and one or more message 426 are provided.

Method 1200 further includes：At 1206, meets threshold value in response to the quantity of one or more message, send mapping table Mapping table data to be stored at one or more memory naked cores by data.Run memory order first set it Afterwards, the operation triggering of barrier command sends mapping table data so that mapping table data are stored in one or more memory naked cores Place.In order to illustrate meeting threshold value 448 in response to the quantity of one or more message 426, controller 430 can be reflected newer Firing table 428 is sent to nonvolatile memory 404.

Method 1200 can also include：During non-obstructive root canal simultaneously operating, to the storage by nonvolatile memory The user data that device naked core is written to nonvolatile memory executes continuous processing.For example, non-easy arriving the storage of mapping table 428 After the property lost memory 404, nonvolatile memory 404 can execute one or more additional non-obstructive root canals and synchronize behaviour Make, such as arrives nonvolatile memory by updating mapping table 428 again and storing mapping table 428 again with non-blocking fashion (for example, executing continuous processing to the user data for being written to nonvolatile memory 404 and not having " to block " in 404 When user data is written to nonvolatile memory 404).

In another example, data storage device is configured as asynchronously executing merging behaviour relative to control simultaneously operating Make.Union operation and control simultaneously operating can be handled as the non-obstruction of separation to execute.In particular example, the number of Fig. 4 It is configured as asynchronously executing union operation relative to control simultaneously operating according to storage device 402.

By data storage device execute control simultaneously operating may include by main table and to being updated/written to for main table it is non- Volatile memory (for example, by the way that main table is copied to nonvolatile memory from volatile memory).For example, main table can be with The previous logic of nonvolatile memory (via first control simultaneously operating) is stored in physics including being directed toward The pointer of address (logical-to-physical, L2P) " block (chunk) " (or part of L2P mapping tables).Main table is also May include newer " update step " (from the preceding control simultaneously operating) for indicating L2P mapping tables.L2P mappings can be based on Data in L2P blocks add the possible increment (delta) from " update step ".Increment can also be stored in referred to as CAT In the cache of the L2P blocks of (Cached Address Translation, cached address conversion).CAT tables can be with It is stored in volatile memory, is such as stored in static RAM (static random access Memory, SRAM) in.In some embodiments, " update step " is not present, and updates and is stored in CAT, it can be through By merging process by regular expulsion to flash memory (or by regular expulsion to another nonvolatile memory).

Union operation may include the update (or the update being stored in CAT) of update step is fused to be stored in it is non-easily In L2P blocks at the property lost memory.Union operation can be executed and be fused to discharging the space in update step or updating CAT Flash memory (or being fused to another nonvolatile memory).For example, update step can become " expiring ", and can be by will be with update The associated update of layer copies to nonvolatile memory " evacuation " update step from volatile memory.

By being detached to union operation and control simultaneously operating, operation can " thinner ", and can be more effectively And it is carried out using less time and process resource.In addition, in some cases, the frequency of union operation is (for example, more Mew layer becomes the frequency of " full ") it is likely larger than the frequency of control simultaneously operating.Pass through lock out operation, it is possible to reduce for executing " no It is necessary " control simultaneously operating time with process resource (for example, it is synchronous by more less frequent than union operation to execute control Operation).

If CAT not yet updates, it includes the atom that update step is dispersed into CAT tables that non-obstruction union operation, which can use, Technology.The evacuation (evacuation) of update step and the compression (compaction) of update step can be executed together (in update step After evacuation).If improper pass occurs for (and before subsequent control simultaneously operating) after non-obstruction union operation Machine (UGSD), the then state that data storage device can be indicated by the previous version of " rollback " to control table, the wherein control table Previous version be stored in nonvolatile memory using previous control simultaneously operating.

As lock out operation and in the case of UGSD rollback control to the end synchronous regime as a result, can be in CAT Block executes the update to CAT while being just stored in nonvolatile memory.Therefore, write operation need not be grasped merging It is stopped or postpones (for example, " obstruction ") during work.On the contrary, update associated with write operation can be in specific union operation Period is written to update step and CAT.Update can be written to during subsequent operation in nonvolatile memory.

In order to further illustrate in the example of union operation, the SRAM copies of mapping table can be updated, such as by repairing Change the SRAM cache of update step and the addresses the correspondence L2P block alternately through modification CAT tables.In order to make union operation Can be non-obstruction, to the update of update step can each block in an atomic manner (for example, in the center of data storage device During the operation of processing unit (central processing unit, CPU)) it is fused in CAT tables.It is fused to that will update After in CAT tables, the CAT blocks of selection can be written to nonvolatile memory (for example, using union operation).It is executing While union operation, the request to accessing nonvolatile memory can be run, such as by running request to write data Enter to nonvolatile memory.Because CAT tables (rather than update step) are written to nonvolatile memory by union operation, Update step can during union operation by modification (for example, by change update step using indicate newer L2P address of cache as Run the result of request), and update step can be then written into via the control simultaneously operating executed after the merge operation To nonvolatile memory.

In some cases, the specific request received during union operation can indicate the targeted ground of union operation Location.As a result, update can be applied to also be written to nonvolatile memory (for example, via union operation) The L2P " block " of particular cache.In this case, update can be written in advance nonvolatile memory (for example, Before host data associated with specific request is submitted to nonvolatile memory).It is advantageous according to the technology of the disclosure Ground allows such situation, because could only be used after power cycle there are additional control simultaneously operating It is written to the new block of nonvolatile memory (as the pointer for being directed toward the write area block during control is synchronous).The synchronous behaviour of control Previously written data should be submitted to nonvolatile memory by work, include by the data of specific request instruction.

Although the description of front is related to the particular example of update step and CAT tables, it should be appreciated that, the present disclosure is not limited to this The particular example of sample.In order to illustrate describing Figure 13 to Figure 16's with reference to a part for control table and the parts L2P of cache Non- obstruction union operation.

With reference to figure 13, depicts the certain illustrative example of system and be generally designated as 1300.System 1300 Including data storage device 1302 and equipment 1380 (for example, host equipment or access equipment).Data storage device 1302 by with It is set to and executes non-obstruction union operation.

Data storage device 1302 includes nonvolatile memory 1304 and controller 1330.Controller 1330 is coupled to Nonvolatile memory 1304.

Nonvolatile memory 1304 includes the non-volatile memories member being included in one or more memory naked cores Part array.The one or more aspects of nonvolatile memory 1304 can be such as nonvolatile memory 104, Fig. 4 with reference to figure 1 Nonvolatile memory 404, or combinations thereof described in like that.In illustrated examples, nonvolatile memory 1304 wraps Include the first memory naked core 406 or Fig. 4 of the first memory naked core 106 of Fig. 1, the second memory naked core 108 of Fig. 1, Fig. 4 One or more of second memory naked core 408.Nonvolatile memory 1304 includes one or more sets of memory elements, Such as represent block 1306.

Controller 1330 includes the memory interface 1332 to nonvolatile memory 1304, and further includes to equipment 1380 equipment interface 1372 (for example, host interface).Controller 1330 can also include flash translation layer (FTL) (FTL) 1338, meter Number device 1346, counter 1352 and volatile memory 1344.As illustrated examples, volatile memory 1344 may include Random access memory (RAM).

Volatile memory 1344 is configured as the first of storage control table associated with nonvolatile memory 1304 Copy 1384.Nonvolatile memory 1304 can be configured as the triplicate 1310 of storage control table.Controller 1330 can To change the first authentic copy 1384 based on the write operation executed at nonvolatile memory 1304, and can then be based on Triplicate 1310 is updated (for example, by the way that the change of the first authentic copy 1384 is traveled to the change of the first authentic copy 1384 Two copies 1310).

During operation, controller 1330 can retrieve control information from nonvolatile memory 1304.As an example, ringing Event should be powered at data storage device 1302, it is secondary that controller 1330 can retrieve first from nonvolatile memory 1304 Sheet 1384 and pattern storage (for example, cache) first authentic copy 1384 at volatile memory 1344.

Controller 1330 can be received from equipment 1380 asks accessing the one or more of nonvolatile memory 1304. For example, equipment interface 1372 is configured as receiving the first request to accessing nonvolatile memory 1304 from equipment 1380 1376.In particular example, the first 1376 designation dates 1374 of request will be written to nonvolatile memory 1304.Controller 1330 can execute one or more operations based on data 1374, such as encoded to generate by being encoded to data 1374 Data Concurrent send encoded data so that encoded data to be stored at nonvolatile memory 1304.

In some embodiments, the FTL 1338 of controller 1330 be configured to respond to the first request 1376 execution patrol It collects and arrives physics (L2P) address conversion.For example, FTL 1338 can be configured as arrives non-volatile memories by the storage of data 1374 Before device 1304, logical address associated with data 1374 is converted into physical address associated with data 1374.

Controller 1330 be configured to respond to the first request 1376 execute the first authentic copy 1384 part 1340 (for example, Update step) first update.For example, part 1340 can be in modification triplicate 1310 to refer to before indicating L2P address conversions Show L2P address conversions.As a specific example, controller 1330 can be with the first of execution part 1340 before initiating the second update The specific L2P address conversions executed in response to the first request 1376 of operation are updated to indicate that, wherein the second update is by L2P Location conversion merges with triplicate 1310.First update may include that particular items are added to the L2P indicated by part 1340 The list of address of cache.

In some embodiments, controller 1330 is configured to respond to the first request 1376 of operation and updates effectively meter Number 1350.For example, the quantity of invalid page associated with nonvolatile memory 1304 can be indicated by effectively counting 1350, and And controller 1330 can be in response to being moved to nonvolatile memory 1304 by data associated with particular physical address Another physical address effectively counts 1350 to update.

After executing the first update of the part 1340 of the first authentic copy 1384 in response to the first request 1376, controller 1330 can initiate the second update of triplicate 1310 based on the first update at nonvolatile memory 1304.For example, the Two update can be included in atom union operation 1324, by with 1384 phase of the first authentic copy at volatile memory 1344 Associated modification is merged with the triplicate 1310 at nonvolatile memory 1304, is such as stored to non-by that will update 1328 Volatile memory 1304 is to indicate modification associated with the first authentic copy 1384.

In particular example, in response to detecting that the quantity of the modification carried out to the first authentic copy 1384 meets threshold value 1348, Controller 1330 can execute the second update.In order to illustrate counter 1352 can be configured as storage value 1354, the value 1354 It indicates from the previous update to triplicate 1310 to be performed the quantity of the modification to the first authentic copy 1384.In response to receiving To the first request 1376, controller 1330 can be configured as modification (for example, being incremented by) value 1354 and be configured to determine that value Whether 1354 meet threshold value 1348.As non-limitative illustration example, threshold value 1348 can correspond to 10 modification, 20 repair Change or the modification of another quantity, and controller 1330 can be configured as in response to detect value 1354 be greater than or equal to 10, 20 or another quantity and execute the second update.

In particular example, controller 1330 be configured to respond to execute second update and in volatile memory 1344 Place executes squeeze operation.For example, after executing the second update, controller 1330 " can remove " (or " emptying ") and correspond to portion Divide 1340 data structure (for example, subsequent L2P entries is enable to be added to part 1340).

Second update is non-obstruction for the one or more of the other operation that can be executed by data storage device 1302. For example, data storage device 1302 can be configured as is performed in parallel one or more operations with the second update.In order into one Step explanation, controller 1330 are configured as concurrently running (for example, rather than blocking holding for the second request 1378 with the second update Row, until completing the second update, vice versa) ask 1378 to accessing the second of nonvolatile memory 1304.As explanation Property example, the second request 1378 can indicate the write operation that data 1377 are written to nonvolatile memory 1304, and Data 1377 concurrently can be written to nonvolatile memory 1304 by the second request 1378 with the second update is executed.

Controller 1330 is configured as executing control simultaneously operating 1322.It may include by first to control simultaneously operating 1322 Copy 1384 stores nonvolatile memory 1304 (for example, by will be secondary with second to change that the first authentic copy 1384 carries out This 1310 " fusion ").Controller 1330 can be configured as execution control simultaneously operating 1322 with atom union operation 1324 The first authentic copy of control table 1384 is independently copied into nonvolatile memory 1304.

Nonvolatile memory can be arrived by change " submission " associated with the second update by controlling simultaneously operating 1322 1304.In order to further illustrate the second update can execute on atomic basis, wherein second is updated successfully or fails.Control The execution of simultaneously operating 1322 can make second to be updated successfully, and such as pass through " submission " change associated with the second update.

Alternatively, in some cases, the second update may fail.For example, in some cases, in the synchronous behaviour of control Abnormal shutdown (UGSD) event may occur before making 1322.UGSD events may cause to be stored in volatile memory 1344 The information at place is lost from data storage device 1302.For example, the UGSD events occurred before controlling simultaneously operating 1322 can The first authentic copy 1384 can be caused to be lost from volatile memory 1344 (and from data storage device 1302).

Controller 1330 be configured as second update after detection UGSD events and be configured as UGSD events it After re-execute operation associated with the second update.For example, triplicate 1310 can indicate nonvolatile memory 1304 The block finally opened, such as block 1306.Controller 1330 can be configured as through scanning block 1306 to identify in UGSD things Be written to before part nonvolatile memory 1304 data (such as by identify data 1374, data 1377, or both) come Re-execute operation.As illustrated examples, controller 1330 can be with the metadata of scan data 1374,1377 (for example, header Information) to determine that data 1374,1377 control simultaneously operating (for example, the first authentic copy 1384 is written to non-volatile previous Property memory 1304 control simultaneously operating) after and be written to before UGSD events nonvolatile memory 1304.

Controller 1330 can be configured as is written to nonvolatile memory in response to being identified before UGSD events 1304 data operate to re-execute one or more associated with the second update.For example, from nonvolatile memory 1304 retrieve the first authentic copy 1384 and the first authentic copy 1384 are stored (for example, cache) at volatile memory 1344 Later, controller 1330 can update triplicate 1310 (for example, to generate the first authentic copy 1384) and can re-execute Control simultaneously operating 1322.

Control simultaneously operating 1322 can be blocked relative to one or more requests from equipment 1380.For example, Controller 1330 can be configured as the operation of blocking request, until completing control simultaneously operating 1322 (or vice versa).

It may include that pointer information is copied to non-volatile deposit from volatile memory 1344 to control simultaneously operating 1322 Reservoir 1304, such as by replicate indicate storage control table (e.g., including update triplicate 1,310 1328) it is non-volatile The pointer of the position of property memory 1304.In this case, controller 1330 be configured as update control table in pointer with Indicate position of the triplicate 1310 of control table in nonvolatile memory 1304.

It can make union operation (for example, atom union operation 1324) can with reference to the one or more aspects that figure 13 describes It is executed with non-blocking fashion, without the risk of the loss of data caused by UGSD events.If controlled in execution " submission " UGSD events occur before the union operation of the change of simultaneously operating processed, then it can be heavy after data storage device 1302 starts The new operation for executing (or " playback ") update operation.Therefore, union operation can be executed in a manner of non-obstruction, without due to UGSD events and the risk for leading to loss of data.

Figure 14 is the certain exemplary block diagrams for the operation for showing to execute at the data storage device 1302 of Figure 13. In particular example, feature associated with controller 1330 is shown in the top section of Figure 14, and in the bottom of Figure 14 Feature associated with nonvolatile memory 1304 is shown in part.

Figure 14 depicts certain illustrative aspects (for example, current version of control table) of the first authentic copy 1384.For example, the One copy 1384 may include pointer 1404 (for example, pointer of the instruction when proparea, also referred to as " block (chunk) " of L2P tables Or " part "), the list 1408 of free block that can be used for newly being written and part 1340.In particular example, part 1340 is wrapped Include the multiple lists of (or corresponding to) with address modification updates the data structure, each in multiple lists corresponds to difference One group of logical block address (logical block addresse, LBA).For example, part 1340 can be indicated non-volatile The list that execution but the L2P not yet merged are converted at memory 1304.

Controller 1330 can also store the parts L2P 1412 (for example, CAT tables) of cache.In order to further illustrate, The parts L2P 1412 that the example of Figure 14 depicts cache may include part 1,2,12,32,57 and 953.In order to illustrate, Each parts L2P can correspond to the range of LBA (for example, 32 Mbytes of (megabyte, MB) ranges of logical address are mapped To part 32 kilobytes (kilobyte, kB) of physical address) and may include physical address translations for LBA.Therefore, Entire L2P tables are not copied into volatile memory 1344 from nonvolatile memory 1304, it can will be newer The section of table copies to L2P part 1412 of the volatile memory 1334 as cache.

Nonvolatile memory 1304 can store L2P tables 1416.In the illustrated examples of Figure 14, L2P tables 1416 wrap Include part 1,2,3,4,5,6 ..., 100000.For example, part 1 may include the 32MB range (examples for the first logical address Such as, 0-32MB) change data, part 2 may include the 32MB ranges (for example, 32-64MB) for the second logical address Change data etc..Though it is shown that 100000 parts are (for example, support 3.2TB (terabyte, terabyte) logically Location range), but in other embodiments, L2P tables 1416 may include less than 100000 parts or more than 100000 Part, the size of each in memory capacity and the parts L2P such as based on nonvolatile memory 1304.

Nonvolatile memory 1304 also stores update 1328.For example, update 1328 can be via atom union operation 1324 are stored in nonvolatile memory 1304.In the illustrated examples of Figure 14, update 1328 includes part 2 and 12.

Nonvolatile memory 1304 also stores triplicate 1310 (for example, submission version of control table).Triplicate It is " old " or " out-of-date " information (for example, not yet via the control of Figure 13 that 1310, which may include compared with the first authentic copy 1384, The information of simultaneously operating 1322 and the first authentic copy 1384 " synchronous ").For example, triplicate 1310 may include instruction " old " The pointer 1422 of the parts L2P.

In order to illustrate, triplicate 1310 pointer 1422 can indicate (for example, direction) L2P tables 1416 part 1,2, 3 and 4.In the example in figure 14, the pointer 1404 of the first authentic copy 1384 indicates the update to part 2.For example, with certain logic The associated data in location can be copied to the second physical address, and the data at the first physical address from the first physical address It can fail.It (is grasped for example, merging via atom as a result, update 1328 can be written to nonvolatile memory 1304 Make 1324) to indicate the second physical address (rather than first physical address).Before executing control simultaneously operating 1322, storage Control information at nonvolatile memory 1304 can indicate " old " physical address (the first physical address).Executing control When simultaneously operating 1322 processed, " correct " physical address can be indicated by being stored in the control information at nonvolatile memory 1304 (the second physical address).The specific example of the operation of the component including Figure 14 is also described in detail with reference to figure 15.

It is liftoff that the example of Figure 14 shows that union operation and control simultaneously operating can be punished in data storage device 1302 It executes.As a result, if UGSD events occur before executing control simultaneously operating, one or more behaviour of union operation Work can be by " playback ".

Figure 15 is the certain exemplary ladders for the operation 1500 for showing to execute at the data storage device 1302 of Figure 13 Shape figure.In the example of Figure 13, reference device 1380, FTL 1338, the first authentic copy 1384 of control table and non-volatile memories Device 1304 describes operation 1500.

Operation 1500 is included in the first writing commands that the first logical address of instruction is received at 1502.For example, the first write-in Order can correspond to the specific request received from the equipment 1380 of Figure 13.

Operation 1500 further includes the part 1340 that the first L2P address of cache is added to the first authentic copy 1384 at 1504. For example, controller 1330 can update part 1340 to indicate the first object of the first logical address and nonvolatile memory 1304 It is associated to manage address, such as by adding entry to part 1340 to indicate that the first logical address is related to the first physical address Connection.

Operation 1500 further includes that associated with the first physical address the first write operation is executed at 1506 to run the One writing commands.For example, data storage device 1302 data indicated by the first writing commands can be written to it is non-volatile Memory 1304.

Operation 1500 further includes that the second writing commands of the second logical address of instruction are received at 1508.For example, second writes Enter the first request 1376 that order can correspond to Figure 13.

Operation 1500 further includes that the 2nd L2P address of cache is added to part 1340 at 1510.For example, controller 1330 Part 1340 can be updated to indicate that the second logical address is associated with the second physical address of nonvolatile memory 1304.It is all Such as by adding entry to part 1340 to indicate that the second logical address is associated with the second physical address.

Operation 1500 further includes that associated with the second physical address the second write operation is executed at 1512 to run the Two writing commands.For example, data 1374 can be written to nonvolatile memory 1304 by data storage device 1302.

Operation 1500 further includes being read from the first position of nonvolatile memory 1304 with first logically at 1514 Associated first parts L2P in location.For example, the parts the first L2P can be from the L2P tables 1416 in nonvolatile memory 1304 The volatile memory for being retrieved and can be by storage (for example, cache) in the parts L2P 1412 of cache At 1344.

Operation 1500 further includes that the update of first logical address is fused in the first parts L2P at 1516.For example, control Device 1330 processed can change the first L2P part with indicate the first L2P address of cache (for example, by by the first L2P address of cache with First L2P partial fusions are to generate newer first parts L2P).

Operation 1500 further includes at 1518 by the second of newer first L2P partial writes nonvolatile memory 1304 Position.For example, data storage device 1302 can retrieve newer first parts L2P from volatile memory 1344, and can With by the newer first L2P updates 1328 that copy in nonvolatile memory 1304 of part (for example, to indicate and the Associated " correct " the L2P mappings of one logical address).

Operation 1500 further includes that pointer associated with the first parts L2P is updated at 1520 to indicate the second position.Example Such as, the first pointer in pointer 1404 can be updated to indicate the second position rather than first position is (for example, to indicate second Position storage " correct " mapping associated with the first logical address).

Operation 1500 further includes being read from the third place of nonvolatile memory 1304 with second logically at 1522 Associated 2nd parts L2P in location.For example, the parts the 2nd L2P can be from the L2P tables 1416 in nonvolatile memory 1304 The volatile memory for being retrieved and can be by storage (for example, cache) in the parts L2P 1412 of cache At 1344.

Operation 1500 further includes that will be fused in the 2nd parts L2P to the update of the second logical address at 1524.For example, Controller 1330 can change the parts the 2nd L2P to indicate the 2nd L2P address of cache (for example, by by the 2nd L2P address of cache With the 2nd L2P partial fusions to generate newer 2nd parts L2P).

Operation 1500 further includes at 1532 by the of newer 2nd L2P partial writes to nonvolatile memory 1304 Four positions.For example, data storage device 1302 can retrieve newer 2nd parts L2P from volatile memory 1344, and It can be by update 1328 that the parts newer 2nd L2P copy in nonvolatile memory 1304 (for example, to indicate and the Associated " correct " the L2P mappings of two logical addresses).In particular example, operation 1532, which corresponds to, to be described with reference to figure 13 Second update.

Operation 1500 further includes that pointer associated with the 2nd parts L2P is updated at 1534 to indicate the second position.Example Such as, the second pointer of pointer 1404 can be updated to indicate the 4th position rather than the third place (for example, to indicate second Set storage " correct " mapping associated with the second logical address).

In the example of fig. 15, in conjunction with non-obstruction union operation 1550 execute operation 1514,1516,1518,1520, 1522,1524,1532 and 1534.Non- obstruction union operation 1550 can correspond to the atom union operation described with reference to figure 13 1324。

Non- obstruction union operation 1550 can be with one or more of the other operation at data storage device 1302 concurrently It executes.In order to illustrate the example of Figure 15 shows and can be executed and ablation process 1560 during non-obstruction union operation 1550 Associated one or more operations.One or more operations of ablation process 1560 can be in non-1550 phase of obstruction union operation Between execute, and do not postpone (or " obstruction ") ablation process 1560 until completing non-obstruction union operation 1550.

To further illustrate, ablation process 1560 may include receiving to indicate that the third of third logical address is write at 1526 Enter order.For example, third writing commands can correspond to the received from the equipment 1380 of Figure 13 second request 1378.Ablation process 1560 can also be included in the part 1340 that the 3rd L2P address of cache is added to the first authentic copy 1384 at 1528.For example, control Device 1330 can update part 1340 to indicate third physical address phase of the third logical address with nonvolatile memory 1304 Association, such as by adding entry to part 1340 to indicate that third logical address is associated with third physical address.It was written Journey 1560, which can also be included at 1530, executes third write operation associated with third physical address to run third write-in Order.For example, the data indicated by third writing commands can be written to nonvolatile memory by data storage device 1302 1304, such as by the way that data 1377 are written to nonvolatile memory 1304.

After executing non-obstruction union operation 1550, operation 1500 can also include executing control simultaneously operating 1570. In particular example, control simultaneously operating 1570 corresponds to the control simultaneously operating 1322 of Figure 13.The synchronous behaviour of control can be executed Make 1570 with " submissions " it is non-obstruction union operation 1550 operation (such as so that it is non-block union operation 1550 operation " at Work(").

It may include that part 1340 is written to nonvolatile memory 1304 at 1536 to control simultaneously operating 1570.Control Simultaneously operating 1570 processed can also be included at 1538 is written to nonvolatile memory by the parts L2P 1412 of cache 1304, and be included at 1540 and pointer 1404 is written to nonvolatile memory 1304.For example, part 1340, high speed are delayed The parts L2P 1412 deposited and pointer 1404 can be by being written to nonvolatile memory 1304 by the first authentic copy 1384 of Figure 13 To be written to nonvolatile memory 1304.

Control simultaneously operating 1570 can be optionally included at 1542 the other information from control table is written to it is non- Volatile memory 1304.As illustrated examples, the list 1408 of the free block that can be used for newly being written can be written into it is non-easily The property lost memory 1304.

Control simultaneously operating 1570, which can also be included at 1544, updates pointer to indicate newer control table.For example, can Indicate that storage first is secondary when executing control simultaneously operating 1570 to update the pointer stored by nonvolatile memory 1304 The specific position memory 1304 of this 1384 nonvolatile memory.

The example of Figure 15 shows that can execute union operation with non-blocking fashion (was such as written to avoid ablation process Journey 1560) delay (or " obstruction ") operation.As a result, it is possible to reduce the stand-by period.

Other than the stand-by period caused by non-obstruction union operation 1550 is reduced, the structure based on part 1340 can be with The additional stand-by period is caused to reduce.For example, including the implementation for single, the non-classified list that LBA maps in part 1340 In mode, it is positioned in combined list, corresponding with the parts single L2P (for example, all LBA in specified range) All LBA map：Repeatedly for each in the parts L2P to be changed based on the entry in part 1340 It is a, relatively interminable, linear session search is carried out in the entry of relatively large amount in lists.

Search for the associated stand-by period with this linear session can be by being arranged as the more of LBA mappings by part 1340 A list is reduced.It can interlock in list with each associated address range in multiple lists.For example, the One list can track L2P corresponding with the first parts L2P of L2P tables mapping, and second list can track the with L2P tables Corresponding L2P mappings in two parts L2P, etc., until the 256th list corresponding with the part 256 of L2P.First list is also Mapping corresponding with part 257 can be tracked, second list can also track mapping corresponding with part 258, etc..One As for, list quantity " n " (n=1 to 256) can track the mapping for part n, n+256, n+512 etc..Because accessing non- Each process of volatile memory 1304 can access storage address no more than 8 gigabytes (gigabyte, GB) Range, so each process can only influence to distribute to the single part of each list in list.Therefore, including with process phase Each list of associated map information only includes the map information of single part (for example, first list only includes for part 1 Mapping, and not comprising mapping for part 257,513 etc.).Therefore the single row with part 1340 can be reduced or eliminated The associated linear session search of table structure.It should be understood that list (256) quantity and process address range (8GB) only It is illustrative, and other embodiment may include the address of the list and other ranges of other quantity.

Figure 16 is depicted can be by the certain illustrated examples for the operation 1600 that data storage device executes.For example, can be with The operation of Figure 16 is executed by the data storage device 1302 of Figure 13.

Operation 1600 is included at 1602 and main-machine communication.For example, data storage device 1302 can receive to access it is non- One or more requests of volatile memory 1304, such as by receiving the first request 1376.

Operation 1600 further includes to the first m- of the update step (U- layer) in volatile memory set (m- gathers 1) and the Two m- set (m- set 2) executes update, for example, controller 1330 can be configured as in response to first ask 1376 update by The L2P mappings that part 1340 at volatile memory 1344 indicates.

Operation 1600 further includes executing atom evacuation and compressing concurrently to evacuate and be compressed to volatile storage by U- layers The address translation table (CAT) (for example, to generate m- set 1* and m- set 2*) of cache in device.For example, controller 1330 may be configured to evacuate part 1340 and be compressed to the parts L2P 1412 of caching.

Operation 1600 further includes executing non-blocking asynchronous at 1608 to merge (for example, to gather m- set 1* and m- 2* is written to flash memory or other nonvolatile memories).

For example, controller 1330, which can be configured as, executes 1324 or non-obstruction union operation 1550 of atom union operation.

Operating 1600 further includes：In next non-obstructive root canal simultaneously operating (for example, in control simultaneously operating 1322,1570 Either one or two of) in, by the daily record 1620 of the pointer including being directed toward new newer m- set (for example, being directed toward m- set 1*, 2*) It is written to nonvolatile memory.Compared with " old " daily record 1610 of instruction " old " m- set (m- gathers 1,2), update refers to The pointer gathered to new newer m- can be with Update log.Daily record 1610 includes being directed toward " old " m- set (m- set 1,2) Pointer, and daily record 1620 includes being directed toward the pointer of " new " m- set (m- set 1*, 2*).For example, daily record 1610,1620 The copy 1310,1384 of control table can be corresponded respectively to, and the triplicate 1310 of control table can be based on control table The first authentic copy 1384 is updated.As Figure 14 example in describe, triplicate 1310 may include being directed toward " old " L2P portions The pointer 1422 divided, and the first authentic copy 1384 may include the pointer 1404 for being directed toward the parts " current " L2P.

Non- obstructive root canal simultaneously operating can be executed using barrier command with non-blocking fashion.For example, barrier command can be with Corresponding to the barrier command 454 of Fig. 4.Barrier command can make the data and control information being written in nonvolatile memory It can be consistent.

Operation 1600 can optionally include detection UGSD events.In such a case, it is possible to rollback and recovery control table, Such as by retrieving the daily record finally stored from nonvolatile memory and volatile memory being written in the daily record finally stored. In this case, the recent renewal executed in U- layers of volatile memory and CAT by controller will lose and quilt Ignore, without losing consistency.

Figure 17 is the exemplary flow chart of certain illustrative of the method 1700 of the operation of equipment.For example, method 1700 can be with It is executed by the data storage device 1302 of Figure 13.

Method 1700 is included at 1702 receives the first request to execute to the first equipment by the first equipment from the second equipment Nonvolatile memory the first write operation.For example, the first equipment can correspond to data storage device 1302 and Two equipment can correspond to equipment 1380.Data storage device 1302 can receive the first request 1376 with by data 1374 from setting Standby 1380 are written to nonvolatile memory 1304.

Method 1700 further includes executing in response to executing the first write operation at 1704 and being stored in the first equipment First update of a part for the first authentic copy of the control table at volatile memory.For example, data storage device 1302 can be with Update the information at volatile memory 1344, such as operation 1504 or operation 1510 by executing Figure 15.

Method 1700 further include executed at nonvolatile memory at 1706 control table triplicate second more Newly triplicate will be traveled to the modification of the first authentic copy.For example, data storage device 1302, which can execute atom, merges behaviour Make 1324 or non-obstruction union operations 1550 mapping L2P associated with the first write operation from volatile memory 1344 It is written to nonvolatile memory 1304, such as operation 1518 or operation 1532 by executing Figure 15.

Method 1700 further includes being write to the second of nonvolatile memory in execution the second reproducting periods execution at 1708 Enter operation.For example, the second write operation can correspond to the write operation executed based on the second request 1378.Show as another Example, the second write operation can correspond to the operation 1530 of Figure 15.

In conjunction with described embodiment, a kind of device includes nonvolatile memory (for example, nonvolatile memory 1304) and it is coupled to the controller (for example, controller 1330) of nonvolatile memory.Controller includes volatile memory (for example, volatile memory 1344) and it is configured as executing the non-obstructive root canal simultaneously operating of separation (for example, control synchronizes Operate 1322,1570) with non-obstruction union operation (for example, one or more of atom union operation 1324, non-obstruction merge 1606) operation 1550 or non-blocking asynchronous merge.

Controller can be configured as according to update step fill up it is required by state, relative to non-obstructive root canal simultaneously operating Non- obstruction union operation is asynchronously executed with different rates.For example, the quantity in response to detecting the modification to part 1340 1354 meet threshold value 1348, and controller 1330 can execute non-obstruction union operation (for example, being detected in response to being based on quantity 1354 To " the filling up state " of part 1340, controller 1330 " can evacuate " part 1340).Non- obstruction union operation can be with non-resistance Independently (and with frequency different with non-obstructive root canal simultaneously operating) occurs for plug control simultaneously operating.

Non- obstruction union operation can be atomic operation comprising update step (U- layers) is concurrently evacuated and is compressed to easily The address translation table (CAT) of cache in the property lost memory.For example, part 1340 concurrently can be evacuated and be compressed to The parts L2P 1412 of cache at volatile memory 1344.

Controller can be configured as continue to execute in volatile memory U- layers and CAT (for example, to cache L2P blocks, also referred herein as " m- set ") update, newer m- set is written to flash memory or it is other it is non-easily The property lost memory.In this example, it executes relative to one or more of the other non-obstruction of operation (for example, not blocking will more New control table is written to nonvolatile memory, such as in the certain equipment for synchronously executing control simultaneously operating and union operation In) union operation.

Controller can be configured as continuation and is performed in parallel with non-obstruction union operation and non-obstructive root canal simultaneously operating To the host write operation of nonvolatile memory.For example, the second request 1378 can be with non-obstruction union operation and non-obstruction Control simultaneously operating is concurrently run.

Controller can be configured as：It includes being directed toward to be updated in next non-obstructive root canal simultaneously operating using barrier command The daily record of the pointer of new newer m- set simultaneously stores daily record in the nonvolatile memory.Barrier command can make to be write The data entered to nonvolatile memory are consistent with control data.In order to illustrate, daily record can correspond to the second daily record 1620, and And barrier command can correspond to the barrier command 454 of Fig. 4.

Controller can be configured as：In the case of abnormal shutdown (UGSD) event, deposited according to from non-volatile The daily record of the control synchronization finally stored in reservoir finally stored is by control table rollback and is restored to volatile memory, and And in this case, the recent renewal executed in U- layers and CAT by controller will lose and be ignored, without losing Lose consistency.For example, " rollback " may include from the retrieval triplicate 1310 of nonvolatile memory 1304 and secondary by second Volatile memory 1344 is arrived in this 1310 storage.

In conjunction with described embodiment, a kind of device includes nonvolatile memory (for example, nonvolatile memory 1304) and it is coupled to the controller (for example, controller 1330) of nonvolatile memory.Controller includes volatile memory (for example, volatile memory 1344) and it is configured as executing non-obstructive root canal simultaneously operating (for example, control simultaneously operating 1322、1570).Controller is additionally configured to asynchronously execute non-obstruction union operation relative to non-obstructive root canal simultaneously operating (for example, atom union operation 1324, non-obstruction union operation 1550 or non-blocking asynchronous merge one or more of 1606). In certain illustrative example, non-obstruction union operation is atomic operation, which includes by update step (for example, part 1340) address translation table of cache in volatile memory is concurrently evacuated and is compressed to (for example, cache The parts L2P 1412).Controller can be configured as (for example, by second request 1378 of operation) and execute merges behaviour with non-obstruction Make the parallel host write operation to nonvolatile memory.

In conjunction with described embodiment, a kind of device includes device for storing data (for example, nonvolatile memory 1304).This device further includes for being received from access equipment (for example, from equipment 1380) to accessing dress for storing data The device (for example, equipment interface 1372) for the first request (for example, first request 1376) set.This device further includes for depositing The first authentic copy (for example, first authentic copy 1384) of associated with the device for storing data control table of storage part (for example, Part 1340) device (for example, volatile memory 1344).This device further includes for executing control in response to the first request First update of the part of the first authentic copy of tabulation initiates control for being updated based on first at device for storing data The second of the triplicate of table updates and for being performed in parallel with second update to accessing dress for storing data The device (for example, controller 1330) for the second request (for example, second request 1378) set.In illustrated examples, this dress It further includes device (example for the newer part of the first authentic copy of control table to be supplied to device for storing data to set Such as, memory interface 1332).

Although the various assemblies described herein are shown as block assembly and are described with general terms, it is the component that May include being configured such that such component is able to carry out the one or more micro- of one or more operations described herein Processor, state machine or other circuits.For example, the one or more aspects of controller 130,430 and 1330 can indicate physics Component, such as hardware control, state machine, logic circuit or other structures, so that controller 130,430 and 1330 is able to carry out Non-blocking operation.

Alternatively or in addition, some aspects of data storage device 102,402 and 1302 can use microprocessor Or microcontroller is implemented.In a particular embodiment, the one or more aspects of controller 130,430 and 1330 can use fortune Row is stored in the processor of the instruction (for example, firmware) at nonvolatile memory 104,404 and 1304 to implement.Alternatively Ground, or extraly, by processor operation can operating instruction can be stored in not be nonvolatile memory 104,404 and At the memory location of the separation of 1304 part, such as in it can be included in controller 130,430 and 1330 It reads at memory (ROM).

Data storage device 102,402 and 1302 can be coupled, be attached to or be embedded into one or more access equipments It is interior, such as in the shell of equipment 180.For example, data storage device 102,402 and 1302 can be according to combined electronics assembly work The journey committee (Joint Electron Devices Engineering Council, JEDEC) general sudden strain of a muscle of solid state technology association (Solid State Technology Association Universal Flash Storage, UFS) configuration is deposited to be embedded into In equipment 180,480 and 1380.In order to further illustrate data storage device 102,402 and 1302 can be integrated in electricity In sub- equipment (for example, equipment 180 or equipment 480), such as mobile phone, computer are (for example, laptop computer, tablet meter Calculation machine or laptop), music player, video player, game station or operation console, E-book reader, a number Word assistant (personal digital assistant, PDA), portable navigation device are stored using internal non-volatile The miscellaneous equipment of device.

In one or more of the other embodiment, data storage device 102,402 and 1302 can be configured as selecting Selecting property it is coupled in the portable device of one or more external equipments (such as host equipment) and implements.For example, data store Equipment 102,402 and 1302 can be from equipment 180,480 and 1380 (that is, " removedly " being coupled to equipment 180,480 and 1380) it removes.As an example, data storage device 102,402 and 1302 can be according to removable universal serial bus (universal serial bus, USB) configuration is removably coupled to equipment 180,480 and 1380.

Equipment 180,480 and 1380 can correspond to mobile phone, computer (for example, laptop computer, tablet calculate Machine or notebook computer), music player, video player, game station or operation console, E-book reader, a number Word assistant (PDA), portable navigating device, another electronic equipment, or combinations thereof.Equipment 180,480 and 1380 can be via control Device processed is communicated, and equipment 180,480 and 1380 can be enable to be led to data storage device 102,402 and 1302 Letter.Equipment 180,480 and 1380 can be in accordance with JEDEC solid state technologies association industry standard, such as embedded multi-media card (MultiMedia Card, eMMC) specification or generic flash memory (Universal FlashStorage, UFS) host control Device interface specification processed.As illustrated examples, equipment 180,480 and 1380 can be in accordance with one or more of the other specification (such as Secure digital (Secure Digital, SD) host controller specification) it is operated.Alternatively, equipment 180,480 and 1380 It can be communicated with data storage device 102,402 and 1302 according to another communication protocol.In some embodiments, as Illustrated examples, data storage device 102,402 and 1302 can be integrated in the data-storage system of network-accessible (such as Enterprise data system, NAS system or cloud data-storage system) in.

In some embodiments, one or two of data storage device 102,402 and 1302 may include solid-state Driver (solid state drive, SSD).Illustratively, unrestricted example, data storage device 102,402 With one or two of 1302 may be used as embedded memory driver (for example, embedded SSD drive of mobile device), Enterprise's memory driver (enterprise storage drive, ESD), cloud storage equipment, network attached storage (network- Attached storage, NAS) equipment or client storage device).In some embodiments, data storage device 102, One or two of 402 and 1302 can be coupled to equipment 180,480 and 1380 via network.For example, network can wrap Include data center's storage system network, enterprise storage system network, storage area network, cloud storage network, LAN (local Area network, LAN), wide area network (wide area network, WAN), internet, and/or other networks.

In order to further illustrate as illustrated examples, one or two of data storage device 102,402 and 1302 Can be configured as be coupled to equipment 180,480 and 1380 be used as in-line memory, such as with embedded multi-media card () (trade mark of the JEDEC solid state technologies association of Virginia Arlington) configuration.Data storage device 102,402 EMMC equipment is can correspond to one or two of 1302.As another example, data storage device 102,402 and 1302 One or two of can correspond to memory card, such as secure digital () card,Card, miniSD^TM Block (trade mark of Wilmington, DE SD-3C LLC), MultiMediaCard^TM(MMC^TM) card (Virginia A Ling The trade mark for the JEDEC solid state technologies association paused) or(CF) card (California Mir's Pitta this The trade mark of SanDisk Corporation).One or two of data storage device 102,402 and 1302 can be advised in accordance with JEDEC industries Model is operated.For example, data storage device 102,402 and 1302 can be in accordance with JEDEC eMMC specifications, JEDEC Common Flash Memories Memory (UFS) specification, one or more of the other specification, or combinations thereof operated.

Nonvolatile memory 104,404 and 1304 may include resistive random access memory (ReRAM), flash memory Reservoir is (for example, nand memory, NOR memories, single stage unit (SLC) flash memory, multi-level unit (MLC) flash Device, lane place line NOR (divided bit-line NOR, DINOR) memory, AND memories, high capacitance coupling ratio (high Capacitive coupling ratio, HiCR) equipment, asymmetric non-contact transistor (asymmetrical Contactless transistor, ACT) equipment or another flash memory), Erasable Programmable Read Only Memory EPROM (EPROM), electricity Erasable Programmable Read Only Memory EPROM (EEPROM), read-only memory (ROM), disposable programmable memory (one-time Programmable memory, OTP), another type of memory, or combinations thereof.Nonvolatile memory 104,404 and 1304 may include semiconductor memory apparatus.

Semiconductor memory devices include volatile memory devices (such as dynamic random access memory (dynamic Random access memory, " DRAM ") or static RAM (static random access memory, " SRAM ") equipment), (such as resistive random access memory (" ReRAM "), reluctance type are random for non-volatile memory devices Access that memory (magnetoresistive random access memory, " MRAM "), electrically erasable is read-only deposits Reservoir (electrically erasable programmable read only memory, " EEPROM "), flash memory (it can also be considered as the subset of EEPROM), ferroelectric RAM (ferroelectric random access Memory, " FRAM ") and can store other semiconductor elements of information.Each type of storage device can have not Same configuration.For example, flash memory device can be configured with NAND or NOR to configure.

Memory devices can be formed by passive and/or active component with any combinations.It is passive as non-limiting example Semiconductor memery device includes ReRAM equipment components, includes antifuse, phase-change material etc. in some embodiments Resistivity switches memory element, and the steering component (steering element) for optionally including diode etc..Separately Outside, as non-limiting example, active semi-conductor memory component includes EEPROM and flash memory device element, at some In embodiment, flash memory device element includes the element for including charged region, and such as floating boom, conductive nano-particles or charge are deposited Store up dielectric material.

Multiple memory components are configured such that they are connected in series with or make each element individually accessible. As non-limiting example, the flash memory device in NAND configurations (nand memory) generally comprises the storage being connected in series with Device element.NAND memory array is configured such that array is made of multiple memory strings, wherein going here and there by shared single Multiple memory components of bit line are constituted and are accessed as one group.Alternatively, memory component, which can be configured as, makes It is individually addressable to obtain each element, for example, NOR memory arrays.The configuration of NAND and NOR memories is exemplary, And memory component can be otherwise configured to.

In substrate and/or the semiconductor memery device of top can be deposited with two dimension or three dimensional arrangement, such as two dimension Reservoir structures or three-dimensional memory structure.In two dimensional memory structure, semiconductor memery device is disposed in single plane Or in single memory devices grade.Normally, in two dimensional memory structure, memory component, which is disposed in, to be substantially parallel to The plane (for example, in x-z direction planes) for supporting the main surface of the substrate of memory component to extend.Substrate can be on it Or in which the wafer of the layer of memory element is formed, or can be the carrier that memory element is attached to after memory element is formed Substrate.As non-limiting example, substrate may include the semiconductor of such as silicon.

Memory component can be arranged in single memory devices grade (such as with multiple rows and/or row) according to oldered array In.However, memory component can be arranged with irregular or nonopiate configuration.Memory component can each have there are two or Multiple electrodes or contact line, such as bit line and wordline.

3 D memory array is arranged such that memory component occupies multiple planes or multiple memory devices grades, from And three-dimensional structure is formed (that is, in the x, y and z directions, wherein the directions y are essentially perpendicular to the main surface of substrate, and x and z Direction is basically parallel to the main surface of substrate).As non-limiting example, three-dimensional memory structure can be vertically arranged for The stacking of multiple two dimensional memory device levels.As another non-limiting example, 3 D memory array can be arranged Multiple vertical rows (for example, being essentially perpendicular to the main surface of substrate, i.e., in y-direction), wherein each row have in each row In multiple memory components.Row can be arranged with two-dimensional arrangement (for example, in x-z-plane) so that memory component Three dimensional arrangement has the element on the memory plane of multiple vertical stackings.The other configurations of three-dimensional storage element can also Constitute 3 D memory array.

As unrestricted example, in three dimensional NAND memory array, memory component can be coupled together To form the NAND string in single horizontal plane (for example, x-z) memory devices grade.Alternatively, memory component can be by coupling It is combined to form the vertical nand string across multiple horizontal plane memory devices grades.Other three-dimensional configurations can be envisioned, In some NAND strings include single storage level in memory component, and it is other string comprising across multiple storage levels storage Device element.It can also be configured with NOR and ReRAM configure to design 3 D memory array.

Normally, in monolithic three dimensional memory array, one or more memory devices are formed above single substrate Grade.Optionally, monolithic three dimensional memory array can also have one or more storages at least partly in single substrate Device layer.As non-limiting examples, substrate may include the semiconductor of such as silicon.In monolithic three dimensional array, forming array The layer of each memory devices grade is generally formed on the layer of bottom memory devices grade of array.However, monolithic three dimensional stores The layer of the adjacent memory device grade of device array can be shared or have between memory devices grade middle layer.

Alternatively, it is possible to be formed separately two-dimensional array, it is then encapsulated in together to be formed with Multilayer Memory Non- monolithic memory equipment.For example, can be by forming storage level on separate substrates and then by storage level heap Top of each other is stacked in build non-monolithic stacked memory.Substrate can be thinned or be gone from memory devices grade before stacking It removes, but when memory device grade originally forms on separate substrates, obtained memory array is not that monolithic three dimensional is deposited Memory array.In addition, multiple two dimensional memory arrays or 3 D memory array (monolithic or non-monolithic) can be formed on point From chip on, be then enclosed in together to form the memory devices of stacked chips.

The operation of memory component and usually require interlock circuit with the communication of memory component.Show as non-limiting Example, memory devices can have for controlling and driving memory component to complete the electricity for the function of such as programming and read Road.This interlock circuit can on substrate identical with memory component and/or on separate substrates.For example, for storing The controller of device read-write operation can be located on the controller chip of separation and/or positioned at identical with memory component On substrate.

It would be recognized by those skilled in the art that the present disclosure is not limited to described two and three dimensions example arrangements, but All correlations being covered in spirit and scope of the present disclosure as described herein and as understood by those skilled in the art are deposited Reservoir structures.Embodiment described herein illustration be intended to provide general understanding to various embodiments.It can be from the disclosure Using and derive other embodiments so that can make without departing from the scope of the disclosure structure and logic It replaces and changes.The disclosure is intended to cover any and all subsequent adaptations or variation of various embodiments.People in the art Member is it will be recognized that such modification is within the scope of this disclosure.

Theme disclosed above will be considered being exemplary rather than it is restrictive, and appended claims intention cover Lid falls into all such modifications, enhancing and other embodiments of the scope of the present disclosure.Therefore, the permitted maximum of law is arrived Degree, the scope of the present invention will be by determining the widest permissible explanation of the following claims and their equivalents, and not It should be restricted or limited by the foregoing detailed description.

Claims

1. a kind of device, including：

Nonvolatile memory；With

Controller is coupled to the nonvolatile memory, and the controller includes volatile memory, wherein the control Device is configured as executing the non-obstructive root canal simultaneously operating of separation and non-obstruction union operation.

2. the apparatus according to claim 1, wherein the non-obstruction union operation includes melting address conversion modification data In the cache part for closing the address translation table at the volatile memory, without blocking to the non-volatile memories The write operation of device.

3. the apparatus according to claim 1, wherein the non-obstructive root canal simultaneously operating includes that will control information from described Volatile memory copies to the nonvolatile memory, without blocking the write operation to the nonvolatile memory.

4. the apparatus according to claim 1, wherein the controller is additionally configured to be wanted according to the update step state of filling up It is asking, the non-obstruction union operation is asynchronously executed with different rates relative to the non-obstructive root canal simultaneously operating.

5. the apparatus according to claim 1, wherein the non-obstruction union operation is atomic operation, the atomic operation packet It includes U- layers of address translation table CAT for concurrently evacuating and being compressed to the cache in the volatile memory of update step.

6. device according to claim 5, wherein the controller is additionally configured to be written in newer m- set While the nonvolatile memory, the update to U- layer and CAT in the volatile memory is continued to execute.

7. the apparatus according to claim 1, wherein the controller be additionally configured to the non-obstruction union operation and Non- obstructive root canal simultaneously operating concurrently continues to execute the host write operation to the nonvolatile memory.

8. the apparatus according to claim 1, wherein the controller is additionally configured to：Using barrier command in next non-resistance Update includes the daily record for the pointer for being directed toward new newer m- set and is stored in the daily record in plug control simultaneously operating In the nonvolatile memory.

9. the apparatus according to claim 1, wherein the controller is additionally configured to：In abnormal shutdown UGSD events In the case of, it will be controlled according to the daily record finally stored synchronized from the non-obstructive root canal finally stored in the nonvolatile memory Tabulation rollback is simultaneously restored to the volatile memory, and in this case, via the controller U- layers described It loses and is ignored with the recent renewal executed in CAT, without losing consistency.

10. a kind of device, including：

Nonvolatile memory；With

Controller, is coupled to the nonvolatile memory, and the controller includes：

Interface is configured as receiving the first request to accessing the nonvolatile memory from access equipment；With

Volatile memory is configured as storing the first authentic copy of control structure associated with the nonvolatile memory,

The wherein described controller is additionally configured to：It is executed to the first authentic copy of the control structure in response to first request Partial first is updated, is initiated to the second of the control structure at the nonvolatile memory based on first update The second of copy updates and concurrently runs the second request to accessing the nonvolatile memory with the second update.

11. device according to claim 10, wherein the control structure includes control table, and the wherein described control knot The triplicate of the control structure is being changed with before indicating logic to physics L2P address conversions in the part of the first authentic copy of structure Indicate L2P address conversions.

12. device according to claim 10, wherein the part includes the update for multiple lists that there is address to change Data structure, each list in the multiple list correspond to the different sets of logical block address LBA.

13. a kind of method, including：

The first request is received to execute the to the nonvolatile memory of first equipment from the second equipment by the first equipment One write operation；

In response to executing first write operation, the control to being stored at the volatile memory of first equipment is executed First update of the part of the first authentic copy of table；

The second update to the triplicate of the control table is executed at the nonvolatile memory with will be to described first The modification of copy travels to the triplicate；With

The second reproducting periods is being executed, the second write operation to the nonvolatile memory is executed.

14. according to the method for claim 13, wherein in response to detecting that the quantity of the modification meets threshold value and executes Second update, and further include being incremented by the quantity in response to executing first write operation.

15. further including according to the method for claim 13, executing to control simultaneously operating to update independently with described second The control table is copied into the nonvolatile memory.

16. the method according to claim 11 further includes the pointer in the update control table to indicate the control table Position of the newer triplicate in the nonvolatile memory, the newer triplicate instruction of the control table patrols Collect at least part to physics L2P mapping tables.

17. a kind of device, including：

Device for storing data；

Device for receiving the first request to accessing device for storing data from access equipment；

The device of the part of the first authentic copy for storing control table associated with device for storing data；With

It is updated, to the first of the part of the first authentic copy of the control table for being based on for being executed in response to first request First update is initiated at device for storing data to the second update of the triplicate of the control table, Yi Jiyong In the device for being performed in parallel the second request to accessing device for storing data with second update.

18. device according to claim 17, wherein device for storing data is configurable for non-volatile number According to storage, wherein the device of the part for storing the first authentic copy is configurable for volatile data storage, and also It include the device for the newer part of the first authentic copy of the control table to be supplied to device for storing data.

19. a kind of device, including：

Nonvolatile memory；With

Controller is coupled to the nonvolatile memory, and the controller includes volatile memory, wherein the control Device is configured as executing non-obstructive root canal simultaneously operating, and the wherein described controller is additionally configured to relative to the non-obstruction Control simultaneously operating asynchronously executes non-obstruction union operation.

20. device according to claim 19, wherein the non-obstruction union operation is atomic operation, the atomic operation Include update step is concurrently evacuated and is compressed to the address translation table of the cache in the volatile memory, and its Described in controller be configured as being performed in parallel host to the nonvolatile memory with the non-obstruction union operation Write operation.