CN112527698B - Processing method, device and equipment - Google Patents
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- 230000015654 memory Effects 0.000 claims abstract description 401
- 230000002093 peripheral effect Effects 0.000 claims abstract description 188
- 230000007717 exclusion Effects 0.000 claims abstract description 106
- 238000013507 mapping Methods 0.000 claims abstract description 41
- 238000012545 processing Methods 0.000 claims abstract description 27
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- 238000004590 computer program Methods 0.000 claims description 17
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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Abstract
The application provides a processing method, which comprises the following steps: if the input/output memory management unit is configured with a first memory exclusion range of a register, establishing a mapping relation between the second memory exclusion range of the register and the second peripheral equipment based on the second memory exclusion range of the second peripheral equipment in a page table of the input/output memory management unit, wherein addresses of the second memory exclusion range of the register and addresses of the second memory exclusion range of the second peripheral equipment are in one-to-one correspondence; the input/output memory management unit page table is used for responding to the memory access request of the second peripheral device, so that the second peripheral device accesses to the target memory address. Meanwhile, the application also provides a processing device and processing equipment.
Description
Technical Field
The present disclosure relates to a setting technology for excluding a memory range, and in particular, to a processing method, apparatus, and device.
Background
In direct memory access (DMA, direct Memory Access) or translation of Input/Output (IO) addresses by Input/Output memory management unit (IOMMU, input/Output Memory Management Unit) hardware, only one exclusive memory range register can be configured, meaning that it only supports one exclusive memory range defined by one peripheral. When there are multiple excluded memory ranges defined by multiple peripheral devices under the same IOMMU hardware, the problem of memory access failure occurs.
Disclosure of Invention
In view of this, it is desirable in one aspect of the present application to provide a processing method comprising: if the input/output memory management unit is configured with a first memory exclusion range of a register, establishing a mapping relation between the second memory exclusion range of the register and the second peripheral equipment based on the second memory exclusion range of the second peripheral equipment in a page table of the input/output memory management unit, wherein addresses of the second memory exclusion range of the register and addresses of the second memory exclusion range of the second peripheral equipment are in one-to-one correspondence;
the input/output memory management unit page table is used for responding to the memory access request of the second peripheral device, so that the second peripheral device accesses to the target memory address.
In the above scheme, the method further comprises:
if a memory access request sent by the second peripheral device is received, searching an input/output memory management unit page table corresponding to the second peripheral device based on a device identifier carried in the memory access request, so as to obtain a target memory address to be accessed by the second peripheral device.
In the above scheme, the addresses of the first excluded memory range of the register and the addresses of the first excluded memory range of the first peripheral device are in one-to-one correspondence;
and the page table of the input/output memory management unit only stores mapping relations of the exclusion ranges of other peripheral devices and registers except the mapping relation of the first peripheral device and the first exclusion memory range of the register.
In the above scheme, the method further comprises:
and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to the second excluded memory range of the second peripheral device.
In the above solution, before determining whether the input/output memory management unit configures the excluded memory range of the register, the method further includes:
in the starting-up process, inquiring the memory exclusion range corresponding to each peripheral device in an input/output memory management unit description table of the advanced configuration and power management interface;
if the search result has the memory exclusion range corresponding to the peripheral equipment, configuring the memory exclusion range of the register based on the memory exclusion range of the first peripheral equipment searched in the search result.
In the above scheme, the method further comprises:
and in the starting process, acquiring the page table of the input/output memory management unit for representing the mapping relation between the excluded memory range and the equipment identifier.
According to another aspect of the present application, there is provided a processing apparatus including:
the judging unit is used for judging whether the input/output memory management unit is configured with the memory exclusion range of the register;
the device comprises an input/output memory management unit, a setting unit and a mapping unit, wherein the input/output memory management unit is used for setting a first memory exclusion range of a register, setting a mapping relation between the second memory exclusion range of the register and a second peripheral device based on the second memory exclusion range of the second peripheral device in a page table of the input/output memory management unit, and enabling addresses of the second memory exclusion range of the register and addresses of the second memory exclusion range of the second peripheral device to be in one-to-one correspondence; the input/output memory management unit page table is used for responding to the memory access request of the second peripheral device, so that the second peripheral device accesses to the target memory address.
In the above scheme, the method further comprises:
and the searching unit is used for searching an input/output memory management unit page table corresponding to the second peripheral device based on the device identifier carried in the memory access request if the memory access request sent by the second peripheral device is received, so as to obtain a target memory address to be accessed by the second peripheral device.
In the above scheme, the addresses of the first excluded memory range of the register and the addresses of the first excluded memory range of the first peripheral device are in one-to-one correspondence;
and the page table of the input/output memory management unit only stores mapping relations of the exclusion ranges of other peripheral devices and registers except the mapping relation of the first peripheral device and the first exclusion memory range of the register.
According to a third aspect of the present application, there is provided a processing apparatus comprising: comprising the following steps: a processor and a memory for storing a computer program capable of running on the processor,
wherein the processor is configured to execute the steps of any of the above-described processing methods when the computer program is run.
According to the processing method, the processing device and the processing equipment, whether the memory exclusion range of the register is configured by the input/output memory management unit is judged, and under the condition that the first memory exclusion range of the register is configured by the input/output memory management unit, the mapping relation between the second memory exclusion range of the register and the second peripheral equipment is established in the page table of the input/output memory management unit based on the second memory exclusion range of the second peripheral equipment, wherein the addresses of the second memory exclusion range of the register and the addresses of the second memory exclusion range of the second peripheral equipment are in one-to-one correspondence; and in the subsequent processing process, responding to the memory access request of the second peripheral equipment by using the input/output memory management unit page table so as to enable the second peripheral equipment to access the target memory address. Thus, under the condition that the input/output memory management unit configures the memory exclusion range of the register, the mapping table representing the mapping relation between the memory exclusion range and the peripheral equipment is utilized to respond to the memory access request of other peripheral equipment, and the register can be supported to correspond to a plurality of memory exclusion ranges of a plurality of peripheral equipment so as to realize that the plurality of peripheral equipment can simultaneously carry out memory access.
Drawings
FIG. 1 is a schematic flow chart of a treatment method in the present application;
FIG. 2 is a schematic diagram of the configuration of the IOMMU page table in the present application;
FIG. 3 is a second flow chart of the treatment method of the present application;
FIG. 4 is a schematic diagram showing the structural components of the treatment device of the present application;
fig. 5 is a schematic diagram of the structural composition of the processing apparatus in the present application.
Detailed Description
The technical scheme of the application is further elaborated below with reference to the drawings in the specification and the specific embodiments.
Fig. 1 is a schematic flow chart of a processing method in the present application, as shown in fig. 1, the method includes:
step 101, if the input/output memory management unit configures a first excluded memory range of a register, establishing a mapping relationship between the second excluded memory range of the register and the second peripheral device based on the second excluded memory range of the second peripheral device in a page table of the input/output memory management unit, wherein addresses of the second excluded memory range of the register and addresses of the second excluded memory range of the second peripheral device are in one-to-one correspondence; the input/output memory management unit page table is used for responding to the memory access request of the second peripheral device, so that the second peripheral device accesses to the target memory address.
In this application, the method is mainly applied to an electronic device with a storage function, in which an Input/output memory management unit (IOMMU, input/Output Memory Management Unit) is configured, and the IOMMU has a memory range register. In the starting-up process of the electronic equipment, an input/output memory management unit description table of an advanced configuration and power management interface (ACPI, advanced Configuration and Power Management Interface) is generated through a unified extensible firmware interface (UEFI, unified Extensible Firmware Interface) or a basic input/output system (BIOS, basic Input Output System), and in the starting-up process, an IOMMU driver can inquire the excluded memory range corresponding to each peripheral equipment in the ACPI description table and obtain a searching result; if the search result has at least one memory exclusion range corresponding to the peripheral device, the IOMMU driver in the electronic device configures the memory exclusion range of the memory exclusion range register based on the memory exclusion range of the first peripheral device found first in the search result.
Here, the memory range configuration of the memory range register mainly depends on whether or not a memory exclusion range is defined in the IOMMU system specification of the chip vendor. If the memory exclusion range is not defined in the IOMMU system plan, the IOMMU driver does not configure the memory exclusion range of the memory range register for the peripheral, and if the memory exclusion range is defined in the IOMMU system specification, the IOMMU driver sets the memory exclusion range of the memory range register according to the memory exclusion range defined in the system specification.
In the present application, when the IOMMU driver searches the memory exclusion ranges of the peripheral devices in the ACPI input/output memory management unit description table, if the search result has the memory exclusion ranges corresponding to the peripheral devices, the memory exclusion ranges corresponding to the peripheral devices may exist in the form of a table or a list.
In this application, IOMMU hardware is mainly used to map virtual memory addresses to physical memory addresses, so that peripheral devices can work in a virtual memory environment. For example, the peripheral devices may be a disk array controller (RAID controller) and a Network adapter (Network adapter). When the peripheral device performs memory addressing in the virtual memory of the electronic device, the IOMMU hardware may search for a physical memory address corresponding to the peripheral device within a memory exclusion range of a memory range register, and if the memory address to be translated by the peripheral device is within the memory exclusion range of the register, the IOMMU hardware does not perform any address translation. For example, device 1 accesses memory address 'a', and if address 'a' is within the memory range of this register, the IOMMU hardware will not make any address translations while passing through the IOMMU hardware, i.e., the register will read memory with address 'a'. Thus, the overhead of IOMMU hardware address translation can be eliminated.
In this application, the IOMMU hardware maintains an IOMMU page table that characterizes the mapping between peripheral devices and memory ranges. When the first excluded memory range is configured in the memory range register, if there is another excluded memory range of the peripheral device in the ACPI description table, the IOMMU driver obtains an IOMMU page table representing a mapping relationship between the excluded memory range and the device identifier during a power-on process, and maps the excluded memory range of the other peripheral device and the device identifier of the peripheral device to the IOMMU page table, so as to establish a second excluded memory range and a third excluded memory range … … N excluded memory range of the memory range register in the IOMMU page table.
Here, each IOMMU page table corresponds to a peripheral device, and in the IOMMU page table, a mapping relationship that characterizes a device identifier of the peripheral device and a memory exclusion range of the peripheral device is stored, wherein in the IOMMU page table, a physical address of the memory exclusion range register and a virtual address of the memory exclusion range of the peripheral device are in an exclusive one-to-one correspondence. For example, address "A" corresponds to an address "A", and the target memory address of the target peripheral device can be conveniently found from the IOMMU table through one-to-one address mapping.
Here, if the excluded memory range of the memory range register configuration corresponds to the first peripheral device, the physical address of the first excluded memory range of the memory range register and the virtual address of the first excluded memory range of the first peripheral device are in exclusive one-to-one correspondence, and only the mapping relationship of the excluded ranges of the other peripheral devices and registers other than the mapping relationship of the first peripheral device and the first excluded memory range of the memory range register is stored in the IOMMU page table. Thus, when the peripheral device accesses the memory, the device system can know from which channel the target memory address is currently acquired.
In this application, the IOMMU driver, when configuring the IOMMU page table, specifically, configures each entry of the IOMMU page table based on the excluded memory range of the peripheral. For example, as shown in fig. 2, taking a three-level input/output (I/O) page table and a 4K physical page as an example, assuming that the memory range occupies 8K, finding out the index value of the first layer page table according to the content value of the physical address of the client, and configuring each page directory entry corresponding to each index value, where the page directory entry points to the address of the next layer I/O page table.
Here, each peripheral corresponds to one IOMMU page table. Each IOMMU page table has system physical addresses for multiple levels of page tables.
In the application, when a first peripheral accesses a memory of the electronic device, the electronic device receives a memory access request of the first peripheral, if an IOMMU driver of the electronic device queries that a memory range register of the IOMMU configures an excluded memory range of the first peripheral, when the electronic device receives the memory access request of the first peripheral, IOMMU hardware in the electronic device searches a target memory address to be accessed by the first peripheral based on the excluded memory range of the memory range register.
In the application, when a second peripheral accesses a memory of the electronic device, the electronic device receives a memory access request of the second peripheral, if the IOMMU hardware of the electronic device queries that a memory range register of the IOMMU configures an excluded memory range, when the electronic device receives the memory access request of the second peripheral, the IOMMU hardware in the electronic device searches an IOMMU page table corresponding to the second peripheral based on a device identifier carried in the memory access request, and obtains a target memory address to be accessed corresponding to the second peripheral based on a mapping relationship between the device identifier and the excluded memory range in the IOMMU page table corresponding to the second peripheral. In this way, it is ensured that a plurality of peripheral devices can function properly without any system failure. Such that the range register supports a plurality of excluded memory ranges defined by a plurality of peripheral devices.
In the present application, if the memory range register of the IOMMU hardware is found to have not configured an excluded memory range of the peripheral device during the device power-on process, the IOMMU driver may configure the excluded memory range of the memory range register according to the excluded memory range of the peripheral device.
For example, if the IOMMU finds that the memory range register does not configure the excluded memory range of the peripheral device, and the excluded memory range is defined by the second peripheral device in the ACPI description table, and the second peripheral device is the first found peripheral device in the ACPI description table, the IOMMU configures the memory range register based on the excluded memory range of the second peripheral device.
Here, the physical address of the excluded memory range of the configured memory range register and the virtual address of the excluded memory range of the second peripheral device are in an exclusive one-to-one correspondence.
In this application, the exclusion range register is used to inform the IOMMU hardware that address "A" is not to be used for address translation (i.e., the I/O page table is not to be looked up for the corresponding physical address) if it is retrieved.
Here, no address conversion is performed, representing an exclusive one-to-one address correspondence (e.g., address a—address a). However, if two PCIe devices define their own excluded memory ranges, this means that the excluded memory ranges of one PCIe device are covered (i.e., the excluded memory ranges of the excluded range register configuration of the IOMMU hardware are covered). Therefore, one-to-one I/O page tables must be prepared for the covered excluded memory range in order for the IOMMU hardware to find the corresponding address via the page table. Such as in fig. 2: guest Physical Address (client physical address) = 0x9f459000,System Physical Address (system physical address) =0x9f 459000.
Fig. 3 is a second flow chart of the processing method in the present application, as shown in fig. 3, including:
step 301, retrieving the excluded memory range of the corresponding peripheral device in the ACPI description table.
That is, during system power-up, the IOMMU driver retrieves the excluded memory range of the corresponding external device in the ACPI description table. This ACPI description table is automatically generated by the UEFI/BIOS during system boot.
Step 302, determine if the corresponding peripheral defines its own excluded memory range?
Here, this step is also performed during the system power-on process. The specific definition depends on whether the IOMMU system specification of the chip vendor has a configuration that excludes memory ranges. If the peripheral device defines its own excluded memory range, step 303 is performed, and if the peripheral device does not define an excluded memory range, step 305 is performed.
In step 303, it is determined whether the memory range register is configured.
Here, this step is also performed during the system power-on process. When the system specification of the peripheral device in the ACPI description table defines the excluded memory range, the IOMMU driver sets the excluded memory range of the memory range register according to the first found system specification of the peripheral device in the ACPI description table. If the peripheral does not define an excluded memory range, the IOMMU driver does not set the excluded memory range of the memory range register.
If the memory range register is already configured, step 304 is performed, and if the memory range register is not already configured, step 306 is performed.
Step 304, lookup the IOMMU page table associated with the peripheral.
Here, this step is also performed during the power-on process. The IOMMU driver would maintain IOMMU page tables.
In step 305, IOMMU page tables are configured for the identification map based on the retrieved excluded memory range.
Here, one IOMMU page table corresponds to one peripheral device, and the IOMMU page table stores therein the mapping relationship of peripheral devices other than the peripheral device corresponding to the excluded memory range that the range register has been configured and the excluded memory addresses of the other peripheral devices, wherein the addresses of the excluded memory range stored in the IOMMU page and the excluded memory addresses of the peripheral devices are in exclusive one-to-one correspondence. So that the system finds the target memory address of the target peripheral in the IOMMU page table.
Step 306, configuring a memory range register according to the retrieved excluded memory range.
Here, when the memory range register is not configured, the memory range register is configured with the excluded memory range of the first searched peripheral device in the ACPI description table.
In the scheme of the application, under the condition of a plurality of peripheral devices, if the memory range register of the IOMMU is configured, the excluded memory range and the device identification of other peripheral devices are mapped in the IOMMU page table so as to respond to the memory access request of the other peripheral devices by utilizing the IOMMU page table, thus the normal operation of the plurality of peripheral devices is not influenced, and the system fault is not generated.
Fig. 4 is a schematic structural diagram of a processing apparatus according to the present application, as shown in fig. 4, including:
a judging unit 401, configured to judge whether the input/output memory management unit configures an excluded memory range of the register;
a building unit 402, configured to build, in a case where the memory management unit configures a first excluded memory range of a register, a mapping relationship between the second excluded memory range of the register and a second peripheral device based on the second excluded memory range of the second peripheral device in an input/output memory management unit page table, where addresses of the second excluded memory range of the register and addresses of the second excluded memory range of the second peripheral device are in one-to-one correspondence; the input/output memory management unit page table is used for responding to the memory access request of the second peripheral device, so that the second peripheral device accesses to the target memory address.
Here, the i/o memory management unit page table characterizes a mapping relationship between the excluded memory range and the device identifier, where the i/o memory management unit page table is acquired during the device boot process.
Here, the apparatus further includes: a search unit 403;
the lookup unit 403 is configured to, if a memory access request sent by the second peripheral device is received, lookup an i/o memory management unit page table corresponding to the second peripheral device based on a device identifier carried in the memory access request, so as to obtain a target memory address to be accessed by the second peripheral device.
Here, the addresses of the first excluded memory range of the register and the addresses of the first excluded memory range of the first peripheral device are in one-to-one correspondence; and the page table of the input/output memory management unit only stores mapping relations of the exclusion ranges of other peripheral devices and registers except the mapping relation of the first peripheral device and the first exclusion memory range of the register.
Here, the lookup unit 403 is further configured to query, in the i/o memory management unit description table of the advanced configuration and power management interface, the excluded memory range corresponding to each peripheral device during the device power-on process.
Here, the apparatus further includes: a configuration unit 404;
specifically, if the lookup result has the excluded memory range corresponding to the peripheral device, the configuration unit 404 configures the excluded memory range of the register based on the excluded memory range of the first peripheral device found in the lookup result.
And the memory exclusion range of the register is configured according to the second memory exclusion range of the second peripheral device if the memory exclusion range of the register is not configured by the input/output memory management unit.
At this time, the second peripheral device may refer to the first peripheral device that is found in the ACPI description table and defines the excluded memory range.
It should be noted that: in the processing device provided in the above embodiment, when information is reminded, only the division of each program module is used for illustration, in practical application, the processing allocation may be completed by different program modules according to needs, that is, the internal structure of the device is divided into different program modules, so as to complete all or part of the processing described above. In addition, the processing device and the processing method provided in the foregoing embodiments belong to the same concept, and specific implementation processes of the processing device and the processing method are detailed in the method embodiments and are not described herein again.
The embodiment of the application also provides a processing device, which comprises: a processor and a memory for storing a computer program capable of running on the processor,
wherein the processor, when executing the computer program, performs: if the input/output memory management unit is configured with a first memory exclusion range of a register, establishing a mapping relation between the second memory exclusion range of the register and the second peripheral equipment based on the second memory exclusion range of the second peripheral equipment in a page table of the input/output memory management unit, wherein addresses of the second memory exclusion range of the register and addresses of the second memory exclusion range of the second peripheral equipment are in one-to-one correspondence;
the input/output memory management unit page table is used for responding to the memory access request of the second peripheral device, so that the second peripheral device accesses to the target memory address.
The processor is further configured to execute, when the computer program is executed: if a memory access request sent by the second peripheral device is received, searching an input/output memory management unit page table corresponding to the second peripheral device based on a device identifier carried in the memory access request, so as to obtain a target memory address to be accessed by the second peripheral device.
The addresses of the first memory exclusion range of the register and the addresses of the first memory exclusion range of the first peripheral device are in one-to-one correspondence;
and the page table of the input/output memory management unit only stores mapping relations of the exclusion ranges of other peripheral devices and registers except the mapping relation of the first peripheral device and the first exclusion memory range of the register.
The processor is further configured to execute, when the computer program is executed: and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to the second excluded memory range of the second peripheral device.
The processor is further configured to execute, when the computer program is executed: in the starting-up process, the page table of the advanced configuration and power management interface is used for inquiring the memory exclusion range corresponding to each peripheral device;
if the search result has the memory exclusion range corresponding to the peripheral equipment, configuring the memory exclusion range of the register based on the memory exclusion range of the first peripheral equipment searched in the search result.
The processor is further configured to execute, when the computer program is executed: and in the starting process, acquiring the page table of the input/output memory management unit for representing the mapping relation between the excluded memory range and the equipment identifier.
Fig. 5 is a schematic diagram showing the structural components of a processing device 500 in the present application, which may be a mobile phone, a computer, a digital broadcasting terminal, an information transceiver device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc. The processing apparatus 500 shown in fig. 5 includes: at least one processor 501, memory 502, at least one network interface 504, and a user interface 503. The various components in processing device 500 are coupled together by bus system 505. It is understood that bus system 505 is used to enable connected communications between these components. The bus system 505 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various buses are labeled as bus system 505 in fig. 5.
The user interface 503 may include, among other things, a display, keyboard, mouse, trackball, click wheel, keys, buttons, touch pad, or touch screen, etc.
It is to be appreciated that memory 502 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 502 described in embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 502 in the present embodiment is used to store various types of data to support the operation of the processing device 500. Examples of such data include: any computer programs for operation on the processing device 500, such as an operating system 5021 and application 5022; contact data; telephone book data; a message; a picture; video, etc. The operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application programs 7022 may include various application programs such as a Media Player (Media Player), a Browser (Browser), and the like for implementing various application services. A program for implementing the method of the embodiment of the present application may be included in the application 5022.
The method disclosed in the embodiments of the present application may be applied to the processor 501 or implemented by the processor 501. The processor 501 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry in hardware or instructions in software in the processor 501. The processor 501 may be a general purpose processor, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 501 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied in a hardware decoding processor or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium in memory 502 and processor 501 reads information in memory 502 to perform the steps of the method described above in connection with its hardware.
In an exemplary embodiment, the processing device 500 may be implemented by one or more application specific integrated circuits (ASIC, application Specific Integrated Circuit), DSPs, programmable logic devices (PLD, programmable Logic Device), complex programmable logic devices (CPLD, complex Programmable Logic Device), field-programmable gate arrays (FPGA, field-Programmable Gate Array), general purpose processors, controllers, microcontrollers (MCU, micro Controller Unit), microprocessors (Microprocessor), or other electronic components for performing the aforementioned methods.
In an exemplary embodiment, the present application also provides a computer readable storage medium, e.g., memory 502 comprising a computer program executable by processor 501 of processing device 500 to perform the steps described in the foregoing methods. The computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, or CD-ROM; but may be a variety of devices including one or any combination of the above-described memories, such as a mobile phone, computer, tablet device, personal digital assistant, or the like.
A computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs: if the input/output memory management unit is configured with a first memory exclusion range of a register, establishing a mapping relation between the second memory exclusion range of the register and the second peripheral equipment based on the second memory exclusion range of the second peripheral equipment in a page table of the input/output memory management unit, wherein addresses of the second memory exclusion range of the register and addresses of the second memory exclusion range of the second peripheral equipment are in one-to-one correspondence;
the input/output memory management unit page table is used for responding to the memory access request of the second peripheral device, so that the second peripheral device accesses to the target memory address.
The computer program, when executed by the processor, further performs: if a memory access request sent by the second peripheral device is received, searching an input/output memory management unit page table corresponding to the second peripheral device based on a device identifier carried in the memory access request, so as to obtain a target memory address to be accessed by the second peripheral device.
The addresses of the first memory exclusion range of the register and the addresses of the first memory exclusion range of the first peripheral device are in one-to-one correspondence;
and the page table of the input/output memory management unit only stores mapping relations of the exclusion ranges of other peripheral devices and registers except the mapping relation of the first peripheral device and the first exclusion memory range of the register.
The computer program, when executed by the processor, further performs: and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to the second excluded memory range of the second peripheral device.
The computer program, when executed by the processor, further performs: in the starting-up process, inquiring the memory exclusion range corresponding to each peripheral device in the description table of the input/output memory management unit of the advanced configuration and power management interface;
if the search result has the memory exclusion range corresponding to the peripheral equipment, configuring the memory exclusion range of the register based on the memory exclusion range of the first peripheral equipment searched in the search result.
The computer program, when executed by the processor, further performs: and in the starting process, acquiring the page table of the input/output memory management unit for representing the mapping relation between the excluded memory range and the equipment identifier.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The methods disclosed in the several method embodiments provided in the present application may be arbitrarily combined without collision to obtain a new method embodiment.
The features disclosed in the several product embodiments provided in the present application may be combined arbitrarily without conflict to obtain new product embodiments.
The features disclosed in the several method or apparatus embodiments provided in the present application may be arbitrarily combined without conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. A method of processing, comprising:
if the input/output memory management unit is configured with a first memory exclusion range of a register, establishing a mapping relation between the second memory exclusion range of the register and the second peripheral equipment based on the second memory exclusion range of the second peripheral equipment in a page table of the input/output memory management unit, wherein addresses of the second memory exclusion range of the register and addresses of the second memory exclusion range of the second peripheral equipment are in one-to-one correspondence;
the input/output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device accesses a target memory address;
the addresses of the first memory exclusion range of the register and the addresses of the first memory exclusion range of the first peripheral device are in one-to-one correspondence;
and the page table of the input/output memory management unit only stores mapping relations of the exclusion ranges of other peripheral devices and registers except the mapping relation of the first peripheral device and the first exclusion memory range of the register.
2. The method of claim 1, further comprising:
if a memory access request sent by the second peripheral device is received, searching an input/output memory management unit page table corresponding to the second peripheral device based on a device identifier carried in the memory access request, so as to obtain a target memory address to be accessed by the second peripheral device.
3. The method of claim 1, further comprising:
and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to the second excluded memory range of the second peripheral device.
4. The method of claim 1, prior to determining whether the input-output memory management unit configures the excluded memory range of the register, further comprising:
in the starting-up process, inquiring the memory exclusion range corresponding to each peripheral device in an input/output memory management unit description table of the advanced configuration and power management interface;
if the search result has the memory exclusion range corresponding to the peripheral equipment, configuring the memory exclusion range of the register based on the memory exclusion range of the first peripheral equipment searched in the search result.
5. The method of claim 1, further comprising:
and in the starting process, acquiring the page table of the input/output memory management unit for representing the mapping relation between the excluded memory range and the equipment identifier.
6. A processing apparatus, comprising:
the judging unit is used for judging whether the input/output memory management unit is configured with the memory exclusion range of the register;
the device comprises an input/output memory management unit, a setting unit and a mapping unit, wherein the input/output memory management unit is used for setting a first memory exclusion range of a register, setting a mapping relation between the second memory exclusion range of the register and a second peripheral device based on the second memory exclusion range of the second peripheral device in a page table of the input/output memory management unit, and enabling addresses of the second memory exclusion range of the register and addresses of the second memory exclusion range of the second peripheral device to be in one-to-one correspondence; the input/output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device accesses a target memory address; the addresses of the first memory exclusion range of the register and the addresses of the first memory exclusion range of the first peripheral device are in one-to-one correspondence; and the page table of the input/output memory management unit only stores mapping relations of the exclusion ranges of other peripheral devices and registers except the mapping relation of the first peripheral device and the first exclusion memory range of the register.
7. The apparatus of claim 6, further comprising:
and the searching unit is used for searching an input/output memory management unit page table corresponding to the second peripheral device based on the device identifier carried in the memory access request if the memory access request sent by the second peripheral device is received, so as to obtain a target memory address to be accessed by the second peripheral device.
8. A processing apparatus, comprising: comprising the following steps: a processor and a memory for storing a computer program capable of running on the processor,
wherein the processor is adapted to perform the steps of the method of any of claims 1 to 5 when the computer program is run.
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